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GET /api/patches/95105/?format=api
{ "id": 95105, "url": "https://patches.dpdk.org/api/patches/95105/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210701071807.2018505-1-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210701071807.2018505-1-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210701071807.2018505-1-michaelba@nvidia.com", "date": "2021-07-01T07:18:07", "name": "compress/mlx5: fix memory region unregistration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8b5289fabf32e465c0f06fec89894d61254704a4", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210701071807.2018505-1-michaelba@nvidia.com/mbox/", "series": [ { "id": 17567, "url": "https://patches.dpdk.org/api/series/17567/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17567", "date": "2021-07-01T07:18:07", "name": "compress/mlx5: fix memory region unregistration", "version": 1, "mbox": "https://patches.dpdk.org/series/17567/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95105/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/95105/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A7FDA0A0C;\n\tThu, 1 Jul 2021 09:18:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0001A40141;\n\tThu, 1 Jul 2021 09:18:34 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2083.outbound.protection.outlook.com [40.107.236.83])\n by mails.dpdk.org (Postfix) with ESMTP id 6852A40040;\n Thu, 1 Jul 2021 09:18:33 +0200 (CEST)", "from DM3PR12CA0110.namprd12.prod.outlook.com (2603:10b6:0:55::30) by\n BL0PR12MB2388.namprd12.prod.outlook.com (2603:10b6:207:4a::30) with\n Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4264.19; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <stable@dpdk.org>", "Date": "Thu, 1 Jul 2021 10:18:07 +0300", "Message-ID": "<20210701071807.2018505-1-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b6e77e30-90cb-42f1-7dc7-08d93c606e7d", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2388:", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB238888F52AFFD65D7553A77FCC009@BL0PR12MB2388.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2449;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 4HstJEUpfhFTIlKd5m1epplGeebiJHeByjW1xSkslvi7LM5LgmO1+LWaBqBnvS38/eZi319c6GlyNKADhxr8mS1u8QBWuEWLBGfE221GyQyJe+bjJ4E+Wl+GuFrR/2pq5A3YcXN+zEC5tlhgSejUQh46e72d9HYoNkNIHUEL38bI44y8x/rDMj+MPzXKTGIdm4t3wA4L/I3/lYJofeYSz59UkRCnJ0o9MyLYSVUrDvnGXm6Z43ChcUj4JLMDzN6zLdTZWyaBuD8okEeowxTnvPkAeKtZEZM/V3vdbwYDpi3pUEygLi3jzJBJAfXBinGSbHRF6fI7A7w6keugtlz3V73G1teCzM8VsNXv825Yhgg42NylnGRcnN5R4Eup1QYcPY3Twc4E4TsVCkA0o9l1sbwN05dVhQwFh/nf7tlauieF3uVexW10XBr6iNJN+nntanTwQoYWlS96l3KQAX7BpYr4L/ay0P/h3nrN2lGMiDk9Zax7Wx1mzFHy2wQ13pUni+BBhvEkP03iFxPjpLEfJLs1+4lZYESHiJduKKnMDkU8fnQUnbKlkTvIQX85wtekqciCC4DfKP0ryuQxYWiYIp7BJBi7lpb6Y0ScYXWZ8Eb05oXceZCjMr/E2pBgTiBOWe9NRJutt1q3aGDL39qeBx118j1qLSpQXj3uDdwc4fxdk5Efg9hDvoCWdJT+peNjsMrVkw6vAwbh99e7A1VIIg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(136003)(39860400002)(346002)(396003)(36840700001)(46966006)(478600001)(356005)(82740400003)(7636003)(36756003)(83380400001)(450100002)(26005)(4326008)(16526019)(186003)(7696005)(47076005)(36860700001)(54906003)(2906002)(316002)(6916009)(336012)(2616005)(426003)(55016002)(86362001)(1076003)(8676002)(82310400003)(70586007)(5660300002)(8936002)(6286002)(6666004)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Jul 2021 07:18:31.6821 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b6e77e30-90cb-42f1-7dc7-08d93c606e7d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT014.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2388", "Subject": "[dpdk-dev] [PATCH] compress/mlx5: fix memory region unregistration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The issue can cause illegal physical address access while a huge-page A\nis released and huge-page B is allocated on the same virtual address.\nThe old MR can be matched using the virtual address of huge-page B but\nthe HW will access the physical address of huge-page A which is no more\npart of the DPDK process.\n\nRegister a driver callback for memory event in order to free out all the\nMRs of memory that is going to be freed from the dpdk process.\n\nFixes: f8c97babc9f4 (\"compress/mlx5: add data-path functions\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/compress/mlx5/mlx5_compress.c | 83 ++++++++++++++++++++++++++-\n 1 file changed, 80 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 80c564f10b..f5f51c0ebe 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -258,6 +258,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Can't change SQ state to ready.\");\n \t\tgoto err;\n \t}\n+\t/* Save pointer of global generation number to check memory event. */\n+\tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n \tDRV_LOG(INFO, \"QP %u: SQN=0x%X CQN=0x%X entries num = %u\",\n \t\t(uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);\n \treturn 0;\n@@ -428,6 +430,40 @@ static struct rte_compressdev_ops mlx5_compress_ops = {\n \t.stream_free\t\t= NULL,\n };\n \n+/**\n+ * Query LKey from a packet buffer for QP. If not found, add the mempool.\n+ *\n+ * @param priv\n+ * Pointer to the priv object.\n+ * @param addr\n+ * Search key.\n+ * @param mr_ctrl\n+ * Pointer to per-queue MR control structure.\n+ * @param ol_flags\n+ * Mbuf offload features.\n+ *\n+ * @return\n+ * Searched LKey on success, UINT32_MAX on no match.\n+ */\n+static __rte_always_inline uint32_t\n+mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,\n+\t\t struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)\n+{\n+\tuint32_t lkey;\n+\n+\t/* Check generation bit to see if there's any change on existing MRs. */\n+\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n+\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n+\t/* Linear search on MR cache array. */\n+\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n+\t\t\t\t MLX5_MR_CACHE_N, addr);\n+\tif (likely(lkey != UINT32_MAX))\n+\t\treturn lkey;\n+\t/* Take slower bottom-half on miss. */\n+\treturn mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,\n+\t\t\t\t !!(ol_flags & EXT_ATTACHED_MBUF));\n+}\n+\n static __rte_always_inline uint32_t\n mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,\n \t\t volatile struct mlx5_wqe_dseg *restrict dseg,\n@@ -437,9 +473,8 @@ mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,\n \tuintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);\n \n \tdseg->bcount = rte_cpu_to_be_32(len);\n-\tdseg->lkey = mlx5_mr_addr2mr_bh(qp->priv->pd, 0, &qp->priv->mr_scache,\n-\t\t\t\t\t&qp->mr_ctrl, addr,\n-\t\t\t\t\t!!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\tdseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl,\n+\t\t\t\t\t mbuf->ol_flags);\n \tdseg->pbuf = rte_cpu_to_be_64(addr);\n \treturn dseg->lkey;\n }\n@@ -711,6 +746,40 @@ mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)\n \treturn 0;\n }\n \n+/**\n+ * Callback for memory event.\n+ *\n+ * @param event_type\n+ * Memory event type.\n+ * @param addr\n+ * Address of memory.\n+ * @param len\n+ * Size of memory.\n+ */\n+static void\n+mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n+\t\t\t size_t len, void *arg __rte_unused)\n+{\n+\tstruct mlx5_compress_priv *priv;\n+\n+\t/* Must be called from the primary process. */\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tswitch (event_type) {\n+\tcase RTE_MEM_EVENT_FREE:\n+\t\tpthread_mutex_lock(&priv_list_lock);\n+\t\t/* Iterate all the existing mlx5 devices. */\n+\t\tTAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)\n+\t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n+\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t addr, len);\n+\t\tpthread_mutex_unlock(&priv_list_lock);\n+\t\tbreak;\n+\tcase RTE_MEM_EVENT_ALLOC:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n /**\n * DPDK callback to register a PCI device.\n *\n@@ -804,6 +873,11 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,\n \t}\n \tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n \tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n+\t/* Register callback function for global shared MR cache management. */\n+\tif (TAILQ_EMPTY(&mlx5_compress_priv_list))\n+\t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\tmlx5_compress_mr_mem_event_cb,\n+\t\t\t\t\t\tNULL);\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n@@ -834,6 +908,9 @@ mlx5_compress_pci_remove(struct rte_pci_device *pdev)\n \t\tTAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n \tif (priv) {\n+\t\tif (TAILQ_EMPTY(&mlx5_compress_priv_list))\n+\t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\t\t NULL);\n \t\tmlx5_mr_release_cache(&priv->mr_scache);\n \t\tmlx5_compress_hw_global_release(priv);\n \t\trte_compressdev_pmd_destroy(priv->cdev);\n", "prefixes": [] }