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GET /api/patches/95095/?format=api
{ "id": 95095, "url": "https://patches.dpdk.org/api/patches/95095/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210701063916.2016763-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210701063916.2016763-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210701063916.2016763-3-michaelba@nvidia.com", "date": "2021-07-01T06:39:15", "name": "[v2,3/4] vdpa/mlx5: fix constant type in QP creation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "798401729e3189c638efd0304c168a6b23f11e02", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210701063916.2016763-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 17559, "url": "https://patches.dpdk.org/api/series/17559/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17559", "date": "2021-07-01T06:39:13", "name": "[v2,1/4] regex/mlx5: fix size of setup constants", "version": 2, "mbox": "https://patches.dpdk.org/series/17559/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95095/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95095/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CE3A5A0A0C;\n\tThu, 1 Jul 2021 08:40:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0B71B412B5;\n\tThu, 1 Jul 2021 08:40:06 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam07on2068.outbound.protection.outlook.com [40.107.95.68])\n by mails.dpdk.org (Postfix) with ESMTP id B8839412A8;\n Thu, 1 Jul 2021 08:40:04 +0200 (CEST)", "from MWHPR17CA0087.namprd17.prod.outlook.com (2603:10b6:300:c2::25)\n by DM6PR12MB4894.namprd12.prod.outlook.com (2603:10b6:5:209::12) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.18; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <stable@dpdk.org>", "Date": "Thu, 1 Jul 2021 09:39:15 +0300", "Message-ID": "<20210701063916.2016763-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210701063916.2016763-1-michaelba@nvidia.com>", "References": "<20210601071122.1612432-1-michaelba@nvidia.com>\n <20210701063916.2016763-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "85df34fe-ae5f-434a-08b0-08d93c5b0e3a", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB4894:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB4894BF4E71556E95E2FB1661CC009@DM6PR12MB4894.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4303;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jwS8YSAnm60pCB++QalICUqibVV3y2bLnHeJqhTJgDDJtDuvw8qe836rsjm6AmsLXngJ4AvsRhN1CQNL8K24LT2NmxGwnocqjdKBNsW5zp1MMtMaTnBcIuM5tht6bYLAmAyIuOetCL61cXZt991DTW2yjqSlLG/8yVvCkqeXl4QtAeThlnOzh4ztCDlhK5sPaWs6iPhrgGTJJoskHq679RCrc/IRd1XjF6v/9/I6Ruvyo2SGAVnMOYWCyUveWlNcivEs8WTP1Z8bcMIKf9uWaIeA9K6XROOvg9khz8VwGeUN7cmziudr/uiiuw2N2H1AoiSf9sz1XOdvpBN3SaV+1kFfOdGbabP4oLfwodZwgpES4IiOCrcMCFE+JL+u/TibdUvOAIipjNd7s7Y9433I/kcAGkQOrpAWGcUb5EgeywLfOc6BY8JcfZ9fY1Yh9w9Ufx0vJvHbASkrowJm8r9ZQZMrj66pu4OABpJ0tsbZQsFmIiBS7Nlc13U7Vc86vIYEfvCEDPneiVbCd/24Wg9FrDwPea68riEhhjKHAevkq3/GdShP86+/QXq+ACS5AV249zueTHNqi9q25mK55r833QkFtOX1aOPGkfhGpGXowXJnOCRIl+w/Mys9hEPW4HYORwj0PutUX8W6+JCPfIrB+Vc2P4t4z3gVcZsa2Ex8PUAawndAkiuHZ/cRZyEKjhK6HJl4E8y24QudkRaT1s1JGg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(396003)(39860400002)(136003)(376002)(36840700001)(46966006)(336012)(426003)(6916009)(7696005)(316002)(7636003)(5660300002)(356005)(70206006)(70586007)(55016002)(2906002)(54906003)(6666004)(478600001)(4326008)(26005)(82310400003)(186003)(83380400001)(16526019)(8936002)(1076003)(2616005)(82740400003)(86362001)(36756003)(47076005)(450100002)(6286002)(8676002)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Jul 2021 06:40:02.6891 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 85df34fe-ae5f-434a-08b0-08d93c5b0e3a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT056.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4894", "Subject": "[dpdk-dev] [PATCH v2 3/4] vdpa/mlx5: fix constant type in QP\n creation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The mlx5_vdpa_event_qp_create function makes shifting to the numeric\nconstant 1, then multiplies it by another constant and finally assigns\nit into a uint64_t variable.\n\nThe numeric constant type is an int with a 32-bit sign. if after\nshifting , its MSB (bit of sign) will change, the uint64 variable will\nget into it a different value than what the function intended it to get.\n\nSet the numeric constant 1 to be uint64_t in the first place.\n\nFixes: 8395927cdfaf (\"vdpa/mlx5: prepare HW queues\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 88f6a4256d..3541c652ce 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -629,8 +629,8 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n \tattr.wq_umem_id = eqp->umem_obj->umem_id;\n \tattr.wq_umem_offset = 0;\n \tattr.dbr_umem_id = eqp->umem_obj->umem_id;\n-\tattr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;\n \tattr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);\n+\tattr.dbr_address = RTE_BIT64(log_desc_n) * MLX5_WSEG_SIZE;\n \teqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n \tif (!eqp->sw_qp) {\n \t\tDRV_LOG(ERR, \"Failed to create SW QP(%u).\", rte_errno);\n", "prefixes": [ "v2", "3/4" ] }