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GET /api/patches/95068/?format=api
{ "id": 95068, "url": "https://patches.dpdk.org/api/patches/95068/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210630124609.8711-15-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210630124609.8711-15-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210630124609.8711-15-suanmingm@nvidia.com", "date": "2021-06-30T12:46:01", "name": "[v2,14/22] net/mlx5: adjust the hash bucket size", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "eb4b3610c9705f17ded55c37f6e9868f353f8f92", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210630124609.8711-15-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17549, "url": "https://patches.dpdk.org/api/series/17549/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17549", "date": "2021-06-30T12:45:47", "name": "net/mlx5: insertion rate optimization", "version": 2, "mbox": "https://patches.dpdk.org/series/17549/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95068/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95068/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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"Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR12MB1243", "Subject": "[dpdk-dev] [PATCH v2 14/22] net/mlx5: adjust the hash bucket size", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "With the new per core optimization to the list, the hash bucket size\ncan be tuned to a more accurate number.\n\nThis commit adjusts the hash bucket size.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 2 +-\n drivers/net/mlx5/mlx5.c | 2 +-\n drivers/net/mlx5/mlx5_defs.h | 6 +++---\n drivers/net/mlx5/mlx5_flow.c | 5 ++---\n 4 files changed, 7 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex cf573a9a4d..a82dc4db00 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -50,7 +50,7 @@\n #include \"mlx5_nl.h\"\n #include \"mlx5_devx.h\"\n \n-#define MLX5_TAGS_HLIST_ARRAY_SIZE 8192\n+#define MLX5_TAGS_HLIST_ARRAY_SIZE\t(1 << 15)\n \n #ifndef HAVE_IBV_MLX5_MOD_MPW\n #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 713accf675..8fb7f4442d 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -373,7 +373,7 @@ static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {\n #define MLX5_FLOW_MIN_ID_POOL_SIZE 512\n #define MLX5_ID_GENERATION_ARRAY_FACTOR 16\n \n-#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096\n+#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024\n \n /**\n * Decide whether representor ID is a HPF(host PF) port on BF2.\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 906aa43c5a..ca67ce8213 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -178,15 +178,15 @@\n \t\t\t\t sizeof(struct rte_ipv4_hdr))\n \n /* Size of the simple hash table for metadata register table. */\n-#define MLX5_FLOW_MREG_HTABLE_SZ 4096\n+#define MLX5_FLOW_MREG_HTABLE_SZ 64\n #define MLX5_FLOW_MREG_HNAME \"MARK_COPY_TABLE\"\n #define MLX5_DEFAULT_COPY_ID UINT32_MAX\n \n /* Size of the simple hash table for header modify table. */\n-#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 16)\n+#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15)\n \n /* Size of the simple hash table for encap decap table. */\n-#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 16)\n+#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12)\n \n /* Hairpin TX/RX queue configuration parameters. */\n #define MLX5_HAIRPIN_QUEUE_STRIDE 6\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex e6b71a87a0..cb8161f668 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -8625,7 +8625,7 @@ mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev,\n \t\tDRV_LOG(ERR, \"Tunnel ID %d exceed max limit.\", id);\n \t\treturn NULL;\n \t}\n-\ttunnel->groups = mlx5_hlist_create(\"tunnel groups\", 1024, false, true,\n+\ttunnel->groups = mlx5_hlist_create(\"tunnel groups\", 64, false, true,\n \t\t\t\t\t priv->sh,\n \t\t\t\t\t mlx5_flow_tunnel_grp2tbl_create_cb,\n \t\t\t\t\t mlx5_flow_tunnel_grp2tbl_match_cb,\n@@ -8734,8 +8734,7 @@ int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh)\n \t\treturn -ENOMEM;\n \tLIST_INIT(&thub->tunnels);\n \trte_spinlock_init(&thub->sl);\n-\tthub->groups = mlx5_hlist_create(\"flow groups\",\n-\t\t\t\t\t rte_align32pow2(MLX5_MAX_TABLES),\n+\tthub->groups = mlx5_hlist_create(\"flow groups\", 64,\n \t\t\t\t\t false, true, sh,\n \t\t\t\t\t mlx5_flow_tunnel_grp2tbl_create_cb,\n \t\t\t\t\t mlx5_flow_tunnel_grp2tbl_match_cb,\n", "prefixes": [ "v2", "14/22" ] }