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GET /api/patches/95058/?format=api
{ "id": 95058, "url": "https://patches.dpdk.org/api/patches/95058/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210630124609.8711-6-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210630124609.8711-6-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210630124609.8711-6-suanmingm@nvidia.com", "date": "2021-06-30T12:45:52", "name": "[v2,05/22] net/mlx5: optimize modify header action memory", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7a38ba8aa91f5e1d91811184a09cbdecb73785c0", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210630124609.8711-6-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17549, "url": "https://patches.dpdk.org/api/series/17549/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17549", "date": "2021-06-30T12:45:47", "name": "net/mlx5: insertion rate optimization", "version": 2, "mbox": "https://patches.dpdk.org/series/17549/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95058/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95058/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1CA58A0A0F;\n\tWed, 30 Jun 2021 14:47:00 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 62C184127C;\n\tWed, 30 Jun 2021 14:46:49 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2081.outbound.protection.outlook.com [40.107.244.81])\n by mails.dpdk.org (Postfix) with ESMTP id 225DE41273\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Wed, 30 Jun 2021 15:45:52 +0300", "Message-ID": "<20210630124609.8711-6-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210630124609.8711-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210630124609.8711-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "6ab66921-3ba7-4a6e-fdb9-08d93bc51e38", "X-MS-TrafficTypeDiagnostic": "BN7PR12MB2740:", "X-Microsoft-Antispam-PRVS": "\n <BN7PR12MB27408B149A03B6200617BC63C1019@BN7PR12MB2740.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7691;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ouwwREd38MJjcCCWU9WgjUmmBtplzdGfbIMjzRKJpl/nBi7YOj4l+fpl/+7G4ea4g/M9j2Jdnz3cX+xiOb644OcgfNwN8yocSL49lSLpepi9HKXV9DhgV3+Vl7qL78mIa1QByDA7o3Z5epmCSiR7Z2fOnycVNvitiiMTYTsY2wK9qt6Il07jD7ROnWuzd+uncy5HzGjLGOOFjL0hv9krAMCOevW+9I2BOxnQ/g/dPsA6KEfw4jVWdeAyEr7C3rQmj40wwKB67xdKGGLoyPMsQBdK298cT+rQQWUKuiEj5fBC86+KhLt0YvEU8I51Um3WM7xCUQoOZa5wmG5K1vvR4eLmedx/vs41nBNiraQTa2eumpJCVfY3bNtugQ3Lypyg2Kp5HMv40tO+Jq00qBQ1XnCluNVP16BClMW4MaBjTCL7ZjCWmLEM+i+6sIG/PLmjPdSBwxyNdF4Sa2JypNIziWz04QaQWHTf7wM6UL5AYW4IsMkMzrW3Ovh7C4zO1xarZOdxRbpujFcdWM5S9gWzX/vKMJWqDI94DMw1CCQZSpYczi2L3mSOOyO1aReTxB1zUY0EtCAbKrQlRrBd4hBVZ4JsBGYWbj5bVfNWsyP7YrMyCM+QERPgixjb+yLaLHcuQk5XkLjoeAEpO6fjrA90yTH9LjN4o8WkjRzjNatwyirYY7ZHl6Pki/QeZ1+oK0Fv2tp8Wcm8LnoRUFHcrSdTwA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(39860400002)(396003)(346002)(376002)(46966006)(36840700001)(26005)(356005)(55016002)(426003)(36756003)(186003)(16526019)(83380400001)(2616005)(6636002)(6286002)(6666004)(5660300002)(336012)(7696005)(54906003)(36860700001)(1076003)(70586007)(70206006)(8676002)(47076005)(7636003)(478600001)(86362001)(110136005)(2906002)(4326008)(316002)(8936002)(82740400003)(82310400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jun 2021 12:46:44.9564 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6ab66921-3ba7-4a6e-fdb9-08d93bc51e38", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT042.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR12MB2740", "Subject": "[dpdk-dev] [PATCH v2 05/22] net/mlx5: optimize modify header action\n memory", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Matan Azrad <matan@nvidia.com>\n\nDefine the types of the modify header action fields to be with the\nminimum size needed for the optional values range.\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_glue.h | 1 +\n drivers/net/mlx5/linux/mlx5_flow_os.h | 3 ++-\n drivers/net/mlx5/mlx5_flow.h | 6 +++---\n drivers/net/mlx5/mlx5_flow_dv.c | 13 ++++++-------\n 4 files changed, 12 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h\nindex 840d8cf57f..a186ee577f 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.h\n+++ b/drivers/common/mlx5/linux/mlx5_glue.h\n@@ -78,6 +78,7 @@ struct mlx5dv_devx_async_cmd_hdr;\n enum mlx5dv_dr_domain_type { unused, };\n struct mlx5dv_dr_domain;\n struct mlx5dv_dr_action;\n+#define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1\n #endif\n \n #ifndef HAVE_MLX5DV_DR_DEVX_PORT\ndiff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h\nindex cee685015b..1926d26410 100644\n--- a/drivers/net/mlx5/linux/mlx5_flow_os.h\n+++ b/drivers/net/mlx5/linux/mlx5_flow_os.h\n@@ -225,7 +225,8 @@ mlx5_flow_os_create_flow_action_modify_header(void *ctx, void *domain,\n \t\t\t(struct mlx5_flow_dv_modify_hdr_resource *)resource;\n \n \t*action = mlx5_glue->dv_create_flow_action_modify_header\n-\t\t\t\t\t(ctx, res->ft_type, domain, res->flags,\n+\t\t\t\t\t(ctx, res->ft_type, domain, res->root ?\n+\t\t\t\t\t MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL : 0,\n \t\t\t\t\t actions_len, (uint64_t *)res->actions);\n \treturn (*action) ? 0 : -1;\n }\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex d9b6acaafd..81c95e0beb 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -523,11 +523,11 @@ struct mlx5_flow_dv_modify_hdr_resource {\n \tvoid *action; /**< Modify header action object. */\n \t/* Key area for hash list matching: */\n \tuint8_t ft_type; /**< Flow table type, Rx or Tx. */\n-\tuint32_t actions_num; /**< Number of modification actions. */\n-\tuint64_t flags; /**< Flags for RDMA API. */\n+\tuint8_t actions_num; /**< Number of modification actions. */\n+\tbool root; /**< Whether action is in root table. */\n \tstruct mlx5_modification_cmd actions[];\n \t/**< Modification actions. */\n-};\n+} __rte_packed;\n \n /* Modify resource key of the hash organization. */\n union mlx5_flow_modify_hdr_key {\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 67f7243503..784ec11dea 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -5000,21 +5000,21 @@ flow_dv_validate_action_port_id(struct rte_eth_dev *dev,\n *\n * @param dev\n * Pointer to rte_eth_dev structure.\n- * @param flags\n- * Flags bits to check if root level.\n+ * @param root\n+ * Whether action is on root table.\n *\n * @return\n * Max number of modify header actions device can support.\n */\n static inline unsigned int\n flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,\n-\t\t\t uint64_t flags)\n+\t\t\t bool root)\n {\n \t/*\n \t * There's no way to directly query the max capacity from FW.\n \t * The maximal value on root table should be assumed to be supported.\n \t */\n-\tif (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))\n+\tif (!root)\n \t\treturn MLX5_MAX_MODIFY_NUM;\n \telse\n \t\treturn MLX5_ROOT_TBL_MODIFY_NUM;\n@@ -5582,10 +5582,9 @@ flow_dv_modify_hdr_resource_register\n \t};\n \tuint64_t key64;\n \n-\tresource->flags = dev_flow->dv.group ? 0 :\n-\t\t\t MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;\n+\tresource->root = !dev_flow->dv.group;\n \tif (resource->actions_num > flow_dv_modify_hdr_action_max(dev,\n-\t\t\t\t resource->flags))\n+\t\t\t\t\t\t\t\tresource->root))\n \t\treturn rte_flow_error_set(error, EOVERFLOW,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t \"too many modify header items\");\n", "prefixes": [ "v2", "05/22" ] }