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GET /api/patches/95041/?format=api
{ "id": 95041, "url": "https://patches.dpdk.org/api/patches/95041/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210630070452.14055-2-getelson@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210630070452.14055-2-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210630070452.14055-2-getelson@nvidia.com", "date": "2021-06-30T07:04:50", "name": "[1/3] common/mlx5: query for hardware capability to offload IPv4 IHL field", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f62821ba576ad711da32d864743a563f4aae7c43", "submitter": { "id": 1882, "url": "https://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210630070452.14055-2-getelson@nvidia.com/mbox/", "series": [ { "id": 17542, "url": "https://patches.dpdk.org/api/series/17542/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17542", "date": "2021-06-30T07:04:49", "name": "net/mlx5: add flow rule match for IPv4 IHL field", "version": 1, "mbox": "https://patches.dpdk.org/series/17542/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95041/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95041/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 72EA3A0A0F;\n\tWed, 30 Jun 2021 09:05:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5FA6B41236;\n\tWed, 30 Jun 2021 09:05:18 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2054.outbound.protection.outlook.com [40.107.94.54])\n by mails.dpdk.org (Postfix) with ESMTP id 488CE41235\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Shahaf Shuler\n <shahafs@nvidia.com>", "Date": "Wed, 30 Jun 2021 10:04:50 +0300", "Message-ID": "<20210630070452.14055-2-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20210630070452.14055-1-getelson@nvidia.com>", "References": "<20210630070452.14055-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "4d34e1ec-1739-4e49-4e48-08d93b956951", "X-MS-TrafficTypeDiagnostic": "CY4PR1201MB0007:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR1201MB0007B32E8F4C341362DF8B44A5019@CY4PR1201MB0007.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2657;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n N5dUQEu3C9w4q7y8LktyNw52p+VLTGHmzbzTAx+/UjPVqJLknWkx6oYjqwoxF8IQMDbfnx7XqQ4ZMz0j1R89OKxmtjWLckQ7gNKuIP9mItdarUEsJ6WBXcsJ4Q98Bq/Ko/kAjN86s1LTPE0xCTe/HZ0vPBSlM3epTsaOB+TJWHo1GF/uJp4e35xSXw1Tf9OSL0drzzp0XAzMlzhuAvErclWfAubv/aLuwdME5cF3dbOPpKLxBAbSG3OAieVIFDgcv1s1CgaaVu5PNjbiI1UlJUTnu+cq2Puq8fweyaFecfNE03py3/1KF6sWDmNCu7DymATj4Vd2cOXifGprmO8JtPoElpiJioNMONmUXFTaDl6qX3U1mejuglp2gx7WqNPjvIkTIUzgxMswBIaHudNlV+p2PALGqYj82XaiTlQJq4lQXiOSV5q5SqmXKNnXOPYJgmu/SpAtUq7gqRMxqiAtPEOjCLruchMB+Ob21cON7PR38ZFfkXjOktAOSRdQ5UrOiSyYuWH/MRWPK70iSpo06pxVaM81/axJsT0asVpq/moXigbvZO8+y4fIYFLhWpaRuJZLXf/OLqTxH+OLA5x7lNo8oPaHKacUHNnwRGL6w72rHMYCkKbkFjM2k6zYLYulA8qH8Ny+JVr/DfGTVarkN7v5J22gOwAAjavlgt2zmxd+ev3DccSpN22z6OCllLn5bOlXc4SHAguYLQXM+MY1Qw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(396003)(376002)(39860400002)(36840700001)(46966006)(5660300002)(1076003)(356005)(26005)(36756003)(70586007)(8676002)(70206006)(316002)(6286002)(82310400003)(7636003)(6666004)(426003)(55016002)(2906002)(107886003)(54906003)(86362001)(83380400001)(2616005)(7696005)(4326008)(478600001)(186003)(16526019)(47076005)(36860700001)(6916009)(82740400003)(8936002)(336012);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jun 2021 07:05:15.1618 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4d34e1ec-1739-4e49-4e48-08d93b956951", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT040.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR1201MB0007", "Subject": "[dpdk-dev] [PATCH 1/3] common/mlx5: query for hardware capability\n to offload IPv4 IHL field", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The patch queries MLX5 port hardware if it is capable to offload\nIPv4 IHL field.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++\n 2 files changed, 8 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex f5914bce32..9070691332 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -948,6 +948,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t(flow_table_nic_cap, hcattr,\n \t\t flow_table_properties_nic_receive.log_max_ft_sampler_num);\n \tattr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);\n+\tattr->inner_ipv4_ihl = MLX5_GET\n+\t\t(flow_table_nic_cap, hcattr,\n+\t\t ft_field_support_2_nic_receive.inner_ipv4_ihl);\n+\tattr->outer_ipv4_ihl = MLX5_GET\n+\t\t(flow_table_nic_cap, hcattr,\n+\t\t ft_field_support_2_nic_receive.outer_ipv4_ihl);\n \t/* Query HCA offloads for Ethernet protocol. */\n \tmemset(in, 0, sizeof(in));\n \tmemset(out, 0, sizeof(out));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex f8a17b886b..034c40b49c 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -148,6 +148,8 @@ struct mlx5_hca_attr {\n \tuint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n+\tuint32_t inner_ipv4_ihl:1;\n+\tuint32_t outer_ipv4_ihl:1;\n \tuint32_t geneve_tlv_opt;\n \tuint32_t cqe_compression:1;\n \tuint32_t mini_cqe_resp_flow_tag:1;\n", "prefixes": [ "1/3" ] }