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GET /api/patches/94950/?format=api
{ "id": 94950, "url": "https://patches.dpdk.org/api/patches/94950/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624952076-30928-6-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624952076-30928-6-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624952076-30928-6-git-send-email-anoobj@marvell.com", "date": "2021-06-29T07:34:33", "name": "[v3,5/8] crypto/cnxk: add asymmetric session ops", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9e4717e74143b30d35765d09d66686576df69ff2", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624952076-30928-6-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17512, "url": "https://patches.dpdk.org/api/series/17512/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17512", "date": "2021-06-29T07:34:28", "name": "Add lookaside IPsec and asymmetric in cnxk crypto PMDs", "version": 3, "mbox": "https://patches.dpdk.org/series/17512/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94950/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94950/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 60A9FA0A0C;\n\tTue, 29 Jun 2021 09:35:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 552F441193;\n\tTue, 29 Jun 2021 09:35:21 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 8B7534119E\n for <dev@dpdk.org>; Tue, 29 Jun 2021 09:35:19 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15T7QRdL006855; Tue, 29 Jun 2021 00:35:18 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 39fuw50s7j-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 29 Jun 2021 00:35:18 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 29 Jun 2021 00:35:16 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 29 Jun 2021 00:35:16 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 922595B6928;\n Tue, 29 Jun 2021 00:35:13 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=pWTTYODcNVGd/Su10C7vGNibIvcYBI14JAIBBUro/Xg=;\n b=Mfk2Mlv84Syt5bln1mvnrYb0V61ldDIJsQfpWSoK56tA+iVmN44eUfblh/deNtd1BV5M\n GchuA1ShfKahU1e4GlwDkKxUnzkVkYQAcrpZFmWvOgOCqjSlq69hb3aW/v7+pB3TDeLy\n SGST3F5dQL4GvVoH/48suB+GxGizLUkPUG+oJkHdejvkWdXnAKwLXmYJEj2NCPBBpIlo\n pmmACwmYAUfyvNXHp9NpRqFHxO/+P9CJWGjZcdTZZOABZZrP3WhXC+51+GhrvbgvLzx7\n LIcU/kMxHry8yBnnyof3zJyWMXmsG10LfxB7h5kk4qKwZJewu0qhgv5bDEKngCgfQnkZ Pg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Kiran Kumar K <kirankumark@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Tue, 29 Jun 2021 13:04:33 +0530", "Message-ID": "<1624952076-30928-6-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624952076-30928-1-git-send-email-anoobj@marvell.com>", "References": "<1624601708-29991-1-git-send-email-anoobj@marvell.com>\n <1624952076-30928-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "5DDhGBxHuFVtfEvzG4SB-wAgPTqzFrY9", "X-Proofpoint-GUID": "5DDhGBxHuFVtfEvzG4SB-wAgPTqzFrY9", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-29_02:2021-06-25,\n 2021-06-29 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 5/8] crypto/cnxk: add asymmetric session ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdd asymmetric crypto session ops.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n doc/guides/cryptodevs/features/cn10k.ini | 13 ++\n doc/guides/cryptodevs/features/cn9k.ini | 13 ++\n drivers/crypto/cnxk/cn10k_cryptodev.c | 2 +\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 6 +-\n drivers/crypto/cnxk/cn9k_cryptodev.c | 4 +-\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 6 +-\n drivers/crypto/cnxk/cnxk_ae.h | 211 ++++++++++++++++++++++++++++++\n drivers/crypto/cnxk/cnxk_cryptodev.h | 4 +-\n drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 106 +++++++++++++++\n drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 8 ++\n 10 files changed, 365 insertions(+), 8 deletions(-)\n create mode 100644 drivers/crypto/cnxk/cnxk_ae.h", "diff": "diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex b268f84..f5552fe 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -5,6 +5,7 @@\n ;\n [Features]\n Symmetric crypto = Y\n+Asymmetric crypto = Y\n Sym operation chaining = Y\n HW Accelerated = Y\n Protocol offload = Y\n@@ -65,3 +66,15 @@ AES GCM (128) = Y\n AES GCM (192) = Y\n AES GCM (256) = Y\n CHACHA20-POLY1305 = Y\n+\n+;\n+; Supported Asymmetric algorithms of the 'cn10k' crypto driver.\n+;\n+[Asymmetric]\n+RSA = Y\n+DSA =\n+Modular Exponentiation = Y\n+Modular Inversion =\n+Diffie-hellman =\n+ECDSA = Y\n+ECPM = Y\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex 7b310e6..d69dbe8 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -5,6 +5,7 @@\n ;\n [Features]\n Symmetric crypto = Y\n+Asymmetric crypto = Y\n Sym operation chaining = Y\n HW Accelerated = Y\n In Place SGL = Y\n@@ -64,3 +65,15 @@ AES GCM (128) = Y\n AES GCM (192) = Y\n AES GCM (256) = Y\n CHACHA20-POLY1305 = Y\n+\n+;\n+; Supported Asymmetric algorithms of the 'cn9k' crypto driver.\n+;\n+[Asymmetric]\n+RSA = Y\n+DSA =\n+Modular Exponentiation = Y\n+Modular Inversion =\n+Diffie-hellman =\n+ECDSA = Y\n+ECPM = Y\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c\nindex 22ae810..10a621f 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c\n@@ -92,7 +92,9 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->driver_id = cn10k_cryptodev_driver_id;\n \n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\t RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |\n \t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\t RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT |\n \t\t\t RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n \t\t\t RTE_CRYPTODEV_FF_IN_PLACE_SGL |\n \t\t\t RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 8005a25..aa615b2 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -426,8 +426,8 @@ struct rte_cryptodev_ops cn10k_cpt_ops = {\n \t.sym_session_clear = cnxk_cpt_sym_session_clear,\n \n \t/* Asymmetric crypto ops */\n-\t.asym_session_get_size = NULL,\n-\t.asym_session_configure = NULL,\n-\t.asym_session_clear = NULL,\n+\t.asym_session_get_size = cnxk_ae_session_size_get,\n+\t.asym_session_configure = cnxk_ae_session_cfg,\n+\t.asym_session_clear = cnxk_ae_session_clear,\n \n };\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c\nindex d3dc084..e74e739 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c\n@@ -83,6 +83,7 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tcnxk_cpt_caps_populate(vf);\n \n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\t RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |\n \t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\t RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n \t\t\t RTE_CRYPTODEV_FF_IN_PLACE_SGL |\n@@ -90,7 +91,8 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n \t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\t RTE_CRYPTODEV_FF_SYM_SESSIONLESS |\n-\t\t\t RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED;\n+\t\t\t RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED |\n+\t\t\t RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;\n \n \tcn9k_cpt_set_enqdeq_fns(dev);\n \ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex b939d99..6d1537b 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -312,8 +312,8 @@ struct rte_cryptodev_ops cn9k_cpt_ops = {\n \t.sym_session_clear = cnxk_cpt_sym_session_clear,\n \n \t/* Asymmetric crypto ops */\n-\t.asym_session_get_size = NULL,\n-\t.asym_session_configure = NULL,\n-\t.asym_session_clear = NULL,\n+\t.asym_session_get_size = cnxk_ae_session_size_get,\n+\t.asym_session_configure = cnxk_ae_session_cfg,\n+\t.asym_session_clear = cnxk_ae_session_clear,\n \n };\ndiff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h\nnew file mode 100644\nindex 0000000..e3dd63b\n--- /dev/null\n+++ b/drivers/crypto/cnxk/cnxk_ae.h\n@@ -0,0 +1,211 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CNXK_AE_H_\n+#define _CNXK_AE_H_\n+\n+#include <rte_common.h>\n+#include <rte_crypto_asym.h>\n+#include <rte_malloc.h>\n+\n+#include \"roc_api.h\"\n+#include \"cnxk_cryptodev_ops.h\"\n+\n+struct cnxk_ae_sess {\n+\tenum rte_crypto_asym_xform_type xfrm_type;\n+\tunion {\n+\t\tstruct rte_crypto_rsa_xform rsa_ctx;\n+\t\tstruct rte_crypto_modex_xform mod_ctx;\n+\t\tstruct roc_ae_ec_ctx ec_ctx;\n+\t};\n+\tuint64_t *cnxk_fpm_iova;\n+\tstruct roc_ae_ec_group **ec_grp;\n+\tuint64_t cpt_inst_w7;\n+};\n+\n+static __rte_always_inline void\n+cnxk_ae_modex_param_normalize(uint8_t **data, size_t *len)\n+{\n+\tsize_t i;\n+\n+\t/* Strip leading NUL bytes */\n+\tfor (i = 0; i < *len; i++) {\n+\t\tif ((*data)[i] != 0)\n+\t\t\tbreak;\n+\t}\n+\t*data += i;\n+\t*len -= i;\n+}\n+\n+static __rte_always_inline int\n+cnxk_ae_fill_modex_params(struct cnxk_ae_sess *sess,\n+\t\t\t struct rte_crypto_asym_xform *xform)\n+{\n+\tstruct rte_crypto_modex_xform *ctx = &sess->mod_ctx;\n+\tsize_t exp_len = xform->modex.exponent.length;\n+\tsize_t mod_len = xform->modex.modulus.length;\n+\tuint8_t *exp = xform->modex.exponent.data;\n+\tuint8_t *mod = xform->modex.modulus.data;\n+\n+\tcnxk_ae_modex_param_normalize(&mod, &mod_len);\n+\tcnxk_ae_modex_param_normalize(&exp, &exp_len);\n+\n+\tif (unlikely(exp_len == 0 || mod_len == 0))\n+\t\treturn -EINVAL;\n+\n+\tif (unlikely(exp_len > mod_len))\n+\t\treturn -ENOTSUP;\n+\n+\t/* Allocate buffer to hold modexp params */\n+\tctx->modulus.data = rte_malloc(NULL, mod_len + exp_len, 0);\n+\tif (ctx->modulus.data == NULL)\n+\t\treturn -ENOMEM;\n+\n+\t/* Set up modexp prime modulus and private exponent */\n+\tmemcpy(ctx->modulus.data, mod, mod_len);\n+\tctx->exponent.data = ctx->modulus.data + mod_len;\n+\tmemcpy(ctx->exponent.data, exp, exp_len);\n+\n+\tctx->modulus.length = mod_len;\n+\tctx->exponent.length = exp_len;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+cnxk_ae_fill_rsa_params(struct cnxk_ae_sess *sess,\n+\t\t\tstruct rte_crypto_asym_xform *xform)\n+{\n+\tstruct rte_crypto_rsa_priv_key_qt qt = xform->rsa.qt;\n+\tstruct rte_crypto_rsa_xform *xfrm_rsa = &xform->rsa;\n+\tstruct rte_crypto_rsa_xform *rsa = &sess->rsa_ctx;\n+\tsize_t mod_len = xfrm_rsa->n.length;\n+\tsize_t exp_len = xfrm_rsa->e.length;\n+\tsize_t len = (mod_len / 2);\n+\tuint64_t total_size;\n+\n+\t/* Make sure key length used is not more than mod_len/2 */\n+\tif (qt.p.data != NULL)\n+\t\tlen = RTE_MIN(len, qt.p.length);\n+\n+\t/* Total size required for RSA key params(n,e,(q,dQ,p,dP,qInv)) */\n+\ttotal_size = mod_len + exp_len + 5 * len;\n+\n+\t/* Allocate buffer to hold all RSA keys */\n+\trsa->n.data = rte_malloc(NULL, total_size, 0);\n+\tif (rsa->n.data == NULL)\n+\t\treturn -ENOMEM;\n+\n+\t/* Set up RSA prime modulus and public key exponent */\n+\tmemcpy(rsa->n.data, xfrm_rsa->n.data, mod_len);\n+\trsa->e.data = rsa->n.data + mod_len;\n+\tmemcpy(rsa->e.data, xfrm_rsa->e.data, exp_len);\n+\n+\t/* Private key in quintuple format */\n+\tif (len != 0) {\n+\t\trsa->qt.q.data = rsa->e.data + exp_len;\n+\t\tmemcpy(rsa->qt.q.data, qt.q.data, qt.q.length);\n+\t\trsa->qt.dQ.data = rsa->qt.q.data + qt.q.length;\n+\t\tmemcpy(rsa->qt.dQ.data, qt.dQ.data, qt.dQ.length);\n+\t\trsa->qt.p.data = rsa->qt.dQ.data + qt.dQ.length;\n+\t\tmemcpy(rsa->qt.p.data, qt.p.data, qt.p.length);\n+\t\trsa->qt.dP.data = rsa->qt.p.data + qt.p.length;\n+\t\tmemcpy(rsa->qt.dP.data, qt.dP.data, qt.dP.length);\n+\t\trsa->qt.qInv.data = rsa->qt.dP.data + qt.dP.length;\n+\t\tmemcpy(rsa->qt.qInv.data, qt.qInv.data, qt.qInv.length);\n+\n+\t\trsa->qt.q.length = qt.q.length;\n+\t\trsa->qt.dQ.length = qt.dQ.length;\n+\t\trsa->qt.p.length = qt.p.length;\n+\t\trsa->qt.dP.length = qt.dP.length;\n+\t\trsa->qt.qInv.length = qt.qInv.length;\n+\t}\n+\trsa->n.length = mod_len;\n+\trsa->e.length = exp_len;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+cnxk_ae_fill_ec_params(struct cnxk_ae_sess *sess,\n+\t\t struct rte_crypto_asym_xform *xform)\n+{\n+\tstruct roc_ae_ec_ctx *ec = &sess->ec_ctx;\n+\n+\tswitch (xform->ec.curve_id) {\n+\tcase RTE_CRYPTO_EC_GROUP_SECP192R1:\n+\t\tec->curveid = ROC_AE_EC_ID_P192;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_EC_GROUP_SECP224R1:\n+\t\tec->curveid = ROC_AE_EC_ID_P224;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_EC_GROUP_SECP256R1:\n+\t\tec->curveid = ROC_AE_EC_ID_P256;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_EC_GROUP_SECP384R1:\n+\t\tec->curveid = ROC_AE_EC_ID_P384;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_EC_GROUP_SECP521R1:\n+\t\tec->curveid = ROC_AE_EC_ID_P521;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Only NIST curves (FIPS 186-4) are supported */\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+cnxk_ae_fill_session_parameters(struct cnxk_ae_sess *sess,\n+\t\t\t\tstruct rte_crypto_asym_xform *xform)\n+{\n+\tint ret;\n+\n+\tsess->xfrm_type = xform->xform_type;\n+\n+\tswitch (xform->xform_type) {\n+\tcase RTE_CRYPTO_ASYM_XFORM_RSA:\n+\t\tret = cnxk_ae_fill_rsa_params(sess, xform);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_XFORM_MODEX:\n+\t\tret = cnxk_ae_fill_modex_params(sess, xform);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECDSA:\n+\t\t/* Fall through */\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECPM:\n+\t\tret = cnxk_ae_fill_ec_params(sess, xform);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENOTSUP;\n+\t}\n+\treturn ret;\n+}\n+\n+static inline void\n+cnxk_ae_free_session_parameters(struct cnxk_ae_sess *sess)\n+{\n+\tstruct rte_crypto_modex_xform *mod;\n+\tstruct rte_crypto_rsa_xform *rsa;\n+\n+\tswitch (sess->xfrm_type) {\n+\tcase RTE_CRYPTO_ASYM_XFORM_RSA:\n+\t\trsa = &sess->rsa_ctx;\n+\t\tif (rsa->n.data)\n+\t\t\trte_free(rsa->n.data);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_XFORM_MODEX:\n+\t\tmod = &sess->mod_ctx;\n+\t\tif (mod->modulus.data)\n+\t\t\trte_free(mod->modulus.data);\n+\t\tbreak;\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECDSA:\n+\t\t/* Fall through */\n+\tcase RTE_CRYPTO_ASYM_XFORM_ECPM:\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+#endif /* _CNXK_AE_H_ */\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h\nindex 6760c13..5e38933 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h\n@@ -13,7 +13,7 @@\n #define CNXK_CPT_MAX_CAPS\t 34\n #define CNXK_SEC_CRYPTO_MAX_CAPS 4\n #define CNXK_SEC_MAX_CAPS\t 3\n-\n+#define CNXK_AE_EC_ID_MAX\t 5\n /**\n * Device private data\n */\n@@ -23,6 +23,8 @@ struct cnxk_cpt_vf {\n \tstruct rte_cryptodev_capabilities\n \t\tsec_crypto_caps[CNXK_SEC_CRYPTO_MAX_CAPS];\n \tstruct rte_security_capability sec_caps[CNXK_SEC_MAX_CAPS];\n+\tuint64_t cnxk_fpm_iova[CNXK_AE_EC_ID_MAX];\n+\tstruct roc_ae_ec_group *ec_grp[CNXK_AE_EC_ID_MAX];\n };\n \n int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt);\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\nindex 0d81785..7322539 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n@@ -8,11 +8,15 @@\n \n #include \"roc_cpt.h\"\n \n+#include \"cnxk_ae.h\"\n #include \"cnxk_cryptodev.h\"\n #include \"cnxk_cryptodev_ops.h\"\n #include \"cnxk_cryptodev_capabilities.h\"\n #include \"cnxk_se.h\"\n \n+#define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS 5\n+#define CNXK_CPT_MAX_ASYM_OP_MOD_LEN\t1024\n+\n static int\n cnxk_cpt_get_mlen(void)\n {\n@@ -31,6 +35,20 @@ cnxk_cpt_get_mlen(void)\n \treturn len;\n }\n \n+static int\n+cnxk_cpt_asym_get_mlen(void)\n+{\n+\tuint32_t len;\n+\n+\t/* To hold RPTR */\n+\tlen = sizeof(uint64_t);\n+\n+\t/* Get meta len for asymmetric operations */\n+\tlen += CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS * CNXK_CPT_MAX_ASYM_OP_MOD_LEN;\n+\n+\treturn len;\n+}\n+\n int\n cnxk_cpt_dev_config(struct rte_cryptodev *dev,\n \t\t struct rte_cryptodev_config *conf)\n@@ -54,6 +72,23 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev,\n \t\treturn ret;\n \t}\n \n+\tif (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {\n+\t\t/* Initialize shared FPM table */\n+\t\tret = roc_ae_fpm_get(vf->cnxk_fpm_iova);\n+\t\tif (ret) {\n+\t\t\tplt_err(\"Could not get FPM table\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* Init EC grp table */\n+\t\tret = roc_ae_ec_grp_get(vf->ec_grp);\n+\t\tif (ret) {\n+\t\t\tplt_err(\"Could not get EC grp table\");\n+\t\t\troc_ae_fpm_put();\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n@@ -86,6 +121,11 @@ cnxk_cpt_dev_close(struct rte_cryptodev *dev)\n \t\t}\n \t}\n \n+\tif (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {\n+\t\troc_ae_fpm_put();\n+\t\troc_ae_ec_grp_put();\n+\t}\n+\n \troc_cpt_dev_clear(&vf->cpt);\n \n \treturn 0;\n@@ -128,6 +168,12 @@ cnxk_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,\n \t\tmlen = cnxk_cpt_get_mlen();\n \t}\n \n+\tif (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {\n+\n+\t\t/* Get meta len required for asymmetric operations */\n+\t\tmlen = RTE_MAX(mlen, cnxk_cpt_asym_get_mlen());\n+\t}\n+\n \tcache_sz = RTE_MIN(RTE_MEMPOOL_CACHE_MAX_SIZE, nb_elements / 1.5);\n \n \t/* Allocate mempool */\n@@ -549,3 +595,63 @@ cnxk_cpt_sym_session_clear(struct rte_cryptodev *dev,\n {\n \treturn sym_session_clear(dev->driver_id, sess);\n }\n+\n+unsigned int\n+cnxk_ae_session_size_get(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn sizeof(struct cnxk_ae_sess);\n+}\n+\n+void\n+cnxk_ae_session_clear(struct rte_cryptodev *dev,\n+\t\t struct rte_cryptodev_asym_session *sess)\n+{\n+\tstruct rte_mempool *sess_mp;\n+\tstruct cnxk_ae_sess *priv;\n+\n+\tpriv = get_asym_session_private_data(sess, dev->driver_id);\n+\tif (priv == NULL)\n+\t\treturn;\n+\n+\t/* Free resources allocated in session_cfg */\n+\tcnxk_ae_free_session_parameters(priv);\n+\n+\t/* Reset and free object back to pool */\n+\tmemset(priv, 0, cnxk_ae_session_size_get(dev));\n+\tsess_mp = rte_mempool_from_obj(priv);\n+\tset_asym_session_private_data(sess, dev->driver_id, NULL);\n+\trte_mempool_put(sess_mp, priv);\n+}\n+\n+int\n+cnxk_ae_session_cfg(struct rte_cryptodev *dev,\n+\t\t struct rte_crypto_asym_xform *xform,\n+\t\t struct rte_cryptodev_asym_session *sess,\n+\t\t struct rte_mempool *pool)\n+{\n+\tstruct cnxk_cpt_vf *vf = dev->data->dev_private;\n+\tstruct roc_cpt *roc_cpt = &vf->cpt;\n+\tstruct cnxk_ae_sess *priv;\n+\tunion cpt_inst_w7 w7;\n+\tint ret;\n+\n+\tif (rte_mempool_get(pool, (void **)&priv))\n+\t\treturn -ENOMEM;\n+\n+\tmemset(priv, 0, sizeof(struct cnxk_ae_sess));\n+\n+\tret = cnxk_ae_fill_session_parameters(priv, xform);\n+\tif (ret) {\n+\t\trte_mempool_put(pool, priv);\n+\t\treturn ret;\n+\t}\n+\n+\tw7.u64 = 0;\n+\tw7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE];\n+\tpriv->cpt_inst_w7 = w7.u64;\n+\tpriv->cnxk_fpm_iova = vf->cnxk_fpm_iova;\n+\tpriv->ec_grp = vf->ec_grp;\n+\tset_asym_session_private_data(sess, dev->driver_id, priv);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\nindex 7995959..c317f40 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n@@ -105,4 +105,12 @@ void cnxk_cpt_sym_session_clear(struct rte_cryptodev *dev,\n \n void sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess);\n \n+unsigned int cnxk_ae_session_size_get(struct rte_cryptodev *dev __rte_unused);\n+\n+void cnxk_ae_session_clear(struct rte_cryptodev *dev,\n+\t\t\t struct rte_cryptodev_asym_session *sess);\n+int cnxk_ae_session_cfg(struct rte_cryptodev *dev,\n+\t\t\tstruct rte_crypto_asym_xform *xform,\n+\t\t\tstruct rte_cryptodev_asym_session *sess,\n+\t\t\tstruct rte_mempool *pool);\n #endif /* _CNXK_CRYPTODEV_OPS_H_ */\n", "prefixes": [ "v3", "5/8" ] }