Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94930/?format=api
{ "id": 94930, "url": "https://patches.dpdk.org/api/patches/94930/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210628194144.637-4-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210628194144.637-4-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210628194144.637-4-pbhagavatula@marvell.com", "date": "2021-06-28T19:41:41", "name": "[v4,4/6] net/cnxk: enable ptp processing in vector Tx", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "67174ed979f378842175f400ee4af7b069acd0db", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210628194144.637-4-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17507, "url": "https://patches.dpdk.org/api/series/17507/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17507", "date": "2021-06-28T19:41:38", "name": "[v4,1/6] net/cnxk: add multi seg Rx vector routine", "version": 4, "mbox": "https://patches.dpdk.org/series/17507/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94930/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94930/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B628EA0A0C;\n\tMon, 28 Jun 2021 21:42:16 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 741AC41178;\n\tMon, 28 Jun 2021 21:42:06 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 1CD1B4116A\n for <dev@dpdk.org>; Mon, 28 Jun 2021 21:42:05 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15SJeqX8014516 for <dev@dpdk.org>; Mon, 28 Jun 2021 12:42:04 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39f964agpr-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 28 Jun 2021 12:42:04 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 28 Jun 2021 12:42:02 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 28 Jun 2021 12:42:02 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 55AC73F7055;\n Mon, 28 Jun 2021 12:42:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=PdXqoUzs8KK7NqI6OocT55ywtotxq3dzfS4UUEMViCw=;\n b=aaqPiJJKcCzVwvoZcC2lWFuL0eLbdi3BG9rpYWM9CauQMYIHbIjKXini4Xus29cuFkuT\n 9PgDmNSHctOHQnJYwSXK0ZlBdJ/FMOJNmXdjENqqREFEIszIe8kseczFiorkh7WYgexz\n vjIsrHTGFBuKXG2s1FlVbSZa1bK7JZCJVaiMIxzD04DhIUDr+7Ewaw6a2aUEKDTSiFDq\n 0vz1DpyEz7OIfr5o8i7dfZ3eeW/F+4YDJqfspGpYJRMosyYGhcXfMAFqkHnQ/PjQ1ZcS\n 1FqKUhZ/3xy5O2RlX9OyBGfhpkkoRBSakttqI690OW6bBh1yy/4BRowpDuZiVD/zFGws Jw==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Tue, 29 Jun 2021 01:11:41 +0530", "Message-ID": "<20210628194144.637-4-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210628194144.637-1-pbhagavatula@marvell.com>", "References": "<20210620202906.10974-1-pbhagavatula@marvell.com>\n <20210628194144.637-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "jbr-Vi-KJKTEpNXIBQbTHrCQDdWpr6lc", "X-Proofpoint-GUID": "jbr-Vi-KJKTEpNXIBQbTHrCQDdWpr6lc", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-28_14:2021-06-25,\n 2021-06-28 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 4/6] net/cnxk: enable ptp processing in vector\n Tx", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nEnable PTP offload in vector Tx burst function. Since, we can\nno-longer use a single LMT line for burst of 4, split the LMT\ninto two and transmit twice.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/cnxk/cn10k_tx.c | 4 +-\n drivers/net/cnxk/cn10k_tx.h | 109 +++++++++++++++++++++++++++-----\n drivers/net/cnxk/cn10k_tx_vec.c | 5 +-\n drivers/net/cnxk/cn9k_tx.c | 4 +-\n drivers/net/cnxk/cn9k_tx.h | 105 ++++++++++++++++++++++++++----\n drivers/net/cnxk/cn9k_tx_vec.c | 5 +-\n 6 files changed, 192 insertions(+), 40 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_tx.c b/drivers/net/cnxk/cn10k_tx.c\nindex 05bc163a4..c4c3e6570 100644\n--- a/drivers/net/cnxk/cn10k_tx.c\n+++ b/drivers/net/cnxk/cn10k_tx.c\n@@ -67,9 +67,7 @@ cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n #undef T\n \t};\n \n-\tif (dev->scalar_ena ||\n-\t (dev->tx_offload_flags &\n-\t (NIX_TX_OFFLOAD_TSTAMP_F | NIX_TX_OFFLOAD_TSO_F)))\n+\tif (dev->scalar_ena || (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))\n \t\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \telse\n \t\tpick_tx_func(eth_dev, nix_eth_tx_vec_burst);\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex 1e1697858..8af6799ff 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -69,7 +69,9 @@ cn10k_nix_pkts_per_vec_brst(const uint16_t flags)\n static __rte_always_inline uint8_t\n cn10k_nix_tx_dwords_per_line(const uint16_t flags)\n {\n-\treturn (flags & NIX_TX_NEED_EXT_HDR) ? 6 : 8;\n+\treturn (flags & NIX_TX_NEED_EXT_HDR) ?\n+\t\t\t ((flags & NIX_TX_OFFLOAD_TSTAMP_F) ? 8 : 6) :\n+\t\t\t 8;\n }\n \n static __rte_always_inline uint64_t\n@@ -695,13 +697,15 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n \tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n \tuint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP],\n-\t\tcmd2[NIX_DESCS_PER_LOOP];\n+\t\tcmd2[NIX_DESCS_PER_LOOP], cmd3[NIX_DESCS_PER_LOOP];\n \tuint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3, data, pa;\n \tuint64x2_t senddesc01_w0, senddesc23_w0;\n \tuint64x2_t senddesc01_w1, senddesc23_w1;\n \tuint16_t left, scalar, burst, i, lmt_id;\n \tuint64x2_t sendext01_w0, sendext23_w0;\n \tuint64x2_t sendext01_w1, sendext23_w1;\n+\tuint64x2_t sendmem01_w0, sendmem23_w0;\n+\tuint64x2_t sendmem01_w1, sendmem23_w1;\n \tuint64x2_t sgdesc01_w0, sgdesc23_w0;\n \tuint64x2_t sgdesc01_w1, sgdesc23_w1;\n \tstruct cn10k_eth_txq *txq = tx_queue;\n@@ -733,6 +737,12 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tsendext23_w0 = sendext01_w0;\n \t\tsendext01_w1 = vdupq_n_u64(12 | 12U << 24);\n \t\tsendext23_w1 = sendext01_w1;\n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\tsendmem01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n+\t\t\tsendmem23_w0 = sendmem01_w0;\n+\t\t\tsendmem01_w1 = vld1q_dup_u64(&txq->cmd[3]);\n+\t\t\tsendmem23_w1 = sendmem01_w1;\n+\t\t}\n \t}\n \n \t/* Get LMT base address and LMT ID as lcore id */\n@@ -760,6 +770,17 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tsendext23_w1 = sendext01_w1;\n \t\t}\n \n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t/* Reset send mem alg to SETTSTMP from SUB*/\n+\t\t\tsendmem01_w0 = vbicq_u64(sendmem01_w0,\n+\t\t\t\t\t\t vdupq_n_u64(BIT_ULL(59)));\n+\t\t\t/* Reset send mem address to default. */\n+\t\t\tsendmem01_w1 =\n+\t\t\t\tvbicq_u64(sendmem01_w1, vdupq_n_u64(0xF));\n+\t\t\tsendmem23_w0 = sendmem01_w0;\n+\t\t\tsendmem23_w1 = sendmem01_w1;\n+\t\t}\n+\n \t\t/* Move mbufs to iova */\n \t\tmbuf0 = (uint64_t *)tx_pkts[0];\n \t\tmbuf1 = (uint64_t *)tx_pkts[1];\n@@ -1371,6 +1392,44 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tsendext23_w1 = vorrq_u64(sendext23_w1, ytmp128);\n \t\t}\n \n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t/* Tx ol_flag for timestam. */\n+\t\t\tconst uint64x2_t olf = {PKT_TX_IEEE1588_TMST,\n+\t\t\t\t\t\tPKT_TX_IEEE1588_TMST};\n+\t\t\t/* Set send mem alg to SUB. */\n+\t\t\tconst uint64x2_t alg = {BIT_ULL(59), BIT_ULL(59)};\n+\t\t\t/* Increment send mem address by 8. */\n+\t\t\tconst uint64x2_t addr = {0x8, 0x8};\n+\n+\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n+\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n+\n+\t\t\t/* Check if timestamp is requested and generate inverted\n+\t\t\t * mask as we need not make any changes to default cmd\n+\t\t\t * value.\n+\t\t\t */\n+\t\t\txtmp128 = vmvnq_u32(vtstq_u64(olf, xtmp128));\n+\t\t\tytmp128 = vmvnq_u32(vtstq_u64(olf, ytmp128));\n+\n+\t\t\t/* Change send mem address to an 8 byte offset when\n+\t\t\t * TSTMP is disabled.\n+\t\t\t */\n+\t\t\tsendmem01_w1 = vaddq_u64(sendmem01_w1,\n+\t\t\t\t\t\t vandq_u64(xtmp128, addr));\n+\t\t\tsendmem23_w1 = vaddq_u64(sendmem23_w1,\n+\t\t\t\t\t\t vandq_u64(ytmp128, addr));\n+\t\t\t/* Change send mem alg to SUB when TSTMP is disabled. */\n+\t\t\tsendmem01_w0 = vorrq_u64(sendmem01_w0,\n+\t\t\t\t\t\t vandq_u64(xtmp128, alg));\n+\t\t\tsendmem23_w0 = vorrq_u64(sendmem23_w0,\n+\t\t\t\t\t\t vandq_u64(ytmp128, alg));\n+\n+\t\t\tcmd3[0] = vzip1q_u64(sendmem01_w0, sendmem01_w1);\n+\t\t\tcmd3[1] = vzip2q_u64(sendmem01_w0, sendmem01_w1);\n+\t\t\tcmd3[2] = vzip1q_u64(sendmem23_w0, sendmem23_w1);\n+\t\t\tcmd3[3] = vzip2q_u64(sendmem23_w0, sendmem23_w1);\n+\t\t}\n+\n \t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n \t\t\t/* Set don't free bit if reference count > 1 */\n \t\t\txmask01 = vdupq_n_u64(0);\n@@ -1458,19 +1517,39 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \t\tif (flags & NIX_TX_NEED_EXT_HDR) {\n \t\t\t/* Store the prepared send desc to LMT lines */\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[0]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[0]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd0[1]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd2[1]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[1]);\n-\t\t\tlnum += 1;\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[2]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[2]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[2]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd0[3]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd2[3]);\n-\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[3]);\n+\t\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd3[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd0[1]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd2[1]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 96), cmd1[1]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 112), cmd3[1]);\n+\t\t\t\tlnum += 1;\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd3[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd0[3]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd2[3]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 96), cmd1[3]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 112), cmd3[3]);\n+\t\t\t} else {\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[0]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd0[1]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd2[1]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[1]);\n+\t\t\t\tlnum += 1;\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 16), cmd2[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 32), cmd1[2]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 48), cmd0[3]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 64), cmd2[3]);\n+\t\t\t\tvst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[3]);\n+\t\t\t}\n \t\t\tlnum += 1;\n \t\t} else {\n \t\t\t/* Store the prepared send desc to LMT lines */\ndiff --git a/drivers/net/cnxk/cn10k_tx_vec.c b/drivers/net/cnxk/cn10k_tx_vec.c\nindex beb5c649b..0b4a4c7ba 100644\n--- a/drivers/net/cnxk/cn10k_tx_vec.c\n+++ b/drivers/net/cnxk/cn10k_tx_vec.c\n@@ -13,9 +13,8 @@\n \t{ \\\n \t\tuint64_t cmd[sz]; \\\n \t\t\t\t\t\t\t\t\t \\\n-\t\t/* VLAN, TSTMP, TSO is not supported by vec */ \\\n-\t\tif ((flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t \\\n-\t\t (flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t \\\n+\t\t/* TSO is not supported by vec */ \\\n+\t\tif ((flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn10k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd,\\\n \t\t\t\t\t\t (flags)); \\\ndiff --git a/drivers/net/cnxk/cn9k_tx.c b/drivers/net/cnxk/cn9k_tx.c\nindex 4b43cdaff..c32681ed4 100644\n--- a/drivers/net/cnxk/cn9k_tx.c\n+++ b/drivers/net/cnxk/cn9k_tx.c\n@@ -66,9 +66,7 @@ cn9k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n #undef T\n \t};\n \n-\tif (dev->scalar_ena ||\n-\t (dev->tx_offload_flags &\n-\t (NIX_TX_OFFLOAD_TSTAMP_F | NIX_TX_OFFLOAD_TSO_F)))\n+\tif (dev->scalar_ena || (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))\n \t\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \telse\n \t\tpick_tx_func(eth_dev, nix_eth_tx_vec_burst);\ndiff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h\nindex d5715bb52..cb574a1c1 100644\n--- a/drivers/net/cnxk/cn9k_tx.h\n+++ b/drivers/net/cnxk/cn9k_tx.h\n@@ -553,12 +553,14 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n \tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n \tuint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP],\n-\t\tcmd2[NIX_DESCS_PER_LOOP];\n+\t\tcmd2[NIX_DESCS_PER_LOOP], cmd3[NIX_DESCS_PER_LOOP];\n \tuint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n \tuint64x2_t senddesc01_w0, senddesc23_w0;\n \tuint64x2_t senddesc01_w1, senddesc23_w1;\n \tuint64x2_t sendext01_w0, sendext23_w0;\n \tuint64x2_t sendext01_w1, sendext23_w1;\n+\tuint64x2_t sendmem01_w0, sendmem23_w0;\n+\tuint64x2_t sendmem01_w1, sendmem23_w1;\n \tuint64x2_t sgdesc01_w0, sgdesc23_w0;\n \tuint64x2_t sgdesc01_w1, sgdesc23_w1;\n \tstruct cn9k_eth_txq *txq = tx_queue;\n@@ -597,6 +599,12 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tsendext23_w1 = sendext01_w1;\n \t\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[4]);\n \t\tsgdesc23_w0 = sgdesc01_w0;\n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\tsendmem01_w0 = vld1q_dup_u64(&txq->cmd[6]);\n+\t\t\tsendmem23_w0 = sendmem01_w0;\n+\t\t\tsendmem01_w1 = vld1q_dup_u64(&txq->cmd[7]);\n+\t\t\tsendmem23_w1 = sendmem01_w1;\n+\t\t}\n \t} else {\n \t\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n \t\tsgdesc23_w0 = sgdesc01_w0;\n@@ -618,6 +626,17 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tsendext23_w1 = sendext01_w1;\n \t\t}\n \n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t/* Reset send mem alg to SETTSTMP from SUB*/\n+\t\t\tsendmem01_w0 = vbicq_u64(sendmem01_w0,\n+\t\t\t\t\t\t vdupq_n_u64(BIT_ULL(59)));\n+\t\t\t/* Reset send mem address to default. */\n+\t\t\tsendmem01_w1 =\n+\t\t\t\tvbicq_u64(sendmem01_w1, vdupq_n_u64(0xF));\n+\t\t\tsendmem23_w0 = sendmem01_w0;\n+\t\t\tsendmem23_w1 = sendmem01_w1;\n+\t\t}\n+\n \t\t/* Move mbufs to iova */\n \t\tmbuf0 = (uint64_t *)tx_pkts[0];\n \t\tmbuf1 = (uint64_t *)tx_pkts[1];\n@@ -1229,6 +1248,44 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tsendext23_w1 = vorrq_u64(sendext23_w1, ytmp128);\n \t\t}\n \n+\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t/* Tx ol_flag for timestam. */\n+\t\t\tconst uint64x2_t olf = {PKT_TX_IEEE1588_TMST,\n+\t\t\t\t\t\tPKT_TX_IEEE1588_TMST};\n+\t\t\t/* Set send mem alg to SUB. */\n+\t\t\tconst uint64x2_t alg = {BIT_ULL(59), BIT_ULL(59)};\n+\t\t\t/* Increment send mem address by 8. */\n+\t\t\tconst uint64x2_t addr = {0x8, 0x8};\n+\n+\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n+\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n+\n+\t\t\t/* Check if timestamp is requested and generate inverted\n+\t\t\t * mask as we need not make any changes to default cmd\n+\t\t\t * value.\n+\t\t\t */\n+\t\t\txtmp128 = vmvnq_u32(vtstq_u64(olf, xtmp128));\n+\t\t\tytmp128 = vmvnq_u32(vtstq_u64(olf, ytmp128));\n+\n+\t\t\t/* Change send mem address to an 8 byte offset when\n+\t\t\t * TSTMP is disabled.\n+\t\t\t */\n+\t\t\tsendmem01_w1 = vaddq_u64(sendmem01_w1,\n+\t\t\t\t\t\t vandq_u64(xtmp128, addr));\n+\t\t\tsendmem23_w1 = vaddq_u64(sendmem23_w1,\n+\t\t\t\t\t\t vandq_u64(ytmp128, addr));\n+\t\t\t/* Change send mem alg to SUB when TSTMP is disabled. */\n+\t\t\tsendmem01_w0 = vorrq_u64(sendmem01_w0,\n+\t\t\t\t\t\t vandq_u64(xtmp128, alg));\n+\t\t\tsendmem23_w0 = vorrq_u64(sendmem23_w0,\n+\t\t\t\t\t\t vandq_u64(ytmp128, alg));\n+\n+\t\t\tcmd3[0] = vzip1q_u64(sendmem01_w0, sendmem01_w1);\n+\t\t\tcmd3[1] = vzip2q_u64(sendmem01_w0, sendmem01_w1);\n+\t\t\tcmd3[2] = vzip1q_u64(sendmem23_w0, sendmem23_w1);\n+\t\t\tcmd3[3] = vzip2q_u64(sendmem23_w0, sendmem23_w1);\n+\t\t}\n+\n \t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n \t\t\t/* Set don't free bit if reference count > 1 */\n \t\t\txmask01 = vdupq_n_u64(0);\n@@ -1327,22 +1384,44 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t * Split and Tx twice.\n \t\t\t */\n \t\t\tdo {\n-\t\t\t\tvst1q_u64(lmt_addr, cmd0[0]);\n-\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[0]);\n-\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[0]);\n-\t\t\t\tvst1q_u64(lmt_addr + 6, cmd0[1]);\n-\t\t\t\tvst1q_u64(lmt_addr + 8, cmd2[1]);\n-\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[1]);\n+\t\t\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t\t\tvst1q_u64(lmt_addr, cmd0[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 6, cmd3[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 8, cmd0[1]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 10, cmd2[1]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 12, cmd1[1]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 14, cmd3[1]);\n+\t\t\t\t} else {\n+\t\t\t\t\tvst1q_u64(lmt_addr, cmd0[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[0]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 6, cmd0[1]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 8, cmd2[1]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[1]);\n+\t\t\t\t}\n \t\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n \t\t\t} while (lmt_status == 0);\n \n \t\t\tdo {\n-\t\t\t\tvst1q_u64(lmt_addr, cmd0[2]);\n-\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[2]);\n-\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[2]);\n-\t\t\t\tvst1q_u64(lmt_addr + 6, cmd0[3]);\n-\t\t\t\tvst1q_u64(lmt_addr + 8, cmd2[3]);\n-\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[3]);\n+\t\t\t\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t\t\tvst1q_u64(lmt_addr, cmd0[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 6, cmd3[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 8, cmd0[3]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 10, cmd2[3]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 12, cmd1[3]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 14, cmd3[3]);\n+\t\t\t\t} else {\n+\t\t\t\t\tvst1q_u64(lmt_addr, cmd0[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 2, cmd2[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 4, cmd1[2]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 6, cmd0[3]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 8, cmd2[3]);\n+\t\t\t\t\tvst1q_u64(lmt_addr + 10, cmd1[3]);\n+\t\t\t\t}\n \t\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n \t\t\t} while (lmt_status == 0);\n \t\t} else {\ndiff --git a/drivers/net/cnxk/cn9k_tx_vec.c b/drivers/net/cnxk/cn9k_tx_vec.c\nindex 5842facb5..9ade66db2 100644\n--- a/drivers/net/cnxk/cn9k_tx_vec.c\n+++ b/drivers/net/cnxk/cn9k_tx_vec.c\n@@ -13,9 +13,8 @@\n \t{ \\\n \t\tuint64_t cmd[sz]; \\\n \t\t\t\t\t\t\t\t\t \\\n-\t\t/* VLAN, TSTMP, TSO is not supported by vec */ \\\n-\t\tif ((flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t \\\n-\t\t (flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t \\\n+\t\t/* TSO is not supported by vec */ \\\n+\t\tif ((flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn9k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd, \\\n \t\t\t\t\t\t (flags));\t\t \\\n", "prefixes": [ "v4", "4/6" ] }