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GET /api/patches/94917/?format=api
{ "id": 94917, "url": "https://patches.dpdk.org/api/patches/94917/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210628163434.77741-11-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210628163434.77741-11-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210628163434.77741-11-arkadiuszx.kusztal@intel.com", "date": "2021-06-28T16:34:28", "name": "[v2,10/16] crypto/qat: add gmac in legacy mode on gen 4", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7eec34ad49d4f4311b188ea88d57c21a2a1f241b", "submitter": { "id": 452, "url": "https://patches.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210628163434.77741-11-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 17505, "url": "https://patches.dpdk.org/api/series/17505/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17505", "date": "2021-06-28T16:34:18", "name": "Add support for fourth generation of Intel QuickAssist Technology devices", "version": 2, "mbox": "https://patches.dpdk.org/series/17505/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94917/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94917/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 36551A0A0C;\n\tMon, 28 Jun 2021 18:35:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8B7A541183;\n\tMon, 28 Jun 2021 18:34:55 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 4EC5A4118D\n for <dev@dpdk.org>; Mon, 28 Jun 2021 18:34:54 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Jun 2021 09:34:54 -0700", "from silpixa00399302.ir.intel.com ([10.237.214.136])\n by fmsmga008.fm.intel.com with ESMTP; 28 Jun 2021 09:34:52 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10029\"; a=\"206165924\"", "E=Sophos;i=\"5.83,306,1616482800\"; d=\"scan'208\";a=\"206165924\"", "E=Sophos;i=\"5.83,306,1616482800\"; d=\"scan'208\";a=\"456395666\"" ], "X-ExtLoop1": "1", "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>", "Date": "Mon, 28 Jun 2021 17:34:28 +0100", "Message-Id": "<20210628163434.77741-11-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20210628163434.77741-1-arkadiuszx.kusztal@intel.com>", "References": "<20210628163434.77741-1-arkadiuszx.kusztal@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 10/16] crypto/qat: add gmac in legacy mode on\n gen 4", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add AES-GMAC algorithm in legacy mode to generation 4 devices.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n drivers/crypto/qat/qat_sym_capabilities.h | 27 ++++++++++++++++++++++-\n drivers/crypto/qat/qat_sym_session.c | 9 +++++++-\n drivers/crypto/qat/qat_sym_session.h | 2 ++\n 3 files changed, 36 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h\nindex 5c6e723466..cfb176ca94 100644\n--- a/drivers/crypto/qat/qat_sym_capabilities.h\n+++ b/drivers/crypto/qat/qat_sym_capabilities.h\n@@ -1174,7 +1174,32 @@\n \t\t\t\t},\t\t\t\t\t\\\n \t\t\t}, }\t\t\t\t\t\t\\\n \t\t}, }\t\t\t\t\t\t\t\\\n-\t}\n+\t},\t\t\t\t\t\t\t\t\\\n+\t{\t/* AES GMAC (AUTH) */\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\t\\\n+\t\t\t{.auth = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_GMAC,\t\\\n+\t\t\t\t.block_size = 16,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 32,\t\t\t\\\n+\t\t\t\t\t.increment = 8\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 8,\t\t\t\\\n+\t\t\t\t\t.max = 16,\t\t\t\\\n+\t\t\t\t\t.increment = 4\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 12,\t\t\t\\\n+\t\t\t\t\t.increment = 12\t\t\t\\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n \n \n \ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex a49da8e364..03514ca073 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -710,6 +710,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n \tconst uint8_t *key_data = auth_xform->key.data;\n \tuint8_t key_length = auth_xform->key.length;\n+\tenum qat_device_gen qat_dev_gen =\n+\t\t\tinternals->qat_dev->qat_dev_gen;\n \n \tsession->aes_cmac = 0;\n \tsession->auth_key_length = auth_xform->key.length;\n@@ -717,6 +719,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \tsession->auth_iv.length = auth_xform->iv.length;\n \tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n \tsession->is_auth = 1;\n+\tsession->digest_length = auth_xform->digest_length;\n \n \tswitch (auth_xform->algo) {\n \tcase RTE_CRYPTO_AUTH_SHA1:\n@@ -773,6 +776,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\tsession->auth_iv.length = AES_GCM_J0_LEN;\n \t\telse\n \t\t\tsession->is_iv12B = 1;\n+\t\tif (qat_dev_gen == QAT_GEN4) {\n+\t\t\tsession->is_cnt_zero = 1;\n+\t\t\tsession->is_ucs = 1;\n+\t\t}\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\n@@ -858,7 +865,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\treturn -EINVAL;\n \t}\n \n-\tsession->digest_length = auth_xform->digest_length;\n \treturn 0;\n }\n \n@@ -1811,6 +1817,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL\n+\t\t|| cdesc->is_cnt_zero\n \t\t\t)\n \t\thash->auth_counter.counter = 0;\n \telse {\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 1568e09200..33b236e49b 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -103,6 +103,8 @@ struct qat_sym_session {\n \tuint8_t is_iv12B;\n \tuint8_t is_gmac;\n \tuint8_t is_auth;\n+\tuint8_t is_cnt_zero;\n+\t/* Some generations need different setup of counter */\n \tuint32_t slice_types;\n \tenum qat_sym_proto_flag qat_proto_flag;\n };\n", "prefixes": [ "v2", "10/16" ] }