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GET /api/patches/94915/?format=api
{ "id": 94915, "url": "https://patches.dpdk.org/api/patches/94915/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210628163434.77741-9-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210628163434.77741-9-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210628163434.77741-9-arkadiuszx.kusztal@intel.com", "date": "2021-06-28T16:34:26", "name": "[v2,08/16] crypto/qat: add aes gcm in ucs spc mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0266632996541cfe4d85751b4ceaa95111071060", "submitter": { "id": 452, "url": "https://patches.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210628163434.77741-9-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 17505, "url": "https://patches.dpdk.org/api/series/17505/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17505", "date": "2021-06-28T16:34:18", "name": "Add support for fourth generation of Intel QuickAssist Technology devices", "version": 2, "mbox": "https://patches.dpdk.org/series/17505/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94915/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94915/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A126A0A0C;\n\tMon, 28 Jun 2021 18:35:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BED734115F;\n\tMon, 28 Jun 2021 18:34:51 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 8109641151\n for <dev@dpdk.org>; Mon, 28 Jun 2021 18:34:50 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Jun 2021 09:34:50 -0700", "from silpixa00399302.ir.intel.com ([10.237.214.136])\n by fmsmga008.fm.intel.com with ESMTP; 28 Jun 2021 09:34:47 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10029\"; a=\"206165914\"", "E=Sophos;i=\"5.83,306,1616482800\"; d=\"scan'208\";a=\"206165914\"", "E=Sophos;i=\"5.83,306,1616482800\"; d=\"scan'208\";a=\"456395628\"" ], "X-ExtLoop1": "1", "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>", "Date": "Mon, 28 Jun 2021 17:34:26 +0100", "Message-Id": "<20210628163434.77741-9-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20210628163434.77741-1-arkadiuszx.kusztal@intel.com>", "References": "<20210628163434.77741-1-arkadiuszx.kusztal@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 08/16] crypto/qat: add aes gcm in ucs spc mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds AES-GCM algorithm that works\nin UCS (Unified crypto slice) SPC(Single-Pass) mode.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n drivers/crypto/qat/qat_sym.c | 32 ++++++++++++++++++++--------\n drivers/crypto/qat/qat_sym_session.c | 9 ++++----\n 2 files changed, 27 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex eef4a886c5..00fc4d6b1a 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -217,6 +217,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \tint ret = 0;\n \tstruct qat_sym_session *ctx = NULL;\n \tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\tstruct icp_qat_fw_la_cipher_20_req_params *cipher_param20;\n \tstruct icp_qat_fw_la_auth_req_params *auth_param;\n \tregister struct icp_qat_fw_la_bulk_req *qat_req;\n \tuint8_t do_auth = 0, do_cipher = 0, do_aead = 0;\n@@ -286,6 +287,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \trte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));\n \tqat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;\n \tcipher_param = (void *)&qat_req->serv_specif_rqpars;\n+\tcipher_param20 = (void *)&qat_req->serv_specif_rqpars;\n \tauth_param = (void *)((uint8_t *)cipher_param +\n \t\t\tICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);\n \n@@ -563,13 +565,17 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tcipher_param->cipher_length = 0;\n \t}\n \n-\tif (do_auth || do_aead) {\n-\t\tauth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(\n+\tif (!ctx->is_single_pass) {\n+\t\t/* Do not let to owerwrite spc_aad len */\n+\t\tif (do_auth || do_aead) {\n+\t\t\tauth_param->auth_off =\n+\t\t\t\t(uint32_t)rte_pktmbuf_iova_offset(\n \t\t\t\top->sym->m_src, auth_ofs) - src_buf_start;\n-\t\tauth_param->auth_len = auth_len;\n-\t} else {\n-\t\tauth_param->auth_off = 0;\n-\t\tauth_param->auth_len = 0;\n+\t\t\tauth_param->auth_len = auth_len;\n+\t\t} else {\n+\t\t\tauth_param->auth_off = 0;\n+\t\t\tauth_param->auth_len = 0;\n+\t\t}\n \t}\n \n \tqat_req->comn_mid.dst_length =\n@@ -675,10 +681,18 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t}\n \n \tif (ctx->is_single_pass) {\n-\t\t/* Handle Single-Pass GCM */\n-\t\tcipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;\n-\t\tcipher_param->spc_auth_res_addr =\n+\t\tif (ctx->is_ucs) {\n+\t\t\t/* GEN 4 */\n+\t\t\tcipher_param20->spc_aad_addr =\n+\t\t\t\top->sym->aead.aad.phys_addr;\n+\t\t\tcipher_param20->spc_auth_res_addr =\n \t\t\t\top->sym->aead.digest.phys_addr;\n+\t\t} else {\n+\t\t\tcipher_param->spc_aad_addr =\n+\t\t\t\top->sym->aead.aad.phys_addr;\n+\t\t\tcipher_param->spc_auth_res_addr =\n+\t\t\t\t\top->sym->aead.digest.phys_addr;\n+\t\t}\n \t} else if (ctx->is_single_pass_gmac &&\n \t\t op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {\n \t\t/* Handle Single-Pass AES-GMAC */\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex fd6fe4423d..019c9f4f02 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -898,16 +898,15 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \n \t\tif (qat_dev_gen == QAT_GEN4)\n \t\t\tsession->is_ucs = 1;\n-\n \t\tif (session->cipher_iv.length == 0) {\n \t\t\tsession->cipher_iv.length = AES_GCM_J0_LEN;\n \t\t\tbreak;\n \t\t}\n \t\tsession->is_iv12B = 1;\n-\t\tif (qat_dev_gen == QAT_GEN3) {\n-\t\t\tqat_sym_session_handle_single_pass(session,\n-\t\t\t\t\taead_xform);\n-\t\t}\n+\t\tif (qat_dev_gen < QAT_GEN3)\n+\t\t\tbreak;\n+\t\tqat_sym_session_handle_single_pass(session,\n+\t\t\t\taead_xform);\n \t\tbreak;\n \tcase RTE_CRYPTO_AEAD_AES_CCM:\n \t\tif (qat_sym_validate_aes_key(aead_xform->key.length,\n", "prefixes": [ "v2", "08/16" ] }