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GET /api/patches/94839/?format=api
{ "id": 94839, "url": "https://patches.dpdk.org/api/patches/94839/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-16-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-16-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-16-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:26", "name": "[v2,15/20] crypto/cnxk: add ZUC and SNOW3G decrypt", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3f3b7b1e16d264ef72a28bc5a4487bd3871a43cf", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-16-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94839/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94839/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DD3E0A0C40;\n\tFri, 25 Jun 2021 07:58:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C60CC41139;\n\tFri, 25 Jun 2021 07:58:20 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7A43440698\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:58:18 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5nxkZ007987; Thu, 24 Jun 2021 22:58:17 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 39d24dhk4q-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:58:17 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:58:15 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:58:15 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id A3A1C3F7041;\n Thu, 24 Jun 2021 22:58:12 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=BXD68OmL3cyhJJWGHQXe/QJdoHn7bOaCgjV3yzIoSwY=;\n b=gBayKFEhEGoFFy+LWHzNguVJrSgmWDFK8j9JLYM7oVE+SHngh+1YoIAFg57k4SEVvjiJ\n oPBwJKwR6BkFYSu9yVgQWEg9AVA4PmoTVQr01X1rrCC95CA7L+O48nVeEQmFcV6yLsJM\n 5I/i8198Genv/hN2PWknDuyK9seI47m+IxGbFNO/B1Fk9Dg57eIYRh8r86A+VmejLSFn\n MRaKaooJhYyJUAO17jsXaIvtYbT+xAAbEs55cmYR7YYRgj/6rPNtNmH5OBRkhNPCcMSI\n gLeGmQrmcKpMkCVsq2YvWSAPJFKn28bjAiazXDygxk+7fXWSZ/zVIIt/zPYck8TYXSjd bw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, <dev@dpdk.org>, Anoob Joseph\n <anoobj@marvell.com>, Archana Muniganti <marchana@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:26 +0530", "Message-ID": "<1624600591-29841-16-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "BP24Vu370AqBte3EyuSRukFrB_b2gpit", "X-Proofpoint-ORIG-GUID": "BP24Vu370AqBte3EyuSRukFrB_b2gpit", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 15/20] crypto/cnxk: add ZUC and SNOW3G decrypt", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tejasree Kondoj <ktejasree@marvell.com>\n\nAdd PDCP opcode which handles ZUC and SNOW3G.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n doc/guides/cryptodevs/features/cn10k.ini | 2 +\n doc/guides/cryptodevs/features/cn9k.ini | 2 +\n drivers/crypto/cnxk/cnxk_se.h | 209 ++++++++++++++++++++++++++++++-\n 3 files changed, 212 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex 7750d92..a90421a 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -30,6 +30,8 @@ AES CTR (256) = Y\n AES XTS (128) = Y\n AES XTS (256) = Y\n DES CBC = Y\n+SNOW3G UEA2 = Y\n+ZUC EEA3 = Y\n \n ;\n ; Supported authentication algorithms of 'cn10k' crypto driver.\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex 7007d11..fb0c09b 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -30,6 +30,8 @@ AES CTR (256) = Y\n AES XTS (128) = Y\n AES XTS (256) = Y\n DES CBC = Y\n+SNOW3G UEA2 = Y\n+ZUC EEA3 = Y\n \n ;\n ; Supported authentication algorithms of 'cn9k' crypto driver.\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 7d3bcbc..c483b95 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -1079,6 +1079,209 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n }\n \n static __rte_always_inline int\n+cpt_zuc_snow3g_dec_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t\tstruct roc_se_fc_params *params,\n+\t\t\tstruct cpt_inst_s *inst)\n+{\n+\tuint32_t size;\n+\tint32_t inputlen = 0, outputlen;\n+\tstruct roc_se_ctx *se_ctx;\n+\tuint8_t pdcp_alg_type, iv_len = 16;\n+\tuint32_t encr_offset;\n+\tuint32_t encr_data_len;\n+\tint flags;\n+\tuint64_t *offset_vaddr;\n+\tuint32_t *iv_s, iv[4], j;\n+\tunion cpt_inst_w4 cpt_inst_w4;\n+\n+\t/*\n+\t * Microcode expects offsets in bytes\n+\t * TODO: Rounding off\n+\t */\n+\tencr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;\n+\tencr_data_len = ROC_SE_ENCR_DLEN(d_lens);\n+\n+\tse_ctx = params->ctx_buf.vaddr;\n+\tflags = se_ctx->zsk_flags;\n+\tpdcp_alg_type = se_ctx->pdcp_alg_type;\n+\n+\tcpt_inst_w4.u64 = 0;\n+\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;\n+\n+\t/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */\n+\n+\tcpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) |\n+\t\t\t\t (0 << 4) | (0 << 3) | (flags & 0x7));\n+\n+\t/* consider iv len */\n+\tencr_offset += iv_len;\n+\n+\tinputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);\n+\toutputlen = inputlen;\n+\n+\t/* IV */\n+\tiv_s = params->iv_buf;\n+\tif (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) {\n+\t\t/*\n+\t\t * DPDK seems to provide it in form of IV3 IV2 IV1 IV0\n+\t\t * and BigEndian, MC needs it as IV0 IV1 IV2 IV3\n+\t\t */\n+\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv[j] = iv_s[3 - j];\n+\t} else {\n+\t\t/* ZUC doesn't need a swap */\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv[j] = iv_s[j];\n+\t}\n+\n+\t/*\n+\t * GP op header, lengths are expected in bits.\n+\t */\n+\tcpt_inst_w4.s.param1 = encr_data_len;\n+\n+\t/*\n+\t * In cn9k, cn10k since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) &&\n+\t\t (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) {\n+\t\tvoid *dm_vaddr = params->bufs[0].vaddr;\n+\n+\t\t/* Use Direct mode */\n+\n+\t\toffset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -\n+\t\t\t\t\t ROC_SE_OFF_CTRL_LEN - iv_len);\n+\n+\t\t/* DPTR */\n+\t\tinst->dptr = (uint64_t)offset_vaddr;\n+\n+\t\t/* RPTR should just exclude offset control word */\n+\t\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n+\n+\t\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN);\n+\t\t\tmemcpy(iv_d, iv, 16);\n+\t\t}\n+\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);\n+\t} else {\n+\t\tvoid *m_vaddr = params->meta_buf.vaddr;\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tstruct roc_se_sglist_comp *gather_comp;\n+\t\tstruct roc_se_sglist_comp *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\t\tuint32_t *iv_d;\n+\n+\t\t/* save space for offset and iv... */\n+\t\toffset_vaddr = m_vaddr;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;\n+\n+\t\tcpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word */\n+\n+\t\t/* iv offset is 0 */\n+\t\t*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);\n+\n+\t\ti = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,\n+\t\t\t\t ROC_SE_OFF_CTRL_LEN + iv_len);\n+\n+\t\tiv_d = (uint32_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t ROC_SE_OFF_CTRL_LEN);\n+\t\tmemcpy(iv_d, iv, 16);\n+\n+\t\t/* Add input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (size) {\n+\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t params->src_iov, 0, &size,\n+\t\t\t\t\t\t NULL, 0);\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d needed\",\n+\t\t\t\t\t size);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n+\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n+\t\t\t\t\t\t g_size_bytes);\n+\n+\t\t/* IV */\n+\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,\n+\t\t\t\t iv_len);\n+\n+\t\t/* Add output data */\n+\t\tsize = outputlen - iv_len;\n+\t\tif (size) {\n+\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t params->dst_iov, 0, &size,\n+\t\t\t\t\t\t NULL, 0);\n+\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d needed\",\n+\t\t\t\t\t size);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len in case of SG mode */\n+\t\tcpt_inst_w4.s.dlen = size;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t}\n+\n+\tif (unlikely((encr_offset >> 16))) {\n+\t\tplt_dp_err(\"Offset not supported\");\n+\t\tplt_dp_err(\"enc_offset: %d\", encr_offset);\n+\t\treturn -1;\n+\t}\n+\n+\tinst->w4.u64 = cpt_inst_w4.u64;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t\t struct roc_se_fc_params *fc_params,\n \t\t struct cpt_inst_s *inst)\n@@ -1089,8 +1292,12 @@ cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \n \tfc_type = ctx->fc_type;\n \n-\tif (likely(fc_type == ROC_SE_FC_GEN))\n+\tif (likely(fc_type == ROC_SE_FC_GEN)) {\n \t\tret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, inst);\n+\t} else if (fc_type == ROC_SE_PDCP) {\n+\t\tret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params,\n+\t\t\t\t\t inst);\n+\t}\n \treturn ret;\n }\n \n", "prefixes": [ "v2", "15/20" ] }