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GET /api/patches/94837/?format=api
{ "id": 94837, "url": "https://patches.dpdk.org/api/patches/94837/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-14-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-14-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-14-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:24", "name": "[v2,13/20] crypto/cnxk: add flexi crypto cipher decrypt", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3a007b64d74baad0daddbaf9c4334d254911bbbf", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-14-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94837/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94837/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 411A9A0C40;\n\tFri, 25 Jun 2021 07:58:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 69C88410FF;\n\tFri, 25 Jun 2021 07:58:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id ACA4C410FE\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:58:08 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5pGSP010749; Thu, 24 Jun 2021 22:58:07 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 39d24dhk42-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:58:07 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:58:06 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:58:06 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id D5CCC3F7068;\n Thu, 24 Jun 2021 22:58:02 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=gLMrNhNPiImxa1gpZqGOKo+CtSM4lCQX6gSuaVO4I50=;\n b=e9wEhj4L8yienPGE427x/HNySQNNKOE7LAkraWJxM+Fr2bRi5FttkMUOpNxr4hNPG4ib\n gEAgFiS9wIoC9oASN7ISzC/WHlTQakkBxz/6Y9Nlc2kjlISGirbrWg3i/19GcpUgem4b\n /eC9WBFqeHSEbFEnT0V1VHdq+fGDwCgUJ6OggykB1uSSOt27nVUPrmzTqrEtW02+tfl/\n SkFcKkylBzgdnZ1y8JUa1fNcoXF9XOcNFPUqYjc2fs6NLpOqmbxGSY6MLgp0aiiYmisl\n Rg5Uc16LwQ/XU8rBQ2Bn4IzHsPbnr2qTuY9LSrzs11bTMBIUShb+Qoh5Xho6mZWcZHE/ Iw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Archana Muniganti <marchana@marvell.com>,\n Jerin Jacob <jerinj@marvell.com>,\n Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph <anoobj@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:24 +0530", "Message-ID": "<1624600591-29841-14-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "_5Eip-YzqOU-iPIqIB9upat-0z_-oMmo", "X-Proofpoint-ORIG-GUID": "_5Eip-YzqOU-iPIqIB9upat-0z_-oMmo", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 13/20] crypto/cnxk: add flexi crypto cipher\n decrypt", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Archana Muniganti <marchana@marvell.com>\n\nAdd flexi crypto cipher decrypt support in enqueue API. Flexi crypto\nopcode covers a broad set of ciphers including variants of AES.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n doc/guides/cryptodevs/features/cn10k.ini | 20 ++\n doc/guides/cryptodevs/features/cn9k.ini | 20 ++\n drivers/crypto/cnxk/cn10k_cryptodev.c | 4 +\n drivers/crypto/cnxk/cn9k_cryptodev.c | 4 +\n drivers/crypto/cnxk/cnxk_se.h | 324 ++++++++++++++++++++++++++++++-\n 5 files changed, 371 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex 175fbf7..7750d92 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -7,6 +7,10 @@\n Symmetric crypto = Y\n Sym operation chaining = Y\n HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In LB Out = Y\n+OOP SGL In SGL Out = Y\n+OOP LB In LB Out = Y\n Symmetric sessionless = Y\n Digest encrypted = Y\n \n@@ -14,6 +18,18 @@ Digest encrypted = Y\n ; Supported crypto algorithms of 'cn10k' crypto driver.\n ;\n [Cipher]\n+NULL = Y\n+3DES CBC = Y\n+3DES ECB = Y\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+AES CTR (128) = Y\n+AES CTR (192) = Y\n+AES CTR (256) = Y\n+AES XTS (128) = Y\n+AES XTS (256) = Y\n+DES CBC = Y\n \n ;\n ; Supported authentication algorithms of 'cn10k' crypto driver.\n@@ -24,3 +40,7 @@ Digest encrypted = Y\n ; Supported AEAD algorithms of 'cn10k' crypto driver.\n ;\n [AEAD]\n+AES GCM (128) = Y\n+AES GCM (192) = Y\n+AES GCM (256) = Y\n+CHACHA20-POLY1305 = Y\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex c22b25c..7007d11 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -7,6 +7,10 @@\n Symmetric crypto = Y\n Sym operation chaining = Y\n HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In LB Out = Y\n+OOP SGL In SGL Out = Y\n+OOP LB In LB Out = Y\n Symmetric sessionless = Y\n Digest encrypted = Y\n \n@@ -14,6 +18,18 @@ Digest encrypted = Y\n ; Supported crypto algorithms of 'cn9k' crypto driver.\n ;\n [Cipher]\n+NULL = Y\n+3DES CBC = Y\n+3DES ECB = Y\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+AES CTR (128) = Y\n+AES CTR (192) = Y\n+AES CTR (256) = Y\n+AES XTS (128) = Y\n+AES XTS (256) = Y\n+DES CBC = Y\n \n ;\n ; Supported authentication algorithms of 'cn9k' crypto driver.\n@@ -24,3 +40,7 @@ Digest encrypted = Y\n ; Supported AEAD algorithms of 'cn9k' crypto driver.\n ;\n [AEAD]\n+AES GCM (128) = Y\n+AES GCM (192) = Y\n+AES GCM (256) = Y\n+CHACHA20-POLY1305 = Y\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c\nindex 8a31290..2ae61b5 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c\n@@ -83,6 +83,10 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\t RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n+\t\t\t RTE_CRYPTODEV_FF_IN_PLACE_SGL |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\t RTE_CRYPTODEV_FF_SYM_SESSIONLESS |\n \t\t\t RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED;\n \ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c\nindex 6b5c9e3..9a2d565 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c\n@@ -81,6 +81,10 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\t RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n+\t\t\t RTE_CRYPTODEV_FF_IN_PLACE_SGL |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\t RTE_CRYPTODEV_FF_SYM_SESSIONLESS |\n \t\t\t RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED;\n \ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 2110f49..e8be663 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -512,6 +512,327 @@ cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n }\n \n static __rte_always_inline int\n+cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)\n+{\n+\tuint32_t iv_offset = 0, size;\n+\tint32_t inputlen, outputlen, enc_dlen, auth_dlen;\n+\tstruct roc_se_ctx *se_ctx;\n+\tint32_t hash_type, mac_len;\n+\tuint8_t iv_len = 16;\n+\tstruct roc_se_buf_ptr *aad_buf = NULL;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len, aad_len = 0;\n+\tuint32_t passthrough_len = 0;\n+\tunion cpt_inst_w4 cpt_inst_w4;\n+\tvoid *offset_vaddr;\n+\tuint8_t op_minor;\n+\n+\tencr_offset = ROC_SE_ENCR_OFFSET(d_offs);\n+\tauth_offset = ROC_SE_AUTH_OFFSET(d_offs);\n+\tencr_data_len = ROC_SE_ENCR_DLEN(d_lens);\n+\tauth_data_len = ROC_SE_AUTH_DLEN(d_lens);\n+\n+\tif (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {\n+\t\t/* We don't support both AAD and auth data separately */\n+\t\tauth_data_len = 0;\n+\t\tauth_offset = 0;\n+\t\taad_len = fc_params->aad_buf.size;\n+\t\taad_buf = &fc_params->aad_buf;\n+\t}\n+\n+\tse_ctx = fc_params->ctx_buf.vaddr;\n+\thash_type = se_ctx->hash_type;\n+\tmac_len = se_ctx->mac_len;\n+\top_minor = se_ctx->template_w4.s.opcode_minor;\n+\n+\tif (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {\n+\t\tiv_len = 0;\n+\t\tiv_offset = ROC_SE_ENCR_IV_OFFSET(d_offs);\n+\t}\n+\n+\tif (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * When AAD is given, data above encr_offset is pass through\n+\t\t * Since AAD is given as separate pointer and not as offset,\n+\t\t * this is a special case as we need to fragment input data\n+\t\t * into passthrough + encr_data and then insert AAD in between.\n+\t\t */\n+\t\tif (hash_type != ROC_SE_GMAC_TYPE) {\n+\t\t\tpassthrough_len = encr_offset;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tencr_offset = passthrough_len + aad_len + iv_len;\n+\t\t\tauth_data_len = aad_len + encr_data_len;\n+\t\t} else {\n+\t\t\tpassthrough_len = 16 + aad_len;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tauth_data_len = aad_len;\n+\t\t}\n+\t} else {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/* Decryption */\n+\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;\n+\tcpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_DECRYPT;\n+\tcpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;\n+\n+\tif (hash_type == ROC_SE_GMAC_TYPE) {\n+\t\tencr_offset = 0;\n+\t\tencr_data_len = 0;\n+\t}\n+\n+\tenc_dlen = encr_offset + encr_data_len;\n+\tauth_dlen = auth_offset + auth_data_len;\n+\n+\tif (auth_dlen > enc_dlen) {\n+\t\tinputlen = auth_dlen + mac_len;\n+\t\toutputlen = auth_dlen;\n+\t} else {\n+\t\tinputlen = enc_dlen + mac_len;\n+\t\toutputlen = enc_dlen;\n+\t}\n+\n+\tif (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)\n+\t\toutputlen = inputlen = enc_dlen;\n+\n+\tcpt_inst_w4.s.param1 = encr_data_len;\n+\tcpt_inst_w4.s.param2 = auth_data_len;\n+\n+\t/*\n+\t * In cn9k, cn10k since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) &&\n+\t\t (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\n+\t\t/* Use Direct mode */\n+\n+\t\toffset_vaddr =\n+\t\t\t(uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - iv_len;\n+\t\tinst->dptr = (uint64_t)offset_vaddr;\n+\n+\t\t/* RPTR should just exclude offset control word */\n+\t\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n+\n+\t\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t} else {\n+\t\tvoid *m_vaddr = fc_params->meta_buf.vaddr;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tstruct roc_se_sglist_comp *gather_comp;\n+\t\tstruct roc_se_sglist_comp *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\t\tuint8_t i = 0;\n+\n+\t\t/* This falls under strict SG mode */\n+\t\toffset_vaddr = m_vaddr;\n+\t\tsize = ROC_SE_OFF_CTRL_LEN + iv_len;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\n+\t\tcpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word that includes iv */\n+\t\ti = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,\n+\t\t\t\t ROC_SE_OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* Add input data */\n+\t\tif (flags & ROC_SE_VALID_MAC_BUF) {\n+\t\t\tsize = inputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\t/* input data only */\n+\t\t\t\tif (unlikely(flags &\n+\t\t\t\t\t ROC_SE_SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\tgather_comp, i, fc_params->bufs,\n+\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\tfc_params->src_iov, 0, &size,\n+\t\t\t\t\t\taad_buf, aad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (unlikely(size)) {\n+\t\t\t\t\tplt_dp_err(\"Insufficient buffer\"\n+\t\t\t\t\t\t \" space, size %d needed\",\n+\t\t\t\t\t\t size);\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\t/* mac data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(gather_comp, i,\n+\t\t\t\t\t\t\t &fc_params->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* input data + mac */\n+\t\t\tsize = inputlen - iv_len;\n+\t\t\tif (size) {\n+\t\t\t\tif (unlikely(flags &\n+\t\t\t\t\t ROC_SE_SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\tgather_comp, i, fc_params->bufs,\n+\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\t\tif (unlikely(!fc_params->src_iov)) {\n+\t\t\t\t\t\tplt_dp_err(\"Bad input args\");\n+\t\t\t\t\t\treturn -1;\n+\t\t\t\t\t}\n+\n+\t\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\tfc_params->src_iov, 0, &size,\n+\t\t\t\t\t\taad_buf, aad_offset);\n+\t\t\t\t}\n+\n+\t\t\t\tif (unlikely(size)) {\n+\t\t\t\t\tplt_dp_err(\"Insufficient buffer\"\n+\t\t\t\t\t\t \" space, size %d needed\",\n+\t\t\t\t\t\t size);\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n+\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n+\t\t\t\t\t\t g_size_bytes);\n+\n+\t\t/* Add iv */\n+\t\tif (iv_len) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t (uint64_t)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* Add output data */\n+\t\tsize = outputlen - iv_len;\n+\t\tif (size) {\n+\t\t\tif (unlikely(flags & ROC_SE_SINGLE_BUF_INPLACE)) {\n+\t\t\t\t/* handle single buffer here */\n+\t\t\t\ti = fill_sg_comp_from_buf_min(scatter_comp, i,\n+\t\t\t\t\t\t\t fc_params->bufs,\n+\t\t\t\t\t\t\t &size);\n+\t\t\t} else {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(!fc_params->dst_iov)) {\n+\t\t\t\t\tplt_dp_err(\"Bad input args\");\n+\t\t\t\t\treturn -1;\n+\t\t\t\t}\n+\n+\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\tscatter_comp, i, fc_params->dst_iov, 0,\n+\t\t\t\t\t&size, aad_buf, aad_offset);\n+\t\t\t}\n+\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d needed\",\n+\t\t\t\t\t size);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len in case of SG mode */\n+\t\tcpt_inst_w4.s.dlen = size;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t}\n+\n+\tif (unlikely((encr_offset >> 16) || (iv_offset >> 8) ||\n+\t\t (auth_offset >> 8))) {\n+\t\tplt_dp_err(\"Offset not supported\");\n+\t\tplt_dp_err(\"enc_offset: %d\", encr_offset);\n+\t\tplt_dp_err(\"iv_offset : %d\", iv_offset);\n+\t\tplt_dp_err(\"auth_offset: %d\", auth_offset);\n+\t\treturn -1;\n+\t}\n+\n+\t*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(\n+\t\t((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) |\n+\t\t((uint64_t)auth_offset));\n+\n+\tinst->w4.u64 = cpt_inst_w4.u64;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *fc_params,\n+\t\t struct cpt_inst_s *inst)\n+{\n+\tstruct roc_se_ctx *ctx = fc_params->ctx_buf.vaddr;\n+\tuint8_t fc_type;\n+\tint ret = -1;\n+\n+\tfc_type = ctx->fc_type;\n+\n+\tif (likely(fc_type == ROC_SE_FC_GEN))\n+\t\tret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, inst);\n+\treturn ret;\n+}\n+\n+static __rte_always_inline int\n cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t\t struct roc_se_fc_params *fc_params,\n \t\t struct cpt_inst_s *inst)\n@@ -1192,7 +1513,8 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,\n \t\tret = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, &fc_params,\n \t\t\t\t\t inst);\n \telse\n-\t\tret = ENOTSUP;\n+\t\tret = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens, &fc_params,\n+\t\t\t\t\t inst);\n \n \tif (unlikely(ret)) {\n \t\tplt_dp_err(\"Preparing request failed due to bad input arg\");\n", "prefixes": [ "v2", "13/20" ] }