Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94830/?format=api
{ "id": 94830, "url": "https://patches.dpdk.org/api/patches/94830/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-7-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624600591-29841-7-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624600591-29841-7-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:56:17", "name": "[v2,06/20] crypto/cnxk: add enqueue burst op", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "19c6eebd890f4d9e4379cc8bddacc382af88130b", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624600591-29841-7-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17483, "url": "https://patches.dpdk.org/api/series/17483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17483", "date": "2021-06-25T05:56:11", "name": "Add Marvell CNXK crypto PMDs", "version": 2, "mbox": "https://patches.dpdk.org/series/17483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94830/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94830/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9B410A0C40;\n\tFri, 25 Jun 2021 07:57:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 68102410F8;\n\tFri, 25 Jun 2021 07:57:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id CF95D410F9\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:57:34 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5vFf7018374; Thu, 24 Jun 2021 22:57:34 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241shrn-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:57:34 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:57:31 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:57:31 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id AD8FE3F7041;\n Thu, 24 Jun 2021 22:57:28 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=K5XlYL0UVWATANuP2BR8Y+B0JM9zk5zyu6exbJLUSYY=;\n b=jKkA2X+kohM4hbkkEfpU76oFU9EgFBC6O1obngKl8kpXxarvfyEho5OtTaICaBrWJxmw\n qma/xEgKs25NPeRLLmY3LJA2IeMGQVJ6ZDabWtTzsWBIeVMvRZ43cXFhSEeJicIUcMiI\n j85FUgAOhyopZTsZWt6ElkXgk4cK1+bxWBZ6NzueFfDhBIkRP4/PLsgs1EpH7xRCTjGD\n OKwwN1Tf301gb/eRF24v9HQW0I6KPM0jPGkJkXAfjs9NC0VO1xqBazk5Y3QXq1LhGmmo\n J4l7zvZWBEdeoumaKefhEJVWlLBfOw8xEfrqIIiwwZZC+lX/q6keoLGbmBV3K6urrgbn Yw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n \"Ankur Dwivedi\" <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Archana Muniganti\n <marchana@marvell.com>", "Date": "Fri, 25 Jun 2021 11:26:17 +0530", "Message-ID": "<1624600591-29841-7-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624600591-29841-1-git-send-email-anoobj@marvell.com>", "References": "\n <http://patches.dpdk.org/project/dpdk/cover/1622652221-22732-1-git-send-email-anoobj@marvell.com/>\n <1624600591-29841-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "1kZhHnOF5uu8uzr1Mkujr7bWSyXm_64_", "X-Proofpoint-ORIG-GUID": "1kZhHnOF5uu8uzr1Mkujr7bWSyXm_64_", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_02:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 06/20] crypto/cnxk: add enqueue burst op", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add enqueue_burst op in cn9k & cn10k.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev.c | 2 +\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 189 ++++++++++++++++++++++++++++++\n drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 2 +\n drivers/crypto/cnxk/cn9k_cryptodev.c | 2 +\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 154 ++++++++++++++++++++++++\n drivers/crypto/cnxk/cn9k_cryptodev_ops.h | 2 +\n drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 9 ++\n 7 files changed, 360 insertions(+)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c\nindex a66b777..53f7a94 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c\n@@ -80,6 +80,8 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->dev_ops = &cn10k_cpt_ops;\n \tdev->driver_id = cn10k_cryptodev_driver_id;\n \n+\tcn10k_cpt_set_enqdeq_fns(dev);\n+\n \treturn 0;\n \n dev_fini:\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 34dc107..5dd2cd2 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -7,7 +7,196 @@\n \n #include \"cn10k_cryptodev.h\"\n #include \"cn10k_cryptodev_ops.h\"\n+#include \"cnxk_cryptodev.h\"\n #include \"cnxk_cryptodev_ops.h\"\n+#include \"cnxk_se.h\"\n+\n+static inline struct cnxk_se_sess *\n+cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op)\n+{\n+\tconst int driver_id = cn10k_cryptodev_driver_id;\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tstruct cnxk_se_sess *priv;\n+\tint ret;\n+\n+\t/* Create temporary session */\n+\tsess = rte_cryptodev_sym_session_create(qp->sess_mp);\n+\tif (sess == NULL)\n+\t\treturn NULL;\n+\n+\tret = sym_session_configure(qp->lf.roc_cpt, driver_id, sym_op->xform,\n+\t\t\t\t sess, qp->sess_mp_priv);\n+\tif (ret)\n+\t\tgoto sess_put;\n+\n+\tpriv = get_sym_session_private_data(sess, driver_id);\n+\n+\tsym_op->session = sess;\n+\n+\treturn priv;\n+\n+sess_put:\n+\trte_mempool_put(qp->sess_mp, sess);\n+\treturn NULL;\n+}\n+\n+static __rte_always_inline int __rte_hot\n+cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t struct cnxk_se_sess *sess, struct cpt_inflight_req *infl_req,\n+\t\t struct cpt_inst_s *inst)\n+{\n+\tRTE_SET_USED(qp);\n+\tRTE_SET_USED(op);\n+\tRTE_SET_USED(sess);\n+\tRTE_SET_USED(infl_req);\n+\tRTE_SET_USED(inst);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+static inline int\n+cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[],\n+\t\t struct cpt_inst_s inst[], struct cpt_inflight_req *infl_req)\n+{\n+\tstruct rte_crypto_sym_op *sym_op;\n+\tstruct cnxk_se_sess *sess;\n+\tstruct rte_crypto_op *op;\n+\tuint64_t w7;\n+\tint ret;\n+\n+\top = ops[0];\n+\n+\tinst[0].w0.u64 = 0;\n+\tinst[0].w2.u64 = 0;\n+\tinst[0].w3.u64 = 0;\n+\n+\tsym_op = op->sym;\n+\n+\tif (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\t\tsess = get_sym_session_private_data(\n+\t\t\t\tsym_op->session, cn10k_cryptodev_driver_id);\n+\t\t\tret = cpt_sym_inst_fill(qp, op, sess, infl_req,\n+\t\t\t\t\t\t&inst[0]);\n+\t\t\tif (unlikely(ret))\n+\t\t\t\treturn 0;\n+\t\t\tw7 = sess->cpt_inst_w7;\n+\t\t} else {\n+\t\t\tsess = cn10k_cpt_sym_temp_sess_create(qp, op);\n+\t\t\tif (unlikely(sess == NULL)) {\n+\t\t\t\tplt_dp_err(\"Could not create temp session\");\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\n+\t\t\tret = cpt_sym_inst_fill(qp, op, sess, infl_req,\n+\t\t\t\t\t\t&inst[0]);\n+\t\t\tif (unlikely(ret)) {\n+\t\t\t\tsym_session_clear(cn10k_cryptodev_driver_id,\n+\t\t\t\t\t\t op->sym->session);\n+\t\t\t\trte_mempool_put(qp->sess_mp, op->sym->session);\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t\tw7 = sess->cpt_inst_w7;\n+\t\t}\n+\t} else {\n+\t\tplt_dp_err(\"Unsupported op type\");\n+\t\treturn 0;\n+\t}\n+\n+\tinst[0].res_addr = (uint64_t)&infl_req->res;\n+\tinfl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;\n+\tinfl_req->cop = op;\n+\n+\tinst[0].w7.u64 = w7;\n+\n+\treturn 1;\n+}\n+\n+#define PKTS_PER_LOOP\t32\n+#define PKTS_PER_STEORL 16\n+\n+static uint16_t\n+cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tuint64_t lmt_base, lmt_arg, io_addr;\n+\tstruct cpt_inflight_req *infl_req;\n+\tuint16_t nb_allowed, count = 0;\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tstruct cpt_inst_s *inst;\n+\tuint16_t lmt_id;\n+\tint ret, i;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tnb_allowed = qp->lf.nb_desc - pend_q->pending_count;\n+\tnb_ops = RTE_MIN(nb_ops, nb_allowed);\n+\n+\tif (unlikely(nb_ops == 0))\n+\t\treturn 0;\n+\n+\tlmt_base = qp->lmtline.lmt_base;\n+\tio_addr = qp->lmtline.io_addr;\n+\n+\tROC_LMT_BASE_ID_GET(lmt_base, lmt_id);\n+\tinst = (struct cpt_inst_s *)lmt_base;\n+\n+again:\n+\tfor (i = 0; i < RTE_MIN(PKTS_PER_LOOP, nb_ops); i++) {\n+\t\tinfl_req = &pend_q->req_queue[pend_q->enq_tail];\n+\t\tinfl_req->op_flags = 0;\n+\n+\t\tret = cn10k_cpt_fill_inst(qp, ops + i, &inst[2 * i], infl_req);\n+\t\tif (unlikely(ret != 1)) {\n+\t\t\tplt_dp_err(\"Could not process op: %p\", ops + i);\n+\t\t\tif (i == 0)\n+\t\t\t\tgoto update_pending;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tMOD_INC(pend_q->enq_tail, qp->lf.nb_desc);\n+\t}\n+\n+\tif (i > PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG |\n+\t\t\t (i - PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t} else {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t}\n+\n+\trte_io_wmb();\n+\n+\tif (nb_ops - i > 0 && i == PKTS_PER_LOOP) {\n+\t\tnb_ops -= i;\n+\t\tops += i;\n+\t\tcount += i;\n+\t\tgoto again;\n+\t}\n+\n+update_pending:\n+\tpend_q->pending_count += count + i;\n+\n+\tpend_q->time_out = rte_get_timer_cycles() +\n+\t\t\t DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n+\n+\treturn count + i;\n+}\n+\n+void\n+cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)\n+{\n+\tdev->enqueue_burst = cn10k_cpt_enqueue_burst;\n+\n+\trte_mb();\n+}\n \n static void\n cn10k_cpt_dev_info_get(struct rte_cryptodev *dev,\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\nindex 24611bf..d500b7d 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n@@ -10,4 +10,6 @@\n \n extern struct rte_cryptodev_ops cn10k_cpt_ops;\n \n+void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n+\n #endif /* _CN10K_CRYPTODEV_OPS_H_ */\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c\nindex 46ad33f..4dbb40d 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c\n@@ -78,6 +78,8 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->dev_ops = &cn9k_cpt_ops;\n \tdev->driver_id = cn9k_cryptodev_driver_id;\n \n+\tcn9k_cpt_set_enqdeq_fns(dev);\n+\n \treturn 0;\n \n dev_fini:\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex bef6159..f09f9ee 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -7,7 +7,161 @@\n \n #include \"cn9k_cryptodev.h\"\n #include \"cn9k_cryptodev_ops.h\"\n+#include \"cnxk_cryptodev.h\"\n #include \"cnxk_cryptodev_ops.h\"\n+#include \"cnxk_se.h\"\n+\n+static __rte_always_inline int __rte_hot\n+cn9k_cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t struct cnxk_se_sess *sess,\n+\t\t struct cpt_inflight_req *infl_req,\n+\t\t struct cpt_inst_s *inst)\n+{\n+\tRTE_SET_USED(qp);\n+\tRTE_SET_USED(op);\n+\tRTE_SET_USED(sess);\n+\tRTE_SET_USED(infl_req);\n+\tRTE_SET_USED(inst);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+static inline struct cnxk_se_sess *\n+cn9k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op)\n+{\n+\tconst int driver_id = cn9k_cryptodev_driver_id;\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tstruct cnxk_se_sess *priv;\n+\tint ret;\n+\n+\t/* Create temporary session */\n+\tsess = rte_cryptodev_sym_session_create(qp->sess_mp);\n+\tif (sess == NULL)\n+\t\treturn NULL;\n+\n+\tret = sym_session_configure(qp->lf.roc_cpt, driver_id, sym_op->xform,\n+\t\t\t\t sess, qp->sess_mp_priv);\n+\tif (ret)\n+\t\tgoto sess_put;\n+\n+\tpriv = get_sym_session_private_data(sess, driver_id);\n+\n+\tsym_op->session = sess;\n+\n+\treturn priv;\n+\n+sess_put:\n+\trte_mempool_put(qp->sess_mp, sess);\n+\treturn NULL;\n+}\n+\n+static uint16_t\n+cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct cpt_inflight_req *infl_req;\n+\tstruct rte_crypto_sym_op *sym_op;\n+\tuint16_t nb_allowed, count = 0;\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tstruct cnxk_se_sess *sess;\n+\tstruct rte_crypto_op *op;\n+\tstruct cpt_inst_s inst;\n+\tuint64_t lmt_status;\n+\tuint64_t lmtline;\n+\tuint64_t io_addr;\n+\tint ret;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tlmtline = qp->lmtline.lmt_base;\n+\tio_addr = qp->lmtline.io_addr;\n+\n+\tinst.w0.u64 = 0;\n+\tinst.w2.u64 = 0;\n+\tinst.w3.u64 = 0;\n+\n+\tnb_allowed = qp->lf.nb_desc - pend_q->pending_count;\n+\tnb_ops = RTE_MIN(nb_ops, nb_allowed);\n+\n+\tfor (count = 0; count < nb_ops; count++) {\n+\t\top = ops[count];\n+\t\tinfl_req = &pend_q->req_queue[pend_q->enq_tail];\n+\t\tinfl_req->op_flags = 0;\n+\n+\t\tif (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\t\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\t\t\tsym_op = op->sym;\n+\t\t\t\tsess = get_sym_session_private_data(\n+\t\t\t\t\tsym_op->session,\n+\t\t\t\t\tcn9k_cryptodev_driver_id);\n+\t\t\t\tret = cn9k_cpt_sym_inst_fill(qp, op, sess,\n+\t\t\t\t\t\t\t infl_req, &inst);\n+\t\t\t} else {\n+\t\t\t\tsess = cn9k_cpt_sym_temp_sess_create(qp, op);\n+\t\t\t\tif (unlikely(sess == NULL)) {\n+\t\t\t\t\tplt_dp_err(\n+\t\t\t\t\t\t\"Could not create temp session\");\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\n+\t\t\t\tret = cn9k_cpt_sym_inst_fill(qp, op, sess,\n+\t\t\t\t\t\t\t infl_req, &inst);\n+\t\t\t\tif (unlikely(ret)) {\n+\t\t\t\t\tsym_session_clear(\n+\t\t\t\t\t\tcn9k_cryptodev_driver_id,\n+\t\t\t\t\t\top->sym->session);\n+\t\t\t\t\trte_mempool_put(qp->sess_mp,\n+\t\t\t\t\t\t\top->sym->session);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\tplt_dp_err(\"Unsupported op type\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (unlikely(ret)) {\n+\t\t\tplt_dp_err(\"Could not process op: %p\", op);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tinfl_req->cop = op;\n+\n+\t\tinfl_req->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\tinst.res_addr = (uint64_t)&infl_req->res;\n+\t\tinst.w7.u64 = sess->cpt_inst_w7;\n+\n+\t\tdo {\n+\t\t\t/* Copy CPT command to LMTLINE */\n+\t\t\tmemcpy((void *)lmtline, &inst, sizeof(inst));\n+\n+\t\t\t/*\n+\t\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t\t * LMTST transactions are always flushed from the write\n+\t\t\t * buffer immediately, a DMB is not required to push out\n+\t\t\t * LMTSTs.\n+\t\t\t */\n+\t\t\trte_io_wmb();\n+\t\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t\t} while (lmt_status == 0);\n+\n+\t\tMOD_INC(pend_q->enq_tail, qp->lf.nb_desc);\n+\t}\n+\n+\tpend_q->pending_count += count;\n+\tpend_q->time_out = rte_get_timer_cycles() +\n+\t\t\t DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n+\n+\treturn count;\n+}\n+\n+void\n+cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)\n+{\n+\tdev->enqueue_burst = cn9k_cpt_enqueue_burst;\n+\n+\trte_mb();\n+}\n \n static void\n cn9k_cpt_dev_info_get(struct rte_cryptodev *dev,\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\nindex 72fc297..2277f6b 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\n@@ -9,4 +9,6 @@\n \n extern struct rte_cryptodev_ops cn9k_cpt_ops;\n \n+void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n+\n #endif /* _CN9K_CRYPTODEV_OPS_H_ */\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\nindex 0a3c705..7995959 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n@@ -11,6 +11,11 @@\n \n #define CNXK_CPT_MIN_HEADROOM_REQ 24\n \n+/* Default command timeout in seconds */\n+#define DEFAULT_COMMAND_TIMEOUT 4\n+\n+#define MOD_INC(i, l) ((i) == (l - 1) ? (i) = 0 : (i)++)\n+\n struct cpt_qp_meta_info {\n \tstruct rte_mempool *pool;\n \tint mlen;\n@@ -26,6 +31,10 @@ enum sym_xform_type {\n \tCNXK_CPT_CIPHER_DEC_AUTH_VRFY\n };\n \n+#define CPT_OP_FLAGS_METABUF\t (1 << 1)\n+#define CPT_OP_FLAGS_AUTH_VERIFY (1 << 0)\n+#define CPT_OP_FLAGS_IPSEC_DIR_INBOUND (1 << 2)\n+\n struct cpt_inflight_req {\n \tunion cpt_res_s res;\n \tstruct rte_crypto_op *cop;\n", "prefixes": [ "v2", "06/20" ] }