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GET /api/patches/94816/?format=api
{ "id": 94816, "url": "https://patches.dpdk.org/api/patches/94816/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-11-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624599410-29689-11-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624599410-29689-11-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:36:42", "name": "[v2,10/17] common/cnxk: add SE microcode defines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "47450c39dc609f6b1f83433d041bb2397438db2a", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-11-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17482, "url": "https://patches.dpdk.org/api/series/17482/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17482", "date": "2021-06-25T05:36:32", "name": "Add CPT in Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/17482/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94816/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94816/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 671B3A0C40;\n\tFri, 25 Jun 2021 07:38:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D754240E03;\n\tFri, 25 Jun 2021 07:38:04 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 9137C40698\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:38:02 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5ZC18014300; Thu, 24 Jun 2021 22:38:02 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241sg6b-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:38:01 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:37:59 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:37:59 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id A76E93F7041;\n Thu, 24 Jun 2021 22:37:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=JGaSM4REWuTdPjxwetdKMz2vDkpn7eDXqAABJIbyh00=;\n b=Cm/IcaWsox3gTPcRdUMZPbzKwAA+PbOr16jPXa5emRWx+JYBLFDIY2/Q71sb/CEsmKP0\n 4wnR0MsQaGvOpeeVifpMF3AuiY0BtVIbvaURu5Wb0veaSZapZcr9jbeftMWWL5ILQ6YY\n X8wzrkxXNxVEHDGxKX3N+H1n+Oju4Rk9iL6s75yFRgGEbb5N4Y2PcYsaZr20NnjnbJCk\n RfzZFqKTWbycKystRJ7UW2hoxxloN2yffLKpdBZBP55hujcgG7cc2jKa/m5PAK2Ye3Im\n BipO1XsTdV8cAAygLz7z6cxe8sKXptiRXk9q4PckLC9MlBUCxKQ3oneiglCP+jPJwtna +A==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Kiran Kumar Kokkilagadda <kirankumark@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Anoob Joseph <anoobj@marvell.com>,\n Vidya Sagar Velumuri <vvelumuri@marvell.com>", "Date": "Fri, 25 Jun 2021 11:06:42 +0530", "Message-ID": "<1624599410-29689-11-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624599410-29689-1-git-send-email-anoobj@marvell.com>", "References": "\n <patches.dpdk.org/project/dpdk/patch/1622649385-22652-1-git-send-email-anoobj@marvell.com/>\n <1624599410-29689-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "TPpWMfB_HmBYxgB_SN9GHHqlGTOSaqP7", "X-Proofpoint-ORIG-GUID": "TPpWMfB_HmBYxgB_SN9GHHqlGTOSaqP7", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_01:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 10/17] common/cnxk: add SE microcode defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>\n\nMicrocode SE opcodes support symmetric operations. Add defines\nand structs defined by microcode.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_cpt.h | 34 ++++++\n drivers/common/cnxk/roc_se.h | 267 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 304 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_se.h", "diff": "diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 88a5611..6511614 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -109,4 +109,7 @@\n /* CPT */\n #include \"roc_cpt.h\"\n \n+/* CPT microcode */\n+#include \"roc_se.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex 83ef5c7..cb2838e 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -14,6 +14,40 @@\n \n #define ROC_CPT_MAX_LFS 64\n \n+/* CPT helper macros */\n+#define ROC_CPT_AH_HDR_LEN\t 12\n+#define ROC_CPT_AES_GCM_IV_LEN\t 8\n+#define ROC_CPT_AES_GCM_MAC_LEN\t 16\n+#define ROC_CPT_AES_CBC_IV_LEN\t 16\n+#define ROC_CPT_SHA1_HMAC_LEN\t 12\n+#define ROC_CPT_AUTH_KEY_LEN_MAX 64\n+\n+#define ROC_CPT_DES3_KEY_LEN\t 24\n+#define ROC_CPT_AES128_KEY_LEN\t 16\n+#define ROC_CPT_AES192_KEY_LEN\t 24\n+#define ROC_CPT_AES256_KEY_LEN\t 32\n+#define ROC_CPT_MD5_KEY_LENGTH\t 16\n+#define ROC_CPT_SHA1_KEY_LENGTH\t 20\n+#define ROC_CPT_SHA256_KEY_LENGTH 32\n+#define ROC_CPT_SHA384_KEY_LENGTH 48\n+#define ROC_CPT_SHA512_KEY_LENGTH 64\n+#define ROC_CPT_AUTH_KEY_LEN_MAX 64\n+\n+#define ROC_CPT_DES_BLOCK_LENGTH 8\n+#define ROC_CPT_AES_BLOCK_LENGTH 16\n+\n+#define ROC_CPT_AES_GCM_ROUNDUP_BYTE_LEN 4\n+#define ROC_CPT_AES_CBC_ROUNDUP_BYTE_LEN 16\n+\n+/* Salt length for AES-CTR/GCM/CCM and AES-GMAC */\n+#define ROC_CPT_SALT_LEN 4\n+\n+#define ROC_CPT_ESP_HDR_LEN\t 8\n+#define ROC_CPT_ESP_TRL_LEN\t 2\n+#define ROC_CPT_AH_HDR_LEN\t 12\n+#define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20\n+#define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40\n+\n struct roc_cpt_lf {\n \t/* Input parameters */\n \tuint16_t lf_id;\ndiff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h\nnew file mode 100644\nindex 0000000..ffae065\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_se.h\n@@ -0,0 +1,267 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __ROC_SE_H__\n+#define __ROC_SE_H__\n+\n+/* SE opcodes */\n+#define ROC_SE_MAJOR_OP_FC\t 0x33\n+#define ROC_SE_FC_MINOR_OP_ENCRYPT 0x0\n+#define ROC_SE_FC_MINOR_OP_DECRYPT 0x1\n+#define ROC_SE_FC_MINOR_OP_HMAC_FIRST 0x10\n+\n+#define ROC_SE_MAJOR_OP_HASH\t 0x34\n+#define ROC_SE_MAJOR_OP_HMAC\t 0x35\n+#define ROC_SE_MAJOR_OP_ZUC_SNOW3G 0x37\n+#define ROC_SE_MAJOR_OP_KASUMI\t 0x38\n+#define ROC_SE_MAJOR_OP_MISC\t 0x01\n+\n+#define ROC_SE_MAX_AAD_SIZE 64\n+#define ROC_SE_MAX_MAC_LEN 64\n+\n+#define ROC_SE_OFF_CTRL_LEN 8\n+#define ROC_SE_DMA_MODE\t (1 << 7)\n+\n+#define ROC_SE_MAX_SG_IN_OUT_CNT 32\n+#define ROC_SE_MAX_SG_CNT\t (ROC_SE_MAX_SG_IN_OUT_CNT / 2)\n+\n+#define ROC_SE_SG_LIST_HDR_SIZE (8u)\n+#define ROC_SE_SG_ENTRY_SIZE\tsizeof(struct roc_se_sglist_comp)\n+\n+#define ROC_SE_ZS_EA 0x1\n+#define ROC_SE_ZS_IA 0x2\n+#define ROC_SE_K_F8 0x4\n+#define ROC_SE_K_F9 0x8\n+\n+#define ROC_SE_FC_GEN\t 0x1\n+#define ROC_SE_PDCP\t 0x2\n+#define ROC_SE_KASUMI\t 0x3\n+#define ROC_SE_HASH_HMAC 0x4\n+\n+#define ROC_SE_OP_CIPHER_ENCRYPT 0x1\n+#define ROC_SE_OP_CIPHER_DECRYPT 0x2\n+#define ROC_SE_OP_CIPHER_MASK \\\n+\t(ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_CIPHER_DECRYPT)\n+\n+#define ROC_SE_OP_AUTH_VERIFY\t0x4\n+#define ROC_SE_OP_AUTH_GENERATE 0x8\n+#define ROC_SE_OP_AUTH_MASK \\\n+\t(ROC_SE_OP_AUTH_VERIFY | ROC_SE_OP_AUTH_GENERATE)\n+\n+#define ROC_SE_OP_ENCODE (ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_AUTH_GENERATE)\n+#define ROC_SE_OP_DECODE (ROC_SE_OP_CIPHER_DECRYPT | ROC_SE_OP_AUTH_VERIFY)\n+\n+#define ROC_SE_ALWAYS_USE_SEPARATE_BUF\n+\n+/*\n+ * Parameters for Flexi Crypto\n+ * requests\n+ */\n+#define ROC_SE_VALID_AAD_BUF\t 0x01\n+#define ROC_SE_VALID_MAC_BUF\t 0x02\n+#define ROC_SE_VALID_IV_BUF\t 0x04\n+#define ROC_SE_SINGLE_BUF_INPLACE 0x08\n+#define ROC_SE_SINGLE_BUF_HEADROOM 0x10\n+\n+#define ROC_SE_ENCR_IV_OFFSET(__d_offs) (((__d_offs) >> 32) & 0xffff)\n+#define ROC_SE_ENCR_OFFSET(__d_offs)\t(((__d_offs) >> 16) & 0xffff)\n+#define ROC_SE_AUTH_OFFSET(__d_offs)\t((__d_offs) & 0xffff)\n+#define ROC_SE_ENCR_DLEN(__d_lens)\t((__d_lens) >> 32)\n+#define ROC_SE_AUTH_DLEN(__d_lens)\t((__d_lens) & 0xffffffff)\n+\n+typedef enum { ROC_SE_FROM_CTX = 0, ROC_SE_FROM_DPTR = 1 } roc_se_input_type;\n+\n+typedef enum {\n+\tROC_SE_MD5_TYPE = 1,\n+\tROC_SE_SHA1_TYPE = 2,\n+\tROC_SE_SHA2_SHA224 = 3,\n+\tROC_SE_SHA2_SHA256 = 4,\n+\tROC_SE_SHA2_SHA384 = 5,\n+\tROC_SE_SHA2_SHA512 = 6,\n+\tROC_SE_GMAC_TYPE = 7,\n+\tROC_SE_POLY1305 = 8,\n+\tROC_SE_SHA3_SHA224 = 10,\n+\tROC_SE_SHA3_SHA256 = 11,\n+\tROC_SE_SHA3_SHA384 = 12,\n+\tROC_SE_SHA3_SHA512 = 13,\n+\tROC_SE_SHA3_SHAKE256 = 14,\n+\tROC_SE_SHA3_SHAKE512 = 15,\n+\n+\t/* These are only for software use */\n+\tROC_SE_ZUC_EIA3 = 0x90,\n+\tROC_SE_SNOW3G_UIA2 = 0x91,\n+\tROC_SE_AES_CMAC_EIA2 = 0x92,\n+\tROC_SE_KASUMI_F9_CBC = 0x93,\n+\tROC_SE_KASUMI_F9_ECB = 0x94,\n+} roc_se_auth_type;\n+\n+typedef enum {\n+\t/* To support passthrough */\n+\tROC_SE_PASSTHROUGH = 0x0,\n+\t/*\n+\t * These are defined by MC for Flexi crypto\n+\t * for field of 4 bits\n+\t */\n+\tROC_SE_DES3_CBC = 0x1,\n+\tROC_SE_DES3_ECB = 0x2,\n+\tROC_SE_AES_CBC = 0x3,\n+\tROC_SE_AES_ECB = 0x4,\n+\tROC_SE_AES_CFB = 0x5,\n+\tROC_SE_AES_CTR = 0x6,\n+\tROC_SE_AES_GCM = 0x7,\n+\tROC_SE_AES_XTS = 0x8,\n+\tROC_SE_CHACHA20 = 0x9,\n+\n+\t/* These are only for software use */\n+\tROC_SE_ZUC_EEA3 = 0x90,\n+\tROC_SE_SNOW3G_UEA2 = 0x91,\n+\tROC_SE_AES_CTR_EEA2 = 0x92,\n+\tROC_SE_KASUMI_F8_CBC = 0x93,\n+\tROC_SE_KASUMI_F8_ECB = 0x94,\n+} roc_se_cipher_type;\n+\n+typedef enum {\n+\t/* Microcode errors */\n+\tROC_SE_NO_ERR = 0x00,\n+\tROC_SE_ERR_OPCODE_UNSUPPORTED = 0x01,\n+\n+\t/* SCATTER GATHER */\n+\tROC_SE_ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,\n+\tROC_SE_ERR_SCATTER_GATHER_LIST = 0x03,\n+\tROC_SE_ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,\n+\n+\t/* SE GC */\n+\tROC_SE_ERR_GC_LENGTH_INVALID = 0x41,\n+\tROC_SE_ERR_GC_RANDOM_LEN_INVALID = 0x42,\n+\tROC_SE_ERR_GC_DATA_LEN_INVALID = 0x43,\n+\tROC_SE_ERR_GC_DRBG_TYPE_INVALID = 0x44,\n+\tROC_SE_ERR_GC_CTX_LEN_INVALID = 0x45,\n+\tROC_SE_ERR_GC_CIPHER_UNSUPPORTED = 0x46,\n+\tROC_SE_ERR_GC_AUTH_UNSUPPORTED = 0x47,\n+\tROC_SE_ERR_GC_OFFSET_INVALID = 0x48,\n+\tROC_SE_ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,\n+\tROC_SE_ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,\n+\tROC_SE_ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,\n+\tROC_SE_ERR_GC_ICV_MISCOMPARE = 0x4c,\n+\tROC_SE_ERR_GC_DATA_UNALIGNED = 0x4d,\n+\n+\t/* API Layer */\n+\tROC_SE_ERR_REQ_PENDING = 0xfe,\n+\tROC_SE_ERR_REQ_TIMEOUT = 0xff,\n+\n+} roc_se_error_code;\n+\n+typedef enum {\n+\tROC_SE_AES_128_BIT = 0x1,\n+\tROC_SE_AES_192_BIT = 0x2,\n+\tROC_SE_AES_256_BIT = 0x3\n+} roc_se_aes_type;\n+\n+struct roc_se_sglist_comp {\n+\tunion {\n+\t\tuint64_t len;\n+\t\tstruct {\n+\t\t\tuint16_t len[4];\n+\t\t} s;\n+\t} u;\n+\tuint64_t ptr[4];\n+};\n+\n+struct roc_se_enc_context {\n+\tuint64_t iv_source : 1;\n+\tuint64_t aes_key : 2;\n+\tuint64_t rsvd_60 : 1;\n+\tuint64_t enc_cipher : 4;\n+\tuint64_t auth_input_type : 1;\n+\tuint64_t rsvd_52_54 : 3;\n+\tuint64_t hash_type : 4;\n+\tuint64_t mac_len : 8;\n+\tuint64_t rsvd_39_0 : 40;\n+\tuint8_t encr_key[32];\n+\tuint8_t encr_iv[16];\n+};\n+\n+struct roc_se_hmac_context {\n+\tuint8_t ipad[64];\n+\tuint8_t opad[64];\n+};\n+\n+struct roc_se_context {\n+\tstruct roc_se_enc_context enc;\n+\tstruct roc_se_hmac_context hmac;\n+};\n+\n+struct roc_se_zuc_snow3g_ctx {\n+\tuint8_t encr_auth_iv[16];\n+\tuint8_t ci_key[16];\n+\tuint8_t zuc_const[32];\n+};\n+\n+struct roc_se_kasumi_ctx {\n+\tuint8_t reg_A[8];\n+\tuint8_t ci_key[16];\n+};\n+\n+/* Buffer pointer */\n+struct roc_se_buf_ptr {\n+\tvoid *vaddr;\n+\tuint32_t size;\n+\tuint32_t resv;\n+};\n+\n+/* IOV Pointer */\n+struct roc_se_iov_ptr {\n+\tint buf_cnt;\n+\tstruct roc_se_buf_ptr bufs[0];\n+};\n+\n+struct roc_se_fc_params {\n+\t/* 0th cache line */\n+\tunion {\n+\t\tstruct roc_se_buf_ptr bufs[1];\n+\t\tstruct {\n+\t\t\tstruct roc_se_iov_ptr *src_iov;\n+\t\t\tstruct roc_se_iov_ptr *dst_iov;\n+\t\t};\n+\t};\n+\tvoid *iv_buf;\n+\tvoid *auth_iv_buf;\n+\tstruct roc_se_buf_ptr meta_buf;\n+\tstruct roc_se_buf_ptr ctx_buf;\n+\tuint64_t rsvd2;\n+\n+\t/* 1st cache line */\n+\tstruct roc_se_buf_ptr aad_buf __plt_cache_aligned;\n+\tstruct roc_se_buf_ptr mac_buf;\n+};\n+\n+PLT_STATIC_ASSERT((offsetof(struct roc_se_fc_params, aad_buf) % 128) == 0);\n+\n+#define ROC_SE_PDCP_ALG_TYPE_ZUC 0\n+#define ROC_SE_PDCP_ALG_TYPE_SNOW3G 1\n+#define ROC_SE_PDCP_ALG_TYPE_AES_CTR 2\n+\n+struct roc_se_ctx {\n+\t/* Below fields are accessed by sw */\n+\tuint64_t enc_cipher : 8;\n+\tuint64_t hash_type : 8;\n+\tuint64_t mac_len : 8;\n+\tuint64_t auth_key_len : 8;\n+\tuint64_t fc_type : 4;\n+\tuint64_t hmac : 1;\n+\tuint64_t zsk_flags : 3;\n+\tuint64_t k_ecb : 1;\n+\tuint64_t pdcp_alg_type : 2;\n+\tuint64_t rsvd : 21;\n+\tunion cpt_inst_w4 template_w4;\n+\t/* Below fields are accessed by hardware */\n+\tunion {\n+\t\tstruct roc_se_context fctx;\n+\t\tstruct roc_se_zuc_snow3g_ctx zs_ctx;\n+\t\tstruct roc_se_kasumi_ctx k_ctx;\n+\t} se_ctx;\n+\tuint8_t auth_key[1024];\n+};\n+\n+#endif /* __ROC_SE_H__ */\n", "prefixes": [ "v2", "10/17" ] }