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GET /api/patches/94813/?format=api
{ "id": 94813, "url": "https://patches.dpdk.org/api/patches/94813/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-8-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624599410-29689-8-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624599410-29689-8-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:36:39", "name": "[v2,07/17] common/cnxk: add CPT diagnostics", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d0dcbd974c14223365338301e9e482563eb072e4", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-8-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17482, "url": "https://patches.dpdk.org/api/series/17482/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17482", "date": "2021-06-25T05:36:32", "name": "Add CPT in Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/17482/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94813/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94813/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 825E5A0C40;\n\tFri, 25 Jun 2021 07:37:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9B247410FE;\n\tFri, 25 Jun 2021 07:37:48 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id B5D6D40E46\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:37:47 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5ZC13014300; Thu, 24 Jun 2021 22:37:47 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39d241sg58-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:37:46 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:37:44 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:37:44 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 2D5EF3F7041;\n Thu, 24 Jun 2021 22:37:40 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=0LJ0uEs6ifnZQuUIAWtqRdZfLyGMdg5jvJ+NRU3IF+c=;\n b=jkK1m1aU24DwmBfsGMm1eVx5In/uvyVxXmREe9GOxrvIf6fZ0XpPBEiJJUSeElbHuBaW\n 0fJHY9Zrl/9BD0OJpOudK2SG4hp6vBm+LxWB5PcUIPoxKmsqPs8fKNOeG0qY04iaQ6be\n wvHGlZD1K8Dil4YVeUJr8FYEhpQ7bHuUezdiY8XBWiK2unXKyPSsaGhmwtwmj6rM8aFj\n oyHOkab5TGv9kGrX29ACuolThTNiXc9hI6180cYTXZ/lv5S3mQBlrd3xSobhIANbF14u\n H6wJz9pQoH6yRPuUFxPsCirFlf57AC1v721PJXT2lJK2aobf/dLpBXZVi8vmht5VZWhw Gg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Aakash Sasidharan <asasidharan@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>,\n Srujana Challa <schalla@marvell.com>", "Date": "Fri, 25 Jun 2021 11:06:39 +0530", "Message-ID": "<1624599410-29689-8-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624599410-29689-1-git-send-email-anoobj@marvell.com>", "References": "\n <patches.dpdk.org/project/dpdk/patch/1622649385-22652-1-git-send-email-anoobj@marvell.com/>\n <1624599410-29689-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "L-vvKvZw0sPemH-yjixSd1xmA0HJYaYX", "X-Proofpoint-ORIG-GUID": "L-vvKvZw0sPemH-yjixSd1xmA0HJYaYX", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_01:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 07/17] common/cnxk: add CPT diagnostics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Aakash Sasidharan <asasidharan@marvell.com>\n\nAdd routines to fetch and dump CPT statistics and states.\n\nSigned-off-by: Aakash Sasidharan <asasidharan@marvell.com>\nSigned-off-by: Srujana Challa <schalla@marvell.com>\n\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_cpt.c | 29 +++++++\n drivers/common/cnxk/roc_cpt.h | 3 +\n drivers/common/cnxk/roc_cpt_debug.c | 167 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 2 +\n 5 files changed, 202 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_cpt_debug.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 739e0e4..f139e0b 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -12,6 +12,7 @@ config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'\n deps = ['eal', 'pci', 'bus_pci', 'mbuf']\n sources = files(\n 'roc_cpt.c',\n+ 'roc_cpt_debug.c',\n 'roc_dev.c',\n 'roc_idev.c',\n 'roc_irq.c',\ndiff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex 02062c1..21c7704 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -188,6 +188,34 @@ cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)\n \tcpt_lf_unregister_done_irq(lf);\n }\n \n+static void\n+cpt_lf_dump(struct roc_cpt_lf *lf)\n+{\n+\tplt_cpt_dbg(\"CPT LF\");\n+\tplt_cpt_dbg(\"RBASE: 0x%016\" PRIx64, lf->rbase);\n+\tplt_cpt_dbg(\"LMT_BASE: 0x%016\" PRIx64, lf->lmt_base);\n+\tplt_cpt_dbg(\"MSIXOFF: 0x%x\", lf->msixoff);\n+\tplt_cpt_dbg(\"LF_ID: 0x%x\", lf->lf_id);\n+\tplt_cpt_dbg(\"NB DESC: %d\", lf->nb_desc);\n+\tplt_cpt_dbg(\"FC_ADDR: 0x%016\" PRIx64, (uintptr_t)lf->fc_addr);\n+\tplt_cpt_dbg(\"CQ.VADDR: 0x%016\" PRIx64, (uintptr_t)lf->iq_vaddr);\n+\n+\tplt_cpt_dbg(\"CPT LF REG:\");\n+\tplt_cpt_dbg(\"LF_CTL[0x%016llx]: 0x%016\" PRIx64, CPT_LF_CTL,\n+\t\t plt_read64(lf->rbase + CPT_LF_CTL));\n+\tplt_cpt_dbg(\"Q_SIZE[0x%016llx]: 0x%016\" PRIx64, CPT_LF_INPROG,\n+\t\t plt_read64(lf->rbase + CPT_LF_INPROG));\n+\n+\tplt_cpt_dbg(\"Q_BASE[0x%016llx]: 0x%016\" PRIx64, CPT_LF_Q_BASE,\n+\t\t plt_read64(lf->rbase + CPT_LF_Q_BASE));\n+\tplt_cpt_dbg(\"Q_SIZE[0x%016llx]: 0x%016\" PRIx64, CPT_LF_Q_SIZE,\n+\t\t plt_read64(lf->rbase + CPT_LF_Q_SIZE));\n+\tplt_cpt_dbg(\"Q_INST_PTR[0x%016llx]: 0x%016\" PRIx64, CPT_LF_Q_INST_PTR,\n+\t\t plt_read64(lf->rbase + CPT_LF_Q_INST_PTR));\n+\tplt_cpt_dbg(\"Q_GRP_PTR[0x%016llx]: 0x%016\" PRIx64, CPT_LF_Q_GRP_PTR,\n+\t\t plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR));\n+}\n+\n int\n roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)\n {\n@@ -484,6 +512,7 @@ cpt_lf_init(struct roc_cpt_lf *lf)\n \tif (rc)\n \t\tgoto disable_iq;\n \n+\tcpt_lf_dump(lf);\n \treturn 0;\n \n disable_iq:\ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex e258ca5..73ecb4e 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -63,5 +63,8 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);\n void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);\n int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);\n void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);\n+int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);\n+int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);\n void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);\n+\n #endif /* _ROC_CPT_H_ */\ndiff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c\nnew file mode 100644\nindex 0000000..9a9dcba\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_cpt_debug.c\n@@ -0,0 +1,167 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static int\n+cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tstruct cpt_rd_wr_reg_msg *msg;\n+\tstruct dev *dev = &cpt->dev;\n+\tint ret;\n+\n+\tmsg = mbox_alloc_msg_cpt_rd_wr_register(dev->mbox);\n+\tif (msg == NULL)\n+\t\treturn -EIO;\n+\n+\tmsg->hdr.pcifunc = dev->pf_func;\n+\n+\tmsg->is_write = 0;\n+\tmsg->reg_offset = reg;\n+\tmsg->ret_val = val;\n+\n+\tret = mbox_process_msg(dev->mbox, (void *)&msg);\n+\tif (ret)\n+\t\treturn -EIO;\n+\n+\t*val = msg->val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpt_sts_print(struct roc_cpt *roc_cpt)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tstruct dev *dev = &cpt->dev;\n+\tstruct cpt_sts_req *req;\n+\tstruct cpt_sts_rsp *rsp;\n+\tint ret;\n+\n+\treq = mbox_alloc_msg_cpt_sts_get(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn -EIO;\n+\n+\treq->blkaddr = 0;\n+\tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn -EIO;\n+\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"inst_req_pc\", rsp->inst_req_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"inst_lat_pc\", rsp->inst_lat_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"rd_req_pc\", rsp->rd_req_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"rd_lat_pc\", rsp->rd_lat_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"rd_uc_pc\", rsp->rd_uc_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"active_cycles_pc\",\n+\t\t rsp->active_cycles_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"ctx_mis_pc\", rsp->ctx_mis_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"ctx_hit_pc\", rsp->ctx_hit_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"ctx_aop_pc\", rsp->ctx_aop_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_aop_lat_pc\",\n+\t\t rsp->ctx_aop_lat_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_ifetch_pc\",\n+\t\t rsp->ctx_ifetch_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_ifetch_lat_pc\",\n+\t\t rsp->ctx_ifetch_lat_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_ffetch_pc\",\n+\t\t rsp->ctx_ffetch_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_ffetch_lat_pc\",\n+\t\t rsp->ctx_ffetch_lat_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_wback_pc\", rsp->ctx_wback_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_wback_lat_pc\",\n+\t\t rsp->ctx_wback_lat_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"ctx_psh_pc\", rsp->ctx_psh_pc);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_psh_lat_pc\",\n+\t\t rsp->ctx_psh_lat_pc);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"ctx_err\", rsp->ctx_err);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"ctx_enc_id\", rsp->ctx_enc_id);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"ctx_flush_timer\",\n+\t\t rsp->ctx_flush_timer);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"rxc_time\", rsp->rxc_time);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"rxc_time_cfg\", rsp->rxc_time_cfg);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"rxc_active_sts\",\n+\t\t rsp->rxc_active_sts);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"rxc_zombie_sts\",\n+\t\t rsp->rxc_zombie_sts);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"rxc_dfrg\", rsp->rxc_dfrg);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"x2p_link_cfg0\",\n+\t\t rsp->x2p_link_cfg0);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"x2p_link_cfg1\",\n+\t\t rsp->x2p_link_cfg1);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"busy_sts_ae\", rsp->busy_sts_ae);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"free_sts_ae\", rsp->free_sts_ae);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"busy_sts_se\", rsp->busy_sts_se);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"free_sts_se\", rsp->free_sts_se);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"busy_sts_ie\", rsp->busy_sts_ie);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"free_sts_ie\", rsp->free_sts_ie);\n+\tplt_print(\" %s:\\t0x%016\" PRIx64, \"exe_err_info\", rsp->exe_err_info);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"cptclk_cnt\", rsp->cptclk_cnt);\n+\tplt_print(\" %s:\\t\\t0x%016\" PRIx64, \"diag\", rsp->diag);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_cpt_afs_print(struct roc_cpt *roc_cpt)\n+{\n+\tuint64_t reg_val;\n+\n+\tplt_print(\"CPT AF registers:\");\n+\n+\tif (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), ®_val))\n+\t\treturn -EIO;\n+\n+\tplt_print(\" CPT_AF_LF0_CTL:\\t0x%016\" PRIx64, reg_val);\n+\n+\tif (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), ®_val))\n+\t\treturn -EIO;\n+\n+\tplt_print(\" CPT_AF_LF0_CTL2:\\t0x%016\" PRIx64, reg_val);\n+\n+\tcpt_sts_print(roc_cpt);\n+\n+\treturn 0;\n+}\n+\n+static void\n+cpt_lf_print(struct roc_cpt_lf *lf)\n+{\n+\tuint64_t reg_val;\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);\n+\tplt_print(\" Encrypted byte count:\\t%\" PRIu64, reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);\n+\tplt_print(\" Encrypted packet count:\\t%\" PRIu64, reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);\n+\tplt_print(\" Decrypted byte count:\\t%\" PRIu64, reg_val);\n+\n+\treg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);\n+\tplt_print(\" Decrypted packet count:\\t%\" PRIu64, reg_val);\n+}\n+\n+int\n+roc_cpt_lfs_print(struct roc_cpt *roc_cpt)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tstruct roc_cpt_lf *lf;\n+\tint lf_id;\n+\n+\tif (cpt == NULL)\n+\t\treturn -EINVAL;\n+\n+\tfor (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) {\n+\t\tlf = roc_cpt->lf[lf_id];\n+\t\tif (lf == NULL)\n+\t\t\tcontinue;\n+\n+\t\tplt_print(\"Count registers for CPT LF%d:\", lf_id);\n+\t\tcpt_lf_print(lf);\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 128997e..87130df 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -11,6 +11,7 @@ INTERNAL {\n \tcnxk_logtype_tim;\n \tcnxk_logtype_tm;\n \troc_clk_freq_get;\n+\troc_cpt_afs_print;\n \troc_cpt_dev_clear;\n \troc_cpt_dev_configure;\n \troc_cpt_dev_fini;\n@@ -19,6 +20,7 @@ INTERNAL {\n \troc_cpt_iq_disable;\n \troc_cpt_lf_init;\n \troc_cpt_lf_fini;\n+\troc_cpt_lfs_print;\n \troc_cpt_rxc_time_cfg;\n \troc_error_msg_get;\n \troc_idev_cpt_get;\n", "prefixes": [ "v2", "07/17" ] }