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GET /api/patches/94809/?format=api
{ "id": 94809, "url": "https://patches.dpdk.org/api/patches/94809/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-4-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624599410-29689-4-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624599410-29689-4-git-send-email-anoobj@marvell.com", "date": "2021-06-25T05:36:35", "name": "[v2,03/17] common/cnxk: add CPT dev config routines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2f56df22e760f4ed8a83ba774eeba8c3829ba3a7", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624599410-29689-4-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 17482, "url": "https://patches.dpdk.org/api/series/17482/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17482", "date": "2021-06-25T05:36:32", "name": "Add CPT in Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/17482/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94809/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 20D0BA0C40;\n\tFri, 25 Jun 2021 07:37:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8781E410E6;\n\tFri, 25 Jun 2021 07:37:26 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 1197A410E5\n for <dev@dpdk.org>; Fri, 25 Jun 2021 07:37:24 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15P5aK5M018492; Thu, 24 Jun 2021 22:37:24 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 39d24dhh24-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 24 Jun 2021 22:37:24 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 24 Jun 2021 22:37:22 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 24 Jun 2021 22:37:22 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 0B2DA3F7041;\n Thu, 24 Jun 2021 22:37:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=yEfc6WIFNjEjtfIRy0oDyHvtpmfnDpHgwbbad3voeok=;\n b=AuTJFeoTes8kIjmKYIioT4dLdq+oLFgg1owRKK5CInmCWaomZQpwYkX4dUME8pgVmxGo\n pj/11v4abY6fyyPhbaKt3UqYfH+0kzmDF5E87sepIxUwIzyr8180OG79+ynZDIJvrZxZ\n Z8EqjJzupCOdOdIl/L2lf2RK9Ro24g+D19oxoC+e0GPm/nS+cuoJy3amM9KO729fQ6a0\n 5dkdxPYiHxz6OdkqOuKzMkX2WJf0smYnDHbwXyl3Sj6vOTdPO8K/R+OCVhicszMtk8gk\n Rh4mvDOSTlHAB7Z+p5YuFVk4fzruMhunFUYK54wvN7VDO9xHkGNWfGhAZbqI7Zuiosfw dA==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n \"Ankur Dwivedi\" <adwivedi@marvell.com>, Tejasree Kondoj\n <ktejasree@marvell.com>, <dev@dpdk.org>, Archana Muniganti\n <marchana@marvell.com>, \"Vidya Sagar Velumuri\" <vvelumuri@marvell.com>", "Date": "Fri, 25 Jun 2021 11:06:35 +0530", "Message-ID": "<1624599410-29689-4-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1624599410-29689-1-git-send-email-anoobj@marvell.com>", "References": "\n <patches.dpdk.org/project/dpdk/patch/1622649385-22652-1-git-send-email-anoobj@marvell.com/>\n <1624599410-29689-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "wPBbsn-1Hl6ny0PhrVByyHsm1Js9u6vU", "X-Proofpoint-ORIG-GUID": "wPBbsn-1Hl6ny0PhrVByyHsm1Js9u6vU", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-25_01:2021-06-24,\n 2021-06-25 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 03/17] common/cnxk: add CPT dev config routines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add routines to init, fini, configure & clear CPT device.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_cpt.c | 308 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_cpt.h | 37 +++++\n drivers/common/cnxk/roc_cpt_priv.h | 37 +++++\n drivers/common/cnxk/roc_dev.c | 2 +\n drivers/common/cnxk/roc_dev_priv.h | 1 +\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 8 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/version.map | 6 +\n 11 files changed, 407 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_cpt.c\n create mode 100644 drivers/common/cnxk/roc_cpt.h\n create mode 100644 drivers/common/cnxk/roc_cpt_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 178bce7..739e0e4 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -11,6 +11,7 @@ endif\n config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'\n deps = ['eal', 'pci', 'bus_pci', 'mbuf']\n sources = files(\n+ 'roc_cpt.c',\n 'roc_dev.c',\n 'roc_idev.c',\n 'roc_irq.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 049854d..88a5611 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -106,4 +106,7 @@\n /* Idev */\n #include \"roc_idev.h\"\n \n+/* CPT */\n+#include \"roc_cpt.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nnew file mode 100644\nindex 0000000..2376125\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -0,0 +1,308 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+int\n+cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\tint rc;\n+\n+\t/* Get MSIX vector offsets */\n+\tmbox_alloc_msg_msix_offset(mbox);\n+\trc = mbox_process_msg(mbox, (void *)msix_rsp);\n+\n+\treturn rc;\n+}\n+\n+int\n+cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct rsrc_attach_req *req;\n+\n+\tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)\n+\t\treturn -EINVAL;\n+\n+\t/* Attach CPT(lf) */\n+\treq = mbox_alloc_msg_attach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->cptlfs = nb_lf;\n+\treq->modify = modify;\n+\treq->cpt_blkaddr = blkaddr;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n+cpt_lfs_detach(struct dev *dev)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct rsrc_detach_req *req;\n+\n+\treq = mbox_alloc_msg_detach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->cptlfs = 1;\n+\treq->partial = 1;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static int\n+cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct free_rsrcs_rsp *rsp;\n+\tint rc;\n+\n+\tmbox_alloc_msg_free_rsrc_cnt(mbox);\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn -EIO;\n+\n+\t*nb_lf = rsp->cpt;\n+\treturn 0;\n+}\n+\n+int\n+cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n+\t bool inl_dev_sso)\n+{\n+\tstruct cpt_lf_alloc_req_msg *req;\n+\tstruct mbox *mbox = dev->mbox;\n+\n+\tif (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)\n+\t\treturn -EINVAL;\n+\n+\tPLT_SET_USED(inl_dev_sso);\n+\n+\treq = mbox_alloc_msg_cpt_lf_alloc(mbox);\n+\treq->nix_pf_func = 0;\n+\treq->sso_pf_func = idev_sso_pffunc_get();\n+\treq->eng_grpmsk = eng_grpmsk;\n+\treq->blkaddr = blkaddr;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n+cpt_lfs_free(struct dev *dev)\n+{\n+\tmbox_alloc_msg_cpt_lf_free(dev->mbox);\n+\n+\treturn mbox_process(dev->mbox);\n+}\n+\n+static int\n+cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)\n+{\n+\tstruct cpt_caps_rsp_msg *rsp;\n+\tint ret;\n+\n+\tmbox_alloc_msg_cpt_caps_get(dev->mbox);\n+\n+\tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn -EIO;\n+\n+\tmbox_memcpy(hw_caps, rsp->eng_caps,\n+\t\t sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tuint8_t blkaddr = RVU_BLOCK_ADDR_CPT0;\n+\tstruct msix_offset_rsp *rsp;\n+\tuint8_t eng_grpmsk;\n+\tint rc, i;\n+\n+\t/* Request LF resources */\n+\trc = cpt_lfs_attach(&cpt->dev, blkaddr, false, nb_lf);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\teng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |\n+\t\t (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |\n+\t\t (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);\n+\n+\trc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr, false);\n+\tif (rc)\n+\t\tgoto lfs_detach;\n+\n+\trc = cpt_get_msix_offset(&cpt->dev, &rsp);\n+\tif (rc)\n+\t\tgoto lfs_free;\n+\n+\tfor (i = 0; i < nb_lf; i++)\n+\t\tcpt->lf_msix_off[i] =\n+\t\t\t(cpt->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ?\n+\t\t\t\trsp->cpt1_lf_msixoff[i] :\n+\t\t\t\trsp->cptlf_msixoff[i];\n+\n+\troc_cpt->nb_lf = nb_lf;\n+\n+\treturn 0;\n+\n+lfs_free:\n+\tcpt_lfs_free(&cpt->dev);\n+lfs_detach:\n+\tcpt_lfs_detach(&cpt->dev);\n+\treturn rc;\n+}\n+\n+uint64_t\n+cpt_get_blkaddr(struct dev *dev)\n+{\n+\tuint64_t reg;\n+\tuint64_t off;\n+\n+\t/* Reading the discovery register to know which CPT is the LF\n+\t * attached to. Assume CPT LF's of only one block are attached\n+\t * to a pffunc.\n+\t */\n+\tif (dev_is_vf(dev))\n+\t\toff = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);\n+\telse\n+\t\toff = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);\n+\n+\treg = plt_read64(dev->bar2 + off);\n+\n+\treturn reg & 0x1FFULL ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;\n+}\n+\n+int\n+roc_cpt_dev_init(struct roc_cpt *roc_cpt)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tuint16_t nb_lf_avail;\n+\tstruct dev *dev;\n+\tstruct cpt *cpt;\n+\tint rc;\n+\n+\tif (roc_cpt == NULL || roc_cpt->pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct cpt) <= ROC_CPT_MEM_SZ);\n+\n+\tcpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tmemset(cpt, 0, sizeof(*cpt));\n+\tpci_dev = roc_cpt->pci_dev;\n+\tdev = &cpt->dev;\n+\n+\t/* Initialize device */\n+\trc = dev_init(dev, pci_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc device\");\n+\t\tgoto fail;\n+\t}\n+\n+\tcpt->pci_dev = pci_dev;\n+\troc_cpt->lmt_base = dev->lmt_base;\n+\n+\trc = cpt_hardware_caps_get(dev, roc_cpt->hw_caps);\n+\tif (rc) {\n+\t\tplt_err(\"Could not determine hardware capabilities\");\n+\t\tgoto fail;\n+\t}\n+\n+\trc = cpt_available_lfs_get(&cpt->dev, &nb_lf_avail);\n+\tif (rc) {\n+\t\tplt_err(\"Could not get available lfs\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Reserve 1 CPT LF for inline inbound */\n+\tnb_lf_avail = PLT_MIN(nb_lf_avail, ROC_CPT_MAX_LFS - 1);\n+\n+\troc_cpt->nb_lf_avail = nb_lf_avail;\n+\n+\tdev->roc_cpt = roc_cpt;\n+\n+\treturn 0;\n+\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_cpt_dev_fini(struct roc_cpt *roc_cpt)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\n+\tif (cpt == NULL)\n+\t\treturn -EINVAL;\n+\n+\troc_cpt->nb_lf_avail = 0;\n+\n+\troc_cpt->lmt_base = 0;\n+\n+\treturn dev_fini(&cpt->dev, cpt->pci_dev);\n+}\n+\n+void\n+roc_cpt_dev_clear(struct roc_cpt *roc_cpt)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tint i;\n+\n+\tif (cpt == NULL)\n+\t\treturn;\n+\n+\tfor (i = 0; i < roc_cpt->nb_lf; i++)\n+\t\tcpt->lf_msix_off[i] = 0;\n+\n+\troc_cpt->nb_lf = 0;\n+\n+\tcpt_lfs_free(&cpt->dev);\n+\n+\tcpt_lfs_detach(&cpt->dev);\n+}\n+\n+int\n+roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)\n+{\n+\tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n+\tstruct dev *dev = &cpt->dev;\n+\tstruct cpt_eng_grp_req *req;\n+\tstruct cpt_eng_grp_rsp *rsp;\n+\tint ret;\n+\n+\treq = mbox_alloc_msg_cpt_eng_grp_get(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn -EIO;\n+\n+\tswitch (eng_type) {\n+\tcase CPT_ENG_TYPE_AE:\n+\tcase CPT_ENG_TYPE_SE:\n+\tcase CPT_ENG_TYPE_IE:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treq->eng_type = eng_type;\n+\tret = mbox_process_msg(dev->mbox, (void *)&rsp);\n+\tif (ret)\n+\t\treturn -EIO;\n+\n+\tif (rsp->eng_grp_num > 8) {\n+\t\tplt_err(\"Invalid CPT engine group\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\troc_cpt->eng_grp[eng_type] = rsp->eng_grp_num;\n+\n+\treturn rsp->eng_grp_num;\n+}\ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nnew file mode 100644\nindex 0000000..4e1cf84\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_CPT_H_\n+#define _ROC_CPT_H_\n+\n+#include \"roc_api.h\"\n+\n+/* Default engine groups */\n+#define ROC_CPT_DFLT_ENG_GRP_SE\t 0UL\n+#define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL\n+#define ROC_CPT_DFLT_ENG_GRP_AE\t 2UL\n+\n+#define ROC_CPT_MAX_LFS 64\n+\n+struct roc_cpt {\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];\n+\tuint16_t nb_lf;\n+\tuint16_t nb_lf_avail;\n+\tuintptr_t lmt_base;\n+\t/**< CPT device capabilities */\n+\tunion cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];\n+\tuint8_t eng_grp[CPT_MAX_ENG_TYPES];\n+\n+#define ROC_CPT_MEM_SZ (6 * 1024)\n+\tuint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);\n+int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);\n+int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,\n+\t\t\t\t enum cpt_eng_type eng_type);\n+int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);\n+void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);\n+#endif /* _ROC_CPT_H_ */\ndiff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h\nnew file mode 100644\nindex 0000000..0ef6774\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_cpt_priv.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_CPT_PRIV_H_\n+#define _ROC_CPT_PRIV_H_\n+\n+/* Set number of hystbits to 6.\n+ * This will trigger the FC writes whenever number of outstanding commands in\n+ * the queue becomes multiple of 32.\n+ */\n+#define CPT_FC_NUM_HYST_BITS 6\n+\n+struct cpt {\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev dev;\n+\tuint16_t lf_msix_off[ROC_CPT_MAX_LFS];\n+\tuint8_t lf_blkaddr[ROC_CPT_MAX_LFS];\n+} __plt_cache_aligned;\n+\n+static inline struct cpt *\n+roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt)\n+{\n+\treturn (struct cpt *)&roc_cpt->reserved[0];\n+}\n+\n+int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify,\n+\t\t uint16_t nb_lf);\n+int cpt_lfs_detach(struct dev *dev);\n+int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,\n+\t\t bool inl_dev_sso);\n+int cpt_lfs_free(struct dev *dev);\n+\n+int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);\n+uint64_t cpt_get_blkaddr(struct dev *dev);\n+\n+#endif /* _ROC_CPT_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex a39acc9..052ebe0 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -870,6 +870,8 @@ dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev)\n \t\tbreak;\n \tcase PCI_DEVID_CNXK_RVU_SSO_TIM_VF:\n \tcase PCI_DEVID_CNXK_RVU_NPA_VF:\n+\tcase PCI_DEVID_CN10K_RVU_CPT_VF:\n+\tcase PCI_DEVID_CN9K_RVU_CPT_VF:\n \tcase PCI_DEVID_CNXK_RVU_AF_VF:\n \tcase PCI_DEVID_CNXK_RVU_VF:\n \tcase PCI_DEVID_CNXK_RVU_SDP_VF:\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex 910cfb6..f8277fb 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -83,6 +83,7 @@ struct dev {\n \tuint16_t maxvf;\n \tstruct dev_ops *ops;\n \tvoid *roc_nix;\n+\tvoid *roc_cpt;\n \tbool disable_shared_lmt; /* false(default): shared lmt mode enabled */\n } __plt_cache_aligned;\n \ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 3999fce..74dbdec 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -58,6 +58,7 @@ roc_plt_init(void)\n \n RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 7864fa4..daee100 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -139,6 +139,7 @@\n /* Log */\n extern int cnxk_logtype_base;\n extern int cnxk_logtype_mbox;\n+extern int cnxk_logtype_cpt;\n extern int cnxk_logtype_npa;\n extern int cnxk_logtype_nix;\n extern int cnxk_logtype_npc;\n@@ -161,6 +162,7 @@ extern int cnxk_logtype_tm;\n \t\t##args)\n \n #define plt_base_dbg(fmt, ...)\tplt_dbg(base, fmt, ##__VA_ARGS__)\n+#define plt_cpt_dbg(fmt, ...)\tplt_dbg(cpt, fmt, ##__VA_ARGS__)\n #define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n #define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n #define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n@@ -169,6 +171,12 @@ extern int cnxk_logtype_tm;\n #define plt_tim_dbg(fmt, ...)\tplt_dbg(tim, fmt, ##__VA_ARGS__)\n #define plt_tm_dbg(fmt, ...)\tplt_dbg(tm, fmt, ##__VA_ARGS__)\n \n+/* Datapath logs */\n+#define plt_dp_err(fmt, args...) \\\n+\tRTE_LOG_DP(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n+#define plt_dp_info(fmt, args...) \\\n+\tRTE_LOG_DP(INFO, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n+\n #ifdef __cplusplus\n #define CNXK_PCI_ID(subsystem_dev, dev) \\\n \t{ \\\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 5e7564c..54c28fc 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -32,4 +32,7 @@\n /* TIM */\n #include \"roc_tim_priv.h\"\n \n+/* CPT */\n+#include \"roc_cpt_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 8e67c83..f8e286e 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -2,6 +2,7 @@ INTERNAL {\n \tglobal:\n \n \tcnxk_logtype_base;\n+\tcnxk_logtype_cpt;\n \tcnxk_logtype_mbox;\n \tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n@@ -10,6 +11,11 @@ INTERNAL {\n \tcnxk_logtype_tim;\n \tcnxk_logtype_tm;\n \troc_clk_freq_get;\n+\troc_cpt_dev_clear;\n+\troc_cpt_dev_configure;\n+\troc_cpt_dev_fini;\n+\troc_cpt_dev_init;\n+\troc_cpt_eng_grp_add;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n \troc_idev_npa_maxpools_get;\n", "prefixes": [ "v2", "03/17" ] }