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GET /api/patches/94752/?format=api
{ "id": 94752, "url": "https://patches.dpdk.org/api/patches/94752/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-59-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-59-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-59-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:58", "name": "[v4,58/62] net/cnxk: add time read/write/adjust operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "24091e7acd5362179b94930e5a233a637d390f13", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-59-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94752/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94752/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AAA35A0C41;\n\tWed, 23 Jun 2021 06:53:27 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 22ED5411F5;\n\tWed, 23 Jun 2021 06:50:29 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id B230341101\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:50:27 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k6fr025518 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:50:27 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gwj-6\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:50:26 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:50:25 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:50:25 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 710795B6937;\n Tue, 22 Jun 2021 21:50:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=VP06aFeVkkqXvEk1qKxZktoVQ0KL3FbjgCXgMHkz7bM=;\n b=XSbgA7h95edsujXWtAIrWLaC9NcW8hJm/jQw1QSoppj9hJDGaET/HZreRWdU7tDomkLJ\n xqW6QagOm+kF3vIUjQ+MidTgVcIyweUI1vQDf98gm7Gnljr1BrJg16BXsTssSZpccmw9\n CTtaGFFVZ7O7GLcBkx8sfaxWJcMSkLKzW5BPC5CauM+8d7jJQsb5gW0o2xQKWYKXajHR\n pPj5YZZ6NreLBjMLDGC6/ctR0gU6Irdfebqy98gk+bC4bqGDfuhSwBA8AnsTNXoIFO2g\n 2e0445rpNVE8mEdp7rLAUg0DqSutNNENeNffUjs0qbOEuZWwOQTeDmgX2oHE8lm5kCvK +A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:58 +0530", "Message-ID": "<20210623044702.4240-59-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "5ELbABPmroWlbS7CMTKK1NKN-AMxDTPz", "X-Proofpoint-GUID": "5ELbABPmroWlbS7CMTKK1NKN-AMxDTPz", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 58/62] net/cnxk: add time read/write/adjust\n operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nPatch implements read/write/adjust time operations for\ncn9k and cn10k platforms.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 3 ++\n drivers/net/cnxk/cnxk_ethdev.h | 5 ++++\n drivers/net/cnxk/cnxk_ptp.c | 63 ++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 71 insertions(+)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex cb583b4..c8bbb7a 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -1262,6 +1262,9 @@ struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.get_reg = cnxk_nix_dev_get_reg,\n \t.timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp,\n \t.timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp,\n+\t.timesync_read_time = cnxk_nix_timesync_read_time,\n+\t.timesync_write_time = cnxk_nix_timesync_write_time,\n+\t.timesync_adjust_time = cnxk_nix_timesync_adjust_time,\n };\n \n static int\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 76df84a..4214365 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -317,6 +317,11 @@ int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,\n \t\t\t\t\tuint32_t flags);\n int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,\n \t\t\t\t\tstruct timespec *timestamp);\n+int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev,\n+\t\t\t\tstruct timespec *ts);\n+int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,\n+\t\t\t\t const struct timespec *ts);\n+int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);\n int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);\n \n uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);\ndiff --git a/drivers/net/cnxk/cnxk_ptp.c b/drivers/net/cnxk/cnxk_ptp.c\nindex 7b00f87..52f6eb1 100644\n--- a/drivers/net/cnxk/cnxk_ptp.c\n+++ b/drivers/net/cnxk/cnxk_ptp.c\n@@ -56,6 +56,69 @@ cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev)\n }\n \n int\n+cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev, struct timespec *ts)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct roc_nix *nix = &dev->nix;\n+\tuint64_t clock, ns;\n+\tint rc;\n+\n+\trc = roc_nix_ptp_clock_read(nix, &clock, NULL, false);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tns = rte_timecounter_update(&dev->systime_tc, clock);\n+\t*ts = rte_ns_to_timespec(ns);\n+\treturn 0;\n+}\n+\n+int\n+cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,\n+\t\t\t const struct timespec *ts)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tuint64_t ns;\n+\n+\tns = rte_timespec_to_ns(ts);\n+\t/* Set the time counters to a new value. */\n+\tdev->systime_tc.nsec = ns;\n+\tdev->rx_tstamp_tc.nsec = ns;\n+\tdev->tx_tstamp_tc.nsec = ns;\n+\n+\treturn 0;\n+}\n+\n+int\n+cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct roc_nix *nix = &dev->nix;\n+\tint rc;\n+\n+\t/* Adjust the frequent to make tics increments in 10^9 tics per sec */\n+\tif (delta < ROC_NIX_PTP_FREQ_ADJUST &&\n+\t delta > -ROC_NIX_PTP_FREQ_ADJUST) {\n+\t\trc = roc_nix_ptp_sync_time_adjust(nix, delta);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\t/* Since the frequency of PTP comp register is tuned, delta and\n+\t\t * freq mult calculation for deriving PTP_HI from timestamp\n+\t\t * counter should be done again.\n+\t\t */\n+\t\trc = cnxk_nix_tsc_convert(dev);\n+\t\tif (rc)\n+\t\t\tplt_err(\"Failed to calculate delta and freq mult\");\n+\t}\n+\n+\tdev->systime_tc.nsec += delta;\n+\tdev->rx_tstamp_tc.nsec += delta;\n+\tdev->tx_tstamp_tc.nsec += delta;\n+\n+\treturn 0;\n+}\n+\n+int\n cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,\n \t\t\t\t struct timespec *timestamp, uint32_t flags)\n {\n", "prefixes": [ "v4", "58/62" ] }