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GET /api/patches/94724/?format=api
{ "id": 94724, "url": "https://patches.dpdk.org/api/patches/94724/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-29-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-29-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-29-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:28", "name": "[v4,28/62] net/cnxk: add Tx burst for cn10k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c2e20ce22d3e052d5728c39d6edea8fb2b7cdd5f", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-29-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94724/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94724/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B0F47A0C41;\n\tWed, 23 Jun 2021 06:50:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ECC5F41144;\n\tWed, 23 Jun 2021 06:48:54 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 1FC6041122\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:53 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k9ol025587 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:52 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gpa-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:52 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:50 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:50 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 2AF645B6939;\n Tue, 22 Jun 2021 21:48:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=N0tJEMOo1a5/npzKuNWx6gkb7qslXiJeNWbZvY5E9n4=;\n b=WmB981nWZAPnKJR/zLrTXFeyn/veZ9xwUbKHL102FqRgSeNTZSNHETRt9zj/yWvG56xk\n AdrNBvMdve7wMUu18ahiiFAQcY48Hw1cqqboj3Mvmv3uAoh5F1ASPEexYkBM2CMBDBI9\n itVbxMFxQvF17D6/Iz4wZQTufLB1ovz0LV7aOEKTsnqn/xWo6jifrTBmxbgbPH/yHF5V\n 2y32+VYSJwaUZnTeSQnCLlvtdk9ON1a/QwEJYoDYMD0CvvYiskKpXmXoUp1yQOpvRDF2\n QuI+zhIwxgSAQ31Qb6nNCHoqJJC58yhMZcImcj9VZsxgLqbgosDgMpZhDKq/Q4zQDcmB aQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:28 +0530", "Message-ID": "<20210623044702.4240-29-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "8CZaFC2BXNKHv1ZYIOjzdY02kWW0iMjC", "X-Proofpoint-GUID": "8CZaFC2BXNKHv1ZYIOjzdY02kWW0iMjC", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 28/62] net/cnxk: add Tx burst for cn10k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Tx burst scalar version for CN10K.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 1 +\n doc/guides/nics/features/cnxk.ini | 7 +\n doc/guides/nics/features/cnxk_vec.ini | 6 +\n doc/guides/nics/features/cnxk_vf.ini | 7 +\n drivers/net/cnxk/cn10k_ethdev.h | 1 +\n drivers/net/cnxk/cn10k_tx.c | 54 ++++\n drivers/net/cnxk/cn10k_tx.h | 491 ++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/meson.build | 7 +-\n 8 files changed, 571 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/cnxk/cn10k_tx.c", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 481bc7e..17da141 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -22,6 +22,7 @@ Features of the CNXK Ethdev PMD are:\n - Lock-free Tx queue\n - Multiple queues for TX and RX\n - Receiver Side Scaling (RSS)\n+- Inner and Outer Checksum offload\n - Link state information\n - Scatter-Gather IO support\n - Vector Poll mode driver\ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex 23564b7..02be26b 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -12,11 +12,18 @@ Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n+Fast mbuf free = Y\n+Free Tx mbuf on demand = Y\n Queue start/stop = Y\n+TSO = Y\n RSS hash = Y\n Inner RSS = Y\n Jumbo frame = Y\n Scattered Rx = Y\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n+Inner L3 checksum = Y\n+Inner L4 checksum = Y\n Packet type parsing = Y\n Linux = Y\n ARMv8 = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex 421048d..8c63853 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -12,10 +12,16 @@ Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n+Fast mbuf free = Y\n+Free Tx mbuf on demand = Y\n Queue start/stop = Y\n RSS hash = Y\n Inner RSS = Y\n Jumbo frame = Y\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n+Inner L3 checksum = Y\n+Inner L4 checksum = Y\n Packet type parsing = Y\n Linux = Y\n ARMv8 = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex e901fa2..a1bd49b 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -11,11 +11,18 @@ Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n+Fast mbuf free = Y\n+Free Tx mbuf on demand = Y\n Queue start/stop = Y\n+TSO = Y\n RSS hash = Y\n Inner RSS = Y\n Jumbo frame = Y\n Scattered Rx = Y\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n+Inner L3 checksum = Y\n+Inner L4 checksum = Y\n Packet type parsing = Y\n Linux = Y\n ARMv8 = Y\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex 596985f..d39ca31 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -35,5 +35,6 @@ struct cn10k_eth_rxq {\n \n /* Rx and Tx routines */\n void cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev);\n+void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev);\n \n #endif /* __CN10K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cn10k_tx.c b/drivers/net/cnxk/cn10k_tx.c\nnew file mode 100644\nindex 0000000..13c605f\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_tx.c\n@@ -0,0 +1,54 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_ethdev.h\"\n+#include \"cn10k_tx.h\"\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_##name(\t \\\n+\t\tvoid *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts) \\\n+\t{ \\\n+\t\tuint64_t cmd[sz]; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\t/* For TSO inner checksum is a must */ \\\n+\t\tif (((flags) & NIX_TX_OFFLOAD_TSO_F) &&\t\t\t \\\n+\t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t \\\n+\t\t\treturn 0; \\\n+\t\treturn cn10k_nix_xmit_pkts(tx_queue, tx_pkts, pkts, cmd, \\\n+\t\t\t\t\t flags);\t\t\t \\\n+\t}\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\n+static inline void\n+pick_tx_func(struct rte_eth_dev *eth_dev,\n+\t const eth_tx_burst_t tx_burst[2][2][2][2][2])\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n+\t/* [TSO] [NOFF] [VLAN] [OL3_OL4_CSUM] [IL3_IL4_CSUM] */\n+\teth_dev->tx_pkt_burst = tx_burst\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n+}\n+\n+void\n+cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n+{\n+\tconst eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags) \\\n+\t[f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_##name,\n+\n+\t\tNIX_TX_FASTPATH_MODES\n+#undef T\n+\t};\n+\n+\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n+\n+\trte_mb();\n+}\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex 39d4755..c54fbfe 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -4,10 +4,501 @@\n #ifndef __CN10K_TX_H__\n #define __CN10K_TX_H__\n \n+#define NIX_TX_OFFLOAD_NONE\t (0)\n+#define NIX_TX_OFFLOAD_L3_L4_CSUM_F BIT(0)\n+#define NIX_TX_OFFLOAD_OL3_OL4_CSUM_F BIT(1)\n #define NIX_TX_OFFLOAD_VLAN_QINQ_F BIT(2)\n+#define NIX_TX_OFFLOAD_MBUF_NOFF_F BIT(3)\n #define NIX_TX_OFFLOAD_TSO_F\t BIT(4)\n \n+/* Flags to control xmit_prepare function.\n+ * Defining it from backwards to denote its been\n+ * not used as offload flags to pick function\n+ */\n+#define NIX_TX_MULTI_SEG_F BIT(15)\n+\n+#define NIX_TX_NEED_SEND_HDR_W1 \\\n+\t(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F | \\\n+\t NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)\n+\n #define NIX_TX_NEED_EXT_HDR \\\n \t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)\n \n+#define NIX_XMIT_FC_OR_RETURN(txq, pkts) \\\n+\tdo { \\\n+\t\t/* Cached value is low, Update the fc_cache_pkts */ \\\n+\t\tif (unlikely((txq)->fc_cache_pkts < (pkts))) { \\\n+\t\t\t/* Multiply with sqe_per_sqb to express in pkts */ \\\n+\t\t\t(txq)->fc_cache_pkts = \\\n+\t\t\t\t((txq)->nb_sqb_bufs_adj - *(txq)->fc_mem) \\\n+\t\t\t\t<< (txq)->sqes_per_sqb_log2; \\\n+\t\t\t/* Check it again for the room */ \\\n+\t\t\tif (unlikely((txq)->fc_cache_pkts < (pkts))) \\\n+\t\t\t\treturn 0; \\\n+\t\t} \\\n+\t} while (0)\n+\n+/* Function to determine no of tx subdesc required in case ext\n+ * sub desc is enabled.\n+ */\n+static __rte_always_inline int\n+cn10k_nix_tx_ext_subs(const uint16_t flags)\n+{\n+\treturn (flags &\n+\t\t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)) ? 1 : 0;\n+}\n+\n+static __rte_always_inline uint64_t\n+cn10k_nix_tx_steor_data(const uint16_t flags)\n+{\n+\tconst uint64_t dw_m1 = cn10k_nix_tx_ext_subs(flags) + 1;\n+\tuint64_t data;\n+\n+\t/* This will be moved to addr area */\n+\tdata = dw_m1;\n+\t/* 15 vector sizes for single seg */\n+\tdata |= dw_m1 << 19;\n+\tdata |= dw_m1 << 22;\n+\tdata |= dw_m1 << 25;\n+\tdata |= dw_m1 << 28;\n+\tdata |= dw_m1 << 31;\n+\tdata |= dw_m1 << 34;\n+\tdata |= dw_m1 << 37;\n+\tdata |= dw_m1 << 40;\n+\tdata |= dw_m1 << 43;\n+\tdata |= dw_m1 << 46;\n+\tdata |= dw_m1 << 49;\n+\tdata |= dw_m1 << 52;\n+\tdata |= dw_m1 << 55;\n+\tdata |= dw_m1 << 58;\n+\tdata |= dw_m1 << 61;\n+\n+\treturn data;\n+}\n+\n+static __rte_always_inline void\n+cn10k_nix_tx_skeleton(const struct cn10k_eth_txq *txq, uint64_t *cmd,\n+\t\t const uint16_t flags)\n+{\n+\t/* Send hdr */\n+\tcmd[0] = txq->send_hdr_w0;\n+\tcmd[1] = 0;\n+\tcmd += 2;\n+\n+\t/* Send ext if present */\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t*(__uint128_t *)cmd = *(const __uint128_t *)txq->cmd;\n+\t\tcmd += 2;\n+\t}\n+\n+\t/* Send sg */\n+\tcmd[0] = txq->sg_w0;\n+\tcmd[1] = 0;\n+}\n+\n+static __rte_always_inline void\n+cn10k_nix_xmit_prepare_tso(struct rte_mbuf *m, const uint64_t flags)\n+{\n+\tuint64_t mask, ol_flags = m->ol_flags;\n+\n+\tif (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & PKT_TX_TCP_SEG)) {\n+\t\tuintptr_t mdata = rte_pktmbuf_mtod(m, uintptr_t);\n+\t\tuint16_t *iplen, *oiplen, *oudplen;\n+\t\tuint16_t lso_sb, paylen;\n+\n+\t\tmask = -!!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6));\n+\t\tlso_sb = (mask & (m->outer_l2_len + m->outer_l3_len)) +\n+\t\t\t m->l2_len + m->l3_len + m->l4_len;\n+\n+\t\t/* Reduce payload len from base headers */\n+\t\tpaylen = m->pkt_len - lso_sb;\n+\n+\t\t/* Get iplen position assuming no tunnel hdr */\n+\t\tiplen = (uint16_t *)(mdata + m->l2_len +\n+\t\t\t\t (2 << !!(ol_flags & PKT_TX_IPV6)));\n+\t\t/* Handle tunnel tso */\n+\t\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n+\t\t (ol_flags & PKT_TX_TUNNEL_MASK)) {\n+\t\t\tconst uint8_t is_udp_tun =\n+\t\t\t\t(CNXK_NIX_UDP_TUN_BITMASK >>\n+\t\t\t\t ((ol_flags & PKT_TX_TUNNEL_MASK) >> 45)) &\n+\t\t\t\t0x1;\n+\n+\t\t\toiplen = (uint16_t *)(mdata + m->outer_l2_len +\n+\t\t\t\t\t (2 << !!(ol_flags &\n+\t\t\t\t\t\t PKT_TX_OUTER_IPV6)));\n+\t\t\t*oiplen = rte_cpu_to_be_16(rte_be_to_cpu_16(*oiplen) -\n+\t\t\t\t\t\t paylen);\n+\n+\t\t\t/* Update format for UDP tunneled packet */\n+\t\t\tif (is_udp_tun) {\n+\t\t\t\toudplen = (uint16_t *)(mdata + m->outer_l2_len +\n+\t\t\t\t\t\t m->outer_l3_len + 4);\n+\t\t\t\t*oudplen = rte_cpu_to_be_16(\n+\t\t\t\t\trte_be_to_cpu_16(*oudplen) - paylen);\n+\t\t\t}\n+\n+\t\t\t/* Update iplen position to inner ip hdr */\n+\t\t\tiplen = (uint16_t *)(mdata + lso_sb - m->l3_len -\n+\t\t\t\t\t m->l4_len +\n+\t\t\t\t\t (2 << !!(ol_flags & PKT_TX_IPV6)));\n+\t\t}\n+\n+\t\t*iplen = rte_cpu_to_be_16(rte_be_to_cpu_16(*iplen) - paylen);\n+\t}\n+}\n+\n+static __rte_always_inline void\n+cn10k_nix_xmit_prepare(struct rte_mbuf *m, uint64_t *cmd, uintptr_t lmt_addr,\n+\t\t const uint16_t flags, const uint64_t lso_tun_fmt)\n+{\n+\tstruct nix_send_ext_s *send_hdr_ext;\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tuint64_t ol_flags = 0, mask;\n+\tunion nix_send_hdr_w1_u w1;\n+\tunion nix_send_sg_s *sg;\n+\n+\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tsend_hdr_ext = (struct nix_send_ext_s *)(cmd + 2);\n+\t\tsg = (union nix_send_sg_s *)(cmd + 4);\n+\t\t/* Clear previous markings */\n+\t\tsend_hdr_ext->w0.lso = 0;\n+\t\tsend_hdr_ext->w1.u = 0;\n+\t} else {\n+\t\tsg = (union nix_send_sg_s *)(cmd + 2);\n+\t}\n+\n+\tif (flags & NIX_TX_NEED_SEND_HDR_W1) {\n+\t\tol_flags = m->ol_flags;\n+\t\tw1.u = 0;\n+\t}\n+\n+\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n+\t\tsend_hdr->w0.total = m->data_len;\n+\t\tsend_hdr->w0.aura =\n+\t\t\troc_npa_aura_handle_to_aura(m->pool->pool_id);\n+\t}\n+\n+\t/*\n+\t * L3type: 2 => IPV4\n+\t * 3 => IPV4 with csum\n+\t * 4 => IPV6\n+\t * L3type and L3ptr needs to be set for either\n+\t * L3 csum or L4 csum or LSO\n+\t *\n+\t */\n+\n+\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n+\t (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n+\t\tconst uint8_t csum = !!(ol_flags & PKT_TX_OUTER_UDP_CKSUM);\n+\t\tconst uint8_t ol3type =\n+\t\t\t((!!(ol_flags & PKT_TX_OUTER_IPV4)) << 1) +\n+\t\t\t((!!(ol_flags & PKT_TX_OUTER_IPV6)) << 2) +\n+\t\t\t!!(ol_flags & PKT_TX_OUTER_IP_CKSUM);\n+\n+\t\t/* Outer L3 */\n+\t\tw1.ol3type = ol3type;\n+\t\tmask = 0xffffull << ((!!ol3type) << 4);\n+\t\tw1.ol3ptr = ~mask & m->outer_l2_len;\n+\t\tw1.ol4ptr = ~mask & (w1.ol3ptr + m->outer_l3_len);\n+\n+\t\t/* Outer L4 */\n+\t\tw1.ol4type = csum + (csum << 1);\n+\n+\t\t/* Inner L3 */\n+\t\tw1.il3type = ((!!(ol_flags & PKT_TX_IPV4)) << 1) +\n+\t\t\t ((!!(ol_flags & PKT_TX_IPV6)) << 2);\n+\t\tw1.il3ptr = w1.ol4ptr + m->l2_len;\n+\t\tw1.il4ptr = w1.il3ptr + m->l3_len;\n+\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n+\t\tw1.il3type = w1.il3type + !!(ol_flags & PKT_TX_IP_CKSUM);\n+\n+\t\t/* Inner L4 */\n+\t\tw1.il4type = (ol_flags & PKT_TX_L4_MASK) >> 52;\n+\n+\t\t/* In case of no tunnel header use only\n+\t\t * shift IL3/IL4 fields a bit to use\n+\t\t * OL3/OL4 for header checksum\n+\t\t */\n+\t\tmask = !ol3type;\n+\t\tw1.u = ((w1.u & 0xFFFFFFFF00000000) >> (mask << 3)) |\n+\t\t ((w1.u & 0X00000000FFFFFFFF) >> (mask << 4));\n+\n+\t} else if (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) {\n+\t\tconst uint8_t csum = !!(ol_flags & PKT_TX_OUTER_UDP_CKSUM);\n+\t\tconst uint8_t outer_l2_len = m->outer_l2_len;\n+\n+\t\t/* Outer L3 */\n+\t\tw1.ol3ptr = outer_l2_len;\n+\t\tw1.ol4ptr = outer_l2_len + m->outer_l3_len;\n+\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n+\t\tw1.ol3type = ((!!(ol_flags & PKT_TX_OUTER_IPV4)) << 1) +\n+\t\t\t ((!!(ol_flags & PKT_TX_OUTER_IPV6)) << 2) +\n+\t\t\t !!(ol_flags & PKT_TX_OUTER_IP_CKSUM);\n+\n+\t\t/* Outer L4 */\n+\t\tw1.ol4type = csum + (csum << 1);\n+\n+\t} else if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) {\n+\t\tconst uint8_t l2_len = m->l2_len;\n+\n+\t\t/* Always use OLXPTR and OLXTYPE when only\n+\t\t * when one header is present\n+\t\t */\n+\n+\t\t/* Inner L3 */\n+\t\tw1.ol3ptr = l2_len;\n+\t\tw1.ol4ptr = l2_len + m->l3_len;\n+\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n+\t\tw1.ol3type = ((!!(ol_flags & PKT_TX_IPV4)) << 1) +\n+\t\t\t ((!!(ol_flags & PKT_TX_IPV6)) << 2) +\n+\t\t\t !!(ol_flags & PKT_TX_IP_CKSUM);\n+\n+\t\t/* Inner L4 */\n+\t\tw1.ol4type = (ol_flags & PKT_TX_L4_MASK) >> 52;\n+\t}\n+\n+\tif (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) {\n+\t\tsend_hdr_ext->w1.vlan1_ins_ena = !!(ol_flags & PKT_TX_VLAN);\n+\t\t/* HW will update ptr after vlan0 update */\n+\t\tsend_hdr_ext->w1.vlan1_ins_ptr = 12;\n+\t\tsend_hdr_ext->w1.vlan1_ins_tci = m->vlan_tci;\n+\n+\t\tsend_hdr_ext->w1.vlan0_ins_ena = !!(ol_flags & PKT_TX_QINQ);\n+\t\t/* 2B before end of l2 header */\n+\t\tsend_hdr_ext->w1.vlan0_ins_ptr = 12;\n+\t\tsend_hdr_ext->w1.vlan0_ins_tci = m->vlan_tci_outer;\n+\t}\n+\n+\tif (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & PKT_TX_TCP_SEG)) {\n+\t\tuint16_t lso_sb;\n+\t\tuint64_t mask;\n+\n+\t\tmask = -(!w1.il3type);\n+\t\tlso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;\n+\n+\t\tsend_hdr_ext->w0.lso_sb = lso_sb;\n+\t\tsend_hdr_ext->w0.lso = 1;\n+\t\tsend_hdr_ext->w0.lso_mps = m->tso_segsz;\n+\t\tsend_hdr_ext->w0.lso_format =\n+\t\t\tNIX_LSO_FORMAT_IDX_TSOV4 + !!(ol_flags & PKT_TX_IPV6);\n+\t\tw1.ol4type = NIX_SENDL4TYPE_TCP_CKSUM;\n+\n+\t\t/* Handle tunnel tso */\n+\t\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n+\t\t (ol_flags & PKT_TX_TUNNEL_MASK)) {\n+\t\t\tconst uint8_t is_udp_tun =\n+\t\t\t\t(CNXK_NIX_UDP_TUN_BITMASK >>\n+\t\t\t\t ((ol_flags & PKT_TX_TUNNEL_MASK) >> 45)) &\n+\t\t\t\t0x1;\n+\t\t\tuint8_t shift = is_udp_tun ? 32 : 0;\n+\n+\t\t\tshift += (!!(ol_flags & PKT_TX_OUTER_IPV6) << 4);\n+\t\t\tshift += (!!(ol_flags & PKT_TX_IPV6) << 3);\n+\n+\t\t\tw1.il4type = NIX_SENDL4TYPE_TCP_CKSUM;\n+\t\t\tw1.ol4type = is_udp_tun ? NIX_SENDL4TYPE_UDP_CKSUM : 0;\n+\t\t\t/* Update format for UDP tunneled packet */\n+\t\t\tsend_hdr_ext->w0.lso_format = (lso_tun_fmt >> shift);\n+\t\t}\n+\t}\n+\n+\tif (flags & NIX_TX_NEED_SEND_HDR_W1)\n+\t\tsend_hdr->w1.u = w1.u;\n+\n+\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n+\t\tsg->seg1_size = m->data_len;\n+\t\t*(rte_iova_t *)(sg + 1) = rte_mbuf_data_iova(m);\n+\n+\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n+\t\t\t/* DF bit = 1 if refcount of current mbuf or parent mbuf\n+\t\t\t *\t\tis greater than 1\n+\t\t\t * DF bit = 0 otherwise\n+\t\t\t */\n+\t\t\tsend_hdr->w0.df = cnxk_nix_prefree_seg(m);\n+\t\t}\n+\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n+\t\tif (!send_hdr->w0.df)\n+\t\t\t__mempool_check_cookies(m->pool, (void **)&m, 1, 0);\n+\t}\n+\n+\t/* With minimal offloads, 'cmd' being local could be optimized out to\n+\t * registers. In other cases, 'cmd' will be in stack. Intent is\n+\t * 'cmd' stores content from txq->cmd which is copied only once.\n+\t */\n+\t*((struct nix_send_hdr_s *)lmt_addr) = *send_hdr;\n+\tlmt_addr += 16;\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\t*((struct nix_send_ext_s *)lmt_addr) = *send_hdr_ext;\n+\t\tlmt_addr += 16;\n+\t}\n+\t/* In case of multi-seg, sg template is stored here */\n+\t*((union nix_send_sg_s *)lmt_addr) = *sg;\n+\t*(rte_iova_t *)(lmt_addr + 8) = *(rte_iova_t *)(sg + 1);\n+}\n+\n+static __rte_always_inline uint16_t\n+cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n+\t\t uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct cn10k_eth_txq *txq = tx_queue;\n+\tconst rte_iova_t io_addr = txq->io_addr;\n+\tuintptr_t pa, lmt_addr = txq->lmt_base;\n+\tuint16_t lmt_id, burst, left, i;\n+\tuint64_t lso_tun_fmt;\n+\tuint64_t data;\n+\n+\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\n+\t/* Get cmd skeleton */\n+\tcn10k_nix_tx_skeleton(txq, cmd, flags);\n+\n+\t/* Reduce the cached count */\n+\ttxq->fc_cache_pkts -= pkts;\n+\n+\tif (flags & NIX_TX_OFFLOAD_TSO_F)\n+\t\tlso_tun_fmt = txq->lso_tun_fmt;\n+\n+\t/* Get LMT base address and LMT ID as lcore id */\n+\tROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);\n+\tleft = pkts;\n+again:\n+\tburst = left > 32 ? 32 : left;\n+\tfor (i = 0; i < burst; i++) {\n+\t\t/* Perform header writes for TSO, barrier at\n+\t\t * lmt steorl will suffice.\n+\t\t */\n+\t\tif (flags & NIX_TX_OFFLOAD_TSO_F)\n+\t\t\tcn10k_nix_xmit_prepare_tso(tx_pkts[i], flags);\n+\n+\t\tcn10k_nix_xmit_prepare(tx_pkts[i], cmd, lmt_addr, flags,\n+\t\t\t\t lso_tun_fmt);\n+\t\tlmt_addr += (1ULL << ROC_LMT_LINE_SIZE_LOG2);\n+\t}\n+\n+\t/* Trigger LMTST */\n+\tif (burst > 16) {\n+\t\tdata = cn10k_nix_tx_steor_data(flags);\n+\t\tpa = io_addr | (data & 0x7) << 4;\n+\t\tdata &= ~0x7ULL;\n+\t\tdata |= (15ULL << 12);\n+\t\tdata |= (uint64_t)lmt_id;\n+\n+\t\t/* STEOR0 */\n+\t\troc_lmt_submit_steorl(data, pa);\n+\n+\t\tdata = cn10k_nix_tx_steor_data(flags);\n+\t\tpa = io_addr | (data & 0x7) << 4;\n+\t\tdata &= ~0x7ULL;\n+\t\tdata |= ((uint64_t)(burst - 17)) << 12;\n+\t\tdata |= (uint64_t)(lmt_id + 16);\n+\n+\t\t/* STEOR1 */\n+\t\troc_lmt_submit_steorl(data, pa);\n+\t} else if (burst) {\n+\t\tdata = cn10k_nix_tx_steor_data(flags);\n+\t\tpa = io_addr | (data & 0x7) << 4;\n+\t\tdata &= ~0x7ULL;\n+\t\tdata |= ((uint64_t)(burst - 1)) << 12;\n+\t\tdata |= lmt_id;\n+\n+\t\t/* STEOR0 */\n+\t\troc_lmt_submit_steorl(data, pa);\n+\t}\n+\n+\tleft -= burst;\n+\trte_io_wmb();\n+\tif (left) {\n+\t\t/* Start processing another burst */\n+\t\ttx_pkts += burst;\n+\t\t/* Reset lmt base addr */\n+\t\tlmt_addr -= (1ULL << ROC_LMT_LINE_SIZE_LOG2);\n+\t\tlmt_addr &= (~(BIT_ULL(ROC_LMT_BASE_PER_CORE_LOG2) - 1));\n+\t\tgoto again;\n+\t}\n+\n+\treturn pkts;\n+}\n+\n+#define L3L4CSUM_F NIX_TX_OFFLOAD_L3_L4_CSUM_F\n+#define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\n+#define VLAN_F\t NIX_TX_OFFLOAD_VLAN_QINQ_F\n+#define NOFF_F\t NIX_TX_OFFLOAD_MBUF_NOFF_F\n+#define TSO_F\t NIX_TX_OFFLOAD_TSO_F\n+\n+/* [TSO] [NOFF] [VLAN] [OL3OL4CSUM] [L3L4CSUM] */\n+#define NIX_TX_FASTPATH_MODES\t\t\t\t\t\t\\\n+T(no_offload,\t\t\t\t0, 0, 0, 0, 0,\t4,\t\t\\\n+\t\tNIX_TX_OFFLOAD_NONE)\t\t\t\t\t\\\n+T(l3l4csum,\t\t\t\t0, 0, 0, 0, 1,\t4,\t\t\\\n+\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n+T(ol3ol4csum,\t\t\t\t0, 0, 0, 1, 0,\t4,\t\t\\\n+\t\tOL3OL4CSUM_F)\t\t\t\t\t\t\\\n+T(ol3ol4csum_l3l4csum,\t\t\t0, 0, 0, 1, 1,\t4,\t\t\\\n+\t\tOL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\t\\\n+T(vlan,\t\t\t\t\t0, 0, 1, 0, 0,\t6,\t\t\\\n+\t\tVLAN_F)\t\t\t\t\t\t\t\\\n+T(vlan_l3l4csum,\t\t\t0, 0, 1, 0, 1,\t6,\t\t\\\n+\t\tVLAN_F | L3L4CSUM_F)\t\t\t\t\t\\\n+T(vlan_ol3ol4csum,\t\t\t0, 0, 1, 1, 0,\t6,\t\t\\\n+\t\tVLAN_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n+T(vlan_ol3ol4csum_l3l4csum,\t\t0, 0, 1, 1, 1,\t6,\t\t\\\n+\t\tVLAN_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\t\\\n+T(noff,\t\t\t\t\t0, 1, 0, 0, 0,\t4,\t\t\\\n+\t\tNOFF_F)\t\t\t\t\t\t\t\\\n+T(noff_l3l4csum,\t\t\t0, 1, 0, 0, 1,\t4,\t\t\\\n+\t\tNOFF_F | L3L4CSUM_F)\t\t\t\t\t\\\n+T(noff_ol3ol4csum,\t\t\t0, 1, 0, 1, 0,\t4,\t\t\\\n+\t\tNOFF_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n+T(noff_ol3ol4csum_l3l4csum,\t\t0, 1, 0, 1, 1,\t4,\t\t\\\n+\t\tNOFF_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\t\\\n+T(noff_vlan,\t\t\t\t0, 1, 1, 0, 0,\t6,\t\t\\\n+\t\tNOFF_F | VLAN_F)\t\t\t\t\t\\\n+T(noff_vlan_l3l4csum,\t\t\t0, 1, 1, 0, 1,\t6,\t\t\\\n+\t\tNOFF_F | VLAN_F | L3L4CSUM_F)\t\t\t\t\\\n+T(noff_vlan_ol3ol4csum,\t\t\t0, 1, 1, 1, 0,\t6,\t\t\\\n+\t\tNOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\t\\\n+T(noff_vlan_ol3ol4csum_l3l4csum,\t0, 1, 1, 1, 1,\t6,\t\t\\\n+\t\tNOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n+T(tso,\t\t\t\t\t1, 0, 0, 0, 0,\t6,\t\t\\\n+\t\tTSO_F)\t\t\t\t\t\t\t\\\n+T(tso_l3l4csum,\t\t\t\t1, 0, 0, 0, 1,\t6,\t\t\\\n+\t\tTSO_F | L3L4CSUM_F)\t\t\t\t\t\\\n+T(tso_ol3ol4csum,\t\t\t1, 0, 0, 1, 0,\t6,\t\t\\\n+\t\tTSO_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n+T(tso_ol3ol4csum_l3l4csum,\t\t1, 0, 0, 1, 1,\t6,\t\t\\\n+\t\tTSO_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\\\n+T(tso_vlan,\t\t\t\t1, 0, 1, 0, 0,\t6,\t\t\\\n+\t\tTSO_F | VLAN_F)\t\t\t\t\t\t\\\n+T(tso_vlan_l3l4csum,\t\t\t1, 0, 1, 0, 1,\t6,\t\t\\\n+\t\tTSO_F | VLAN_F | L3L4CSUM_F)\t\t\t\t\\\n+T(tso_vlan_ol3ol4csum,\t\t\t1, 0, 1, 1, 0,\t6,\t\t\\\n+\t\tTSO_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\t\\\n+T(tso_vlan_ol3ol4csum_l3l4csum,\t\t1, 0, 1, 1, 1,\t6,\t\t\\\n+\t\tTSO_F | VLAN_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\\\n+T(tso_noff,\t\t\t\t1, 1, 0, 0, 0,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F)\t\t\t\t\t\t\\\n+T(tso_noff_l3l4csum,\t\t\t1, 1, 0, 0, 1,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | L3L4CSUM_F)\t\t\t\t\\\n+T(tso_noff_ol3ol4csum,\t\t\t1, 1, 0, 1, 0,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | OL3OL4CSUM_F)\t\t\t\t\\\n+T(tso_noff_ol3ol4csum_l3l4csum,\t\t1, 1, 0, 1, 1,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\\\n+T(tso_noff_vlan,\t\t\t1, 1, 1, 0, 0,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | VLAN_F)\t\t\t\t\\\n+T(tso_noff_vlan_l3l4csum,\t\t1, 1, 1, 0, 1,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n+T(tso_noff_vlan_ol3ol4csum,\t\t1, 1, 1, 1, 0,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n+T(tso_noff_vlan_ol3ol4csum_l3l4csum,\t1, 1, 1, 1, 1,\t6,\t\t\\\n+\t\tTSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags) \\\n+\tuint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_##name( \\\n+\t\tvoid *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts);\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\n #endif /* __CN10K_TX_H__ */\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 6748e9c..b1ba824 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -26,13 +26,14 @@ sources += files('cn9k_ethdev.c',\n sources += files('cn10k_ethdev.c',\n \t\t 'cn10k_rx.c',\n \t\t 'cn10k_rx_mseg.c',\n-\t\t 'cn10k_rx_vec.c')\n+\t\t 'cn10k_rx_vec.c',\n+\t\t 'cn10k_tx.c')\n \n deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']\n deps += ['common_cnxk', 'mempool_cnxk']\n \n-# Allow implicit vector conversions\n-extra_flags = ['-flax-vector-conversions']\n+# Allow implicit vector conversions and strict aliasing warning\n+extra_flags = ['-flax-vector-conversions', '-Wno-strict-aliasing']\n foreach flag: extra_flags\n \tif cc.has_argument(flag)\n \t\tcflags += flag\n", "prefixes": [ "v4", "28/62" ] }