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GET /api/patches/94723/?format=api
{ "id": 94723, "url": "https://patches.dpdk.org/api/patches/94723/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-28-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-28-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-28-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:27", "name": "[v4,27/62] net/cnxk: add Rx vector version for cn10k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2199e404c943f787711ffb1b5f85b0ac62d27d40", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-28-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94723/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94723/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 308CBA0C41;\n\tWed, 23 Jun 2021 06:50:31 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B57DB410E6;\n\tWed, 23 Jun 2021 06:48:50 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6F09C410E6\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:49 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k7XU025541 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:48 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gp1-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:48 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:46 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:46 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id C36215B6938;\n Tue, 22 Jun 2021 21:48:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=5rHI0DhVFxW94Wo0ScYBugTNWVd+kIwklYZ29E8C5OE=;\n b=G4RY0s28Uj19h8LM5/zZk9w6zAUxaz8aSwl3Ii8l2oRO572fPtGhZZDhADGMt8yOD5n5\n ISfrDb9kLzU7fCNS2zM1hCKhe1ScigzMl3iBwwSiuuRoPrvIZ467A1iJ7fA6pdGsYwmt\n 4Hz1q0768dylQBYvXZAkcV7Ca4rtpQbWF59Lqcpo9t4qGtYmJDjyfxy1FfqHayaTKDam\n xHIEAABBo/D3IdPPyYDDGOsr1WeXbgg7aukk+DULFnXLWXw4LaPdV1M/kaKc4iO7Lsgb\n juijl+VJeYECxg+4Qdfatonxe0qEfEH0ZUY65Znu9BwmeLy9r5SnSWm92RMs5G6vm62W 6Q==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:27 +0530", "Message-ID": "<20210623044702.4240-28-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "-kR5Z54dYdOBDbVjXHrkc6tT3zj7i6xp", "X-Proofpoint-GUID": "-kR5Z54dYdOBDbVjXHrkc6tT3zj7i6xp", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 27/62] net/cnxk: add Rx vector version for\n cn10k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Rx burst vector version for CN10K.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 1 +\n drivers/net/cnxk/cn10k_rx.c | 13 ++-\n drivers/net/cnxk/cn10k_rx.h | 222 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cn10k_rx_vec.c | 19 ++++\n drivers/net/cnxk/meson.build | 3 +-\n 5 files changed, 256 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/cnxk/cn10k_rx_vec.c", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex fd7f2dd..481bc7e 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -24,6 +24,7 @@ Features of the CNXK Ethdev PMD are:\n - Receiver Side Scaling (RSS)\n - Link state information\n - Scatter-Gather IO support\n+- Vector Poll mode driver\n \n Prerequisites\n -------------\ndiff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c\nindex ce2cfee..0598111 100644\n--- a/drivers/net/cnxk/cn10k_rx.c\n+++ b/drivers/net/cnxk/cn10k_rx.c\n@@ -50,7 +50,18 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n #undef R\n \t};\n \n-\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n+\t[f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name,\n+\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tif (dev->scalar_ena)\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\telse\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n \n \tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex c667c9a..7bb9dd8 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -5,6 +5,7 @@\n #define __CN10K_RX_H__\n \n #include <rte_ether.h>\n+#include <rte_vect.h>\n \n #define NIX_RX_OFFLOAD_NONE\t (0)\n #define NIX_RX_OFFLOAD_RSS_F\t BIT(0)\n@@ -263,6 +264,224 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \treturn nb_pkts;\n }\n \n+#if defined(RTE_ARCH_ARM64)\n+\n+static __rte_always_inline uint16_t\n+cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t pkts, const uint16_t flags)\n+{\n+\tstruct cn10k_eth_rxq *rxq = rx_queue;\n+\tuint16_t packets = 0;\n+\tuint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;\n+\tconst uint64_t mbuf_initializer = rxq->mbuf_initializer;\n+\tconst uint64x2_t data_off = vdupq_n_u64(rxq->data_off);\n+\tuint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;\n+\tuint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n+\tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n+\tconst uint16_t *lookup_mem = rxq->lookup_mem;\n+\tconst uint32_t qmask = rxq->qmask;\n+\tconst uint64_t wdata = rxq->wdata;\n+\tconst uintptr_t desc = rxq->desc;\n+\tuint8x16_t f0, f1, f2, f3;\n+\tuint32_t head = rxq->head;\n+\tuint16_t pkts_left;\n+\n+\tpkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\tpkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);\n+\n+\t/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */\n+\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\n+\twhile (packets < pkts) {\n+\t\t/* Exit loop if head is about to wrap and become unaligned */\n+\t\tif (((head + NIX_DESCS_PER_LOOP - 1) & qmask) <\n+\t\t NIX_DESCS_PER_LOOP) {\n+\t\t\tpkts_left += (pkts - packets);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tconst uintptr_t cq0 = desc + CQE_SZ(head);\n+\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));\n+\n+\t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n+\t\tcq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));\n+\t\tcq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));\n+\t\tcq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));\n+\t\tcq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));\n+\n+\t\t/* Extract mbuf from NIX_RX_SG_S */\n+\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n+\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n+\t\tmbuf01 = vqsubq_u64(mbuf01, data_off);\n+\t\tmbuf23 = vqsubq_u64(mbuf23, data_off);\n+\n+\t\t/* Move mbufs to scalar registers for future use */\n+\t\tmbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);\n+\t\tmbuf1 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 1);\n+\t\tmbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);\n+\t\tmbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);\n+\n+\t\t/* Mask to get packet len from NIX_RX_SG_S */\n+\t\tconst uint8x16_t shuf_msk = {\n+\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t0, 1, /* octet 1~0, low 16 bits pkt_len */\n+\t\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t0, 1, /* octet 1~0, 16 bits data_len */\n+\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};\n+\n+\t\t/* Form the rx_descriptor_fields1 with pkt_len and data_len */\n+\t\tf0 = vqtbl1q_u8(cq0_w8, shuf_msk);\n+\t\tf1 = vqtbl1q_u8(cq1_w8, shuf_msk);\n+\t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n+\t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n+\n+\t\t/* Load CQE word0 and word 1 */\n+\t\tuint64_t cq0_w0 = ((uint64_t *)(cq0 + CQE_SZ(0)))[0];\n+\t\tuint64_t cq0_w1 = ((uint64_t *)(cq0 + CQE_SZ(0)))[1];\n+\t\tuint64_t cq1_w0 = ((uint64_t *)(cq0 + CQE_SZ(1)))[0];\n+\t\tuint64_t cq1_w1 = ((uint64_t *)(cq0 + CQE_SZ(1)))[1];\n+\t\tuint64_t cq2_w0 = ((uint64_t *)(cq0 + CQE_SZ(2)))[0];\n+\t\tuint64_t cq2_w1 = ((uint64_t *)(cq0 + CQE_SZ(2)))[1];\n+\t\tuint64_t cq3_w0 = ((uint64_t *)(cq0 + CQE_SZ(3)))[0];\n+\t\tuint64_t cq3_w1 = ((uint64_t *)(cq0 + CQE_SZ(3)))[1];\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_RSS_F) {\n+\t\t\t/* Fill rss in the rx_descriptor_fields1 */\n+\t\t\tf0 = vsetq_lane_u32(cq0_w0, f0, 3);\n+\t\t\tf1 = vsetq_lane_u32(cq1_w0, f1, 3);\n+\t\t\tf2 = vsetq_lane_u32(cq2_w0, f2, 3);\n+\t\t\tf3 = vsetq_lane_u32(cq3_w0, f3, 3);\n+\t\t\tol_flags0 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags1 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags2 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags3 = PKT_RX_RSS_HASH;\n+\t\t} else {\n+\t\t\tol_flags0 = 0;\n+\t\t\tol_flags1 = 0;\n+\t\t\tol_flags2 = 0;\n+\t\t\tol_flags3 = 0;\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_PTYPE_F) {\n+\t\t\t/* Fill packet_type in the rx_descriptor_fields1 */\n+\t\t\tf0 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq0_w1),\n+\t\t\t\t\t f0, 0);\n+\t\t\tf1 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq1_w1),\n+\t\t\t\t\t f1, 0);\n+\t\t\tf2 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq2_w1),\n+\t\t\t\t\t f2, 0);\n+\t\t\tf3 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq3_w1),\n+\t\t\t\t\t f3, 0);\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {\n+\t\t\tol_flags0 |= nix_rx_olflags_get(lookup_mem, cq0_w1);\n+\t\t\tol_flags1 |= nix_rx_olflags_get(lookup_mem, cq1_w1);\n+\t\t\tol_flags2 |= nix_rx_olflags_get(lookup_mem, cq2_w1);\n+\t\t\tol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {\n+\t\t\tol_flags0 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(0) + 38), ol_flags0,\n+\t\t\t\tmbuf0);\n+\t\t\tol_flags1 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(1) + 38), ol_flags1,\n+\t\t\t\tmbuf1);\n+\t\t\tol_flags2 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(2) + 38), ol_flags2,\n+\t\t\t\tmbuf2);\n+\t\t\tol_flags3 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(3) + 38), ol_flags3,\n+\t\t\t\tmbuf3);\n+\t\t}\n+\n+\t\t/* Form rearm_data with ol_flags */\n+\t\trearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);\n+\t\trearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);\n+\t\trearm2 = vsetq_lane_u64(ol_flags2, rearm2, 1);\n+\t\trearm3 = vsetq_lane_u64(ol_flags3, rearm3, 1);\n+\n+\t\t/* Update rx_descriptor_fields1 */\n+\t\tvst1q_u64((uint64_t *)mbuf0->rx_descriptor_fields1, f0);\n+\t\tvst1q_u64((uint64_t *)mbuf1->rx_descriptor_fields1, f1);\n+\t\tvst1q_u64((uint64_t *)mbuf2->rx_descriptor_fields1, f2);\n+\t\tvst1q_u64((uint64_t *)mbuf3->rx_descriptor_fields1, f3);\n+\n+\t\t/* Update rearm_data */\n+\t\tvst1q_u64((uint64_t *)mbuf0->rearm_data, rearm0);\n+\t\tvst1q_u64((uint64_t *)mbuf1->rearm_data, rearm1);\n+\t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n+\t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n+\n+\t\t/* Update that no more segments */\n+\t\tmbuf0->next = NULL;\n+\t\tmbuf1->next = NULL;\n+\t\tmbuf2->next = NULL;\n+\t\tmbuf3->next = NULL;\n+\n+\t\t/* Store the mbufs to rx_pkts */\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n+\n+\t\t/* Prefetch mbufs */\n+\t\troc_prefetch_store_keep(mbuf0);\n+\t\troc_prefetch_store_keep(mbuf1);\n+\t\troc_prefetch_store_keep(mbuf2);\n+\t\troc_prefetch_store_keep(mbuf3);\n+\n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\t__mempool_check_cookies(mbuf0->pool, (void **)&mbuf0, 1, 1);\n+\t\t__mempool_check_cookies(mbuf1->pool, (void **)&mbuf1, 1, 1);\n+\t\t__mempool_check_cookies(mbuf2->pool, (void **)&mbuf2, 1, 1);\n+\t\t__mempool_check_cookies(mbuf3->pool, (void **)&mbuf3, 1, 1);\n+\n+\t\t/* Advance head pointer and packets */\n+\t\thead += NIX_DESCS_PER_LOOP;\n+\t\thead &= qmask;\n+\t\tpackets += NIX_DESCS_PER_LOOP;\n+\t}\n+\n+\trxq->head = head;\n+\trxq->available -= packets;\n+\n+\trte_io_wmb();\n+\t/* Free all the CQs that we've processed */\n+\tplt_write64((rxq->wdata | packets), rxq->cq_door);\n+\n+\tif (unlikely(pkts_left))\n+\t\tpackets += cn10k_nix_recv_pkts(rx_queue, &rx_pkts[packets],\n+\t\t\t\t\t pkts_left, flags);\n+\n+\treturn packets;\n+}\n+\n+#else\n+\n+static inline uint16_t\n+cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t pkts, const uint16_t flags)\n+{\n+\tRTE_SET_USED(rx_queue);\n+\tRTE_SET_USED(rx_pkts);\n+\tRTE_SET_USED(pkts);\n+\tRTE_SET_USED(flags);\n+\n+\treturn 0;\n+}\n+\n+#endif\n+\n+\n #define RSS_F\t NIX_RX_OFFLOAD_RSS_F\n #define PTYPE_F\t NIX_RX_OFFLOAD_PTYPE_F\n #define CKSUM_F\t NIX_RX_OFFLOAD_CHECKSUM_F\n@@ -292,6 +511,9 @@ R(mark_cksum_ptype_rss,\t\t1, 1, 1, 1, MARK_F | CKSUM_F | PTYPE_F | RSS_F)\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n \t\t\t\t\t\t\t\t\t \\\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_mseg_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts);\n \n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec.c b/drivers/net/cnxk/cn10k_rx_vec.c\nnew file mode 100644\nindex 0000000..0fa079c\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_rx_vec.c\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_ethdev.h\"\n+#include \"cn10k_rx.h\"\n+\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot\t\t\t\t \\\n+\t\tcn10k_nix_recv_pkts_vec_##name(void *rx_queue, \\\n+\t\t\t\t\t struct rte_mbuf **rx_pkts, \\\n+\t\t\t\t\t uint16_t pkts) \\\n+\t{ \\\n+\t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n+\t\t\t\t\t\t (flags));\t\t \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 20bb00b..6748e9c 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -25,7 +25,8 @@ sources += files('cn9k_ethdev.c',\n # CN10K\n sources += files('cn10k_ethdev.c',\n \t\t 'cn10k_rx.c',\n-\t\t 'cn10k_rx_mseg.c')\n+\t\t 'cn10k_rx_mseg.c',\n+\t\t 'cn10k_rx_vec.c')\n \n deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']\n deps += ['common_cnxk', 'mempool_cnxk']\n", "prefixes": [ "v4", "27/62" ] }