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GET /api/patches/94719/?format=api
{ "id": 94719, "url": "https://patches.dpdk.org/api/patches/94719/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-24-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-24-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-24-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:23", "name": "[v4,23/62] net/cnxk: add Tx multi-segment version for cn9k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3d631176f4fbcddd1fefe683f7355dd13440ff83", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-24-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94719/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94719/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1E085A0C41;\n\tWed, 23 Jun 2021 06:50:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3E8E441101;\n\tWed, 23 Jun 2021 06:48:37 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 1767741101\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:35 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k7nS025556 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:35 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gn0-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:35 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:33 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:33 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 4BD125B6936;\n Tue, 22 Jun 2021 21:48:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=NUIGxYsAplE1gnj6c6FD6yXtj86Iy8sLYeroRlhcGpY=;\n b=awc033iGmTb24dhOVi8vujEgm3bQhzYVmT1I3PozAS9mS1eLolVAkxmHkgkqnf8vMpTc\n J3ulCMPaKf5soi2zBQoccKCt0k8kQqnfrAA+Jp8OyAN6Ne4kF0LeB4unTWfkqDxlXy+E\n cYu0tD0BhZKiIlMmuIgrjZ3KzW11T/Q0NyQsK7mj38uiXhyrQEE4+wLcmvF/21hNkfle\n R46IMupRdDF20xbX8E3eLMgm2hK0SwGgKBQqTg6QaIFJE7u3BydOPJ4Hy90gkpDC4W/q\n dBnzjOHXkIMiwHfwCiYNZsegyUsdMmSPUsWKSBkPOcnKypqPwBmNautxIricXdODDXjm hA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:23 +0530", "Message-ID": "<20210623044702.4240-24-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "82IPKZNx76OayxAJwNrEMuefyMnjqPoN", "X-Proofpoint-GUID": "82IPKZNx76OayxAJwNrEMuefyMnjqPoN", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 23/62] net/cnxk: add Tx multi-segment version\n for cn9k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add Tx burst multi-segment version for CN9K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/cnxk/cn9k_tx.c | 14 ++++\n drivers/net/cnxk/cn9k_tx.h | 150 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cn9k_tx_mseg.c | 25 +++++++\n drivers/net/cnxk/cnxk_ethdev.h | 4 ++\n drivers/net/cnxk/meson.build | 3 +-\n 5 files changed, 195 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/cnxk/cn9k_tx_mseg.c", "diff": "diff --git a/drivers/net/cnxk/cn9k_tx.c b/drivers/net/cnxk/cn9k_tx.c\nindex a0b022a..8f1d5f5 100644\n--- a/drivers/net/cnxk/cn9k_tx.c\n+++ b/drivers/net/cnxk/cn9k_tx.c\n@@ -21,6 +21,7 @@\n NIX_TX_FASTPATH_MODES\n #undef T\n \n+\n static inline void\n pick_tx_func(struct rte_eth_dev *eth_dev,\n \t const eth_tx_burst_t tx_burst[2][2][2][2][2])\n@@ -39,6 +40,8 @@ pick_tx_func(struct rte_eth_dev *eth_dev,\n void\n cn9k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n {\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n \tconst eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2] = {\n #define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t \\\n \t[f4][f3][f2][f1][f0] = cn9k_nix_xmit_pkts_##name,\n@@ -47,7 +50,18 @@ cn9k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n #undef T\n \t};\n \n+\tconst eth_tx_burst_t nix_eth_tx_burst_mseg[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t \\\n+\t[f4][f3][f2][f1][f0] = cn9k_nix_xmit_pkts_mseg_##name,\n+\n+\t\tNIX_TX_FASTPATH_MODES\n+#undef T\n+\t};\n+\n \tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \n+\tif (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)\n+\t\tpick_tx_func(eth_dev, nix_eth_tx_burst_mseg);\n+\n \trte_mb();\n }\ndiff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h\nindex 7acecc6..d9aa406 100644\n--- a/drivers/net/cnxk/cn9k_tx.h\n+++ b/drivers/net/cnxk/cn9k_tx.h\n@@ -311,6 +311,111 @@ cn9k_nix_xmit_submit_lmt_release(const rte_iova_t io_addr)\n }\n \n static __rte_always_inline uint16_t\n+cn9k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tunion nix_send_sg_s *sg;\n+\tstruct rte_mbuf *m_next;\n+\tuint64_t *slist, sg_u;\n+\tuint64_t nb_segs;\n+\tuint64_t segdw;\n+\tuint8_t off, i;\n+\n+\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n+\tsend_hdr->w0.total = m->pkt_len;\n+\tsend_hdr->w0.aura = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n+\n+\tif (flags & NIX_TX_NEED_EXT_HDR)\n+\t\toff = 2;\n+\telse\n+\t\toff = 0;\n+\n+\tsg = (union nix_send_sg_s *)&cmd[2 + off];\n+\t/* Clear sg->u header before use */\n+\tsg->u &= 0xFC00000000000000;\n+\tsg_u = sg->u;\n+\tslist = &cmd[3 + off];\n+\n+\ti = 0;\n+\tnb_segs = m->nb_segs;\n+\n+\t/* Fill mbuf segments */\n+\tdo {\n+\t\tm_next = m->next;\n+\t\tsg_u = sg_u | ((uint64_t)m->data_len << (i << 4));\n+\t\t*slist = rte_mbuf_data_iova(m);\n+\t\t/* Set invert df if buffer is not to be freed by H/W */\n+\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n+\t\t\tsg_u |= (cnxk_nix_prefree_seg(m) << (i + 55));\n+\t\t\t/* Commit changes to mbuf */\n+\t\t\trte_io_wmb();\n+\t\t}\n+\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n+#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n+\t\tif (!(sg_u & (1ULL << (i + 55))))\n+\t\t\t__mempool_check_cookies(m->pool, (void **)&m, 1, 0);\n+\t\trte_io_wmb();\n+#endif\n+\t\tslist++;\n+\t\ti++;\n+\t\tnb_segs--;\n+\t\tif (i > 2 && nb_segs) {\n+\t\t\ti = 0;\n+\t\t\t/* Next SG subdesc */\n+\t\t\t*(uint64_t *)slist = sg_u & 0xFC00000000000000;\n+\t\t\tsg->u = sg_u;\n+\t\t\tsg->segs = 3;\n+\t\t\tsg = (union nix_send_sg_s *)slist;\n+\t\t\tsg_u = sg->u;\n+\t\t\tslist++;\n+\t\t}\n+\t\tm = m_next;\n+\t} while (nb_segs);\n+\n+\tsg->u = sg_u;\n+\tsg->segs = i;\n+\tsegdw = (uint64_t *)slist - (uint64_t *)&cmd[2 + off];\n+\t/* Roundup extra dwords to multiple of 2 */\n+\tsegdw = (segdw >> 1) + (segdw & 0x1);\n+\t/* Default dwords */\n+\tsegdw += (off >> 1) + 1;\n+\tsend_hdr->w0.sizem1 = segdw - 1;\n+\n+\treturn segdw;\n+}\n+\n+static __rte_always_inline void\n+cn9k_nix_xmit_mseg_prep_lmt(uint64_t *cmd, void *lmt_addr, uint16_t segdw)\n+{\n+\troc_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n+}\n+\n+static __rte_always_inline void\n+cn9k_nix_xmit_mseg_one(uint64_t *cmd, void *lmt_addr, rte_iova_t io_addr,\n+\t\t uint16_t segdw)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\troc_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n+\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n+static __rte_always_inline void\n+cn9k_nix_xmit_mseg_one_release(uint64_t *cmd, void *lmt_addr,\n+\t\t\t rte_iova_t io_addr, uint16_t segdw)\n+{\n+\tuint64_t lmt_status;\n+\n+\trte_io_wmb();\n+\tdo {\n+\t\troc_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n+\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n+static __rte_always_inline uint16_t\n cn9k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \t\t uint64_t *cmd, const uint16_t flags)\n {\n@@ -349,6 +454,48 @@ cn9k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \treturn pkts;\n }\n \n+static __rte_always_inline uint16_t\n+cn9k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\tuint16_t pkts, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct cn9k_eth_txq *txq = tx_queue;\n+\tconst rte_iova_t io_addr = txq->io_addr;\n+\tvoid *lmt_addr = txq->lmt_addr;\n+\tuint64_t lso_tun_fmt;\n+\tuint16_t segdw;\n+\tuint64_t i;\n+\n+\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\n+\troc_lmt_mov(cmd, &txq->cmd[0], cn9k_nix_tx_ext_subs(flags));\n+\n+\t/* Perform header writes before barrier for TSO */\n+\tif (flags & NIX_TX_OFFLOAD_TSO_F) {\n+\t\tlso_tun_fmt = txq->lso_tun_fmt;\n+\n+\t\tfor (i = 0; i < pkts; i++)\n+\t\t\tcn9k_nix_xmit_prepare_tso(tx_pkts[i], flags);\n+\t}\n+\n+\t/* Lets commit any changes in the packet here as no further changes\n+\t * to the packet will be done unless no fast free is enabled.\n+\t */\n+\tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))\n+\t\trte_io_wmb();\n+\n+\tfor (i = 0; i < pkts; i++) {\n+\t\tcn9k_nix_xmit_prepare(tx_pkts[i], cmd, flags, lso_tun_fmt);\n+\t\tsegdw = cn9k_nix_prepare_mseg(tx_pkts[i], cmd, flags);\n+\t\tcn9k_nix_xmit_mseg_one(cmd, lmt_addr, io_addr, segdw);\n+\t}\n+\n+\t/* Reduce the cached count */\n+\ttxq->fc_cache_pkts -= pkts;\n+\n+\treturn pkts;\n+}\n+\n+\n #define L3L4CSUM_F NIX_TX_OFFLOAD_L3_L4_CSUM_F\n #define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\n #define VLAN_F\t NIX_TX_OFFLOAD_VLAN_QINQ_F\n@@ -424,6 +571,9 @@ T(tso_noff_vlan_ol3ol4csum_l3l4csum,\t1, 1, 1, 1, 1,\t6,\t\t\\\n \n #define T(name, f4, f3, f2, f1, f0, sz, flags) \\\n \tuint16_t __rte_noinline __rte_hot cn9k_nix_xmit_pkts_##name( \\\n+\t\tvoid *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_xmit_pkts_mseg_##name( \\\n \t\tvoid *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts);\n \n NIX_TX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn9k_tx_mseg.c b/drivers/net/cnxk/cn9k_tx_mseg.c\nnew file mode 100644\nindex 0000000..65c5f36\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_tx_mseg.c\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_ethdev.h\"\n+#include \"cn9k_tx.h\"\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot\t\t\t\t \\\n+\t\tcn9k_nix_xmit_pkts_mseg_##name(void *tx_queue, \\\n+\t\t\t\t\t struct rte_mbuf **tx_pkts, \\\n+\t\t\t\t\t uint16_t pkts) \\\n+\t{ \\\n+\t\tuint64_t cmd[(sz) + CNXK_NIX_TX_MSEG_SG_DWORDS - 2]; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\t/* For TSO inner checksum is a must */ \\\n+\t\tif (((flags) & NIX_TX_OFFLOAD_TSO_F) &&\t\t\t \\\n+\t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t \\\n+\t\t\treturn 0; \\\n+\t\treturn cn9k_nix_xmit_pkts_mseg(tx_queue, tx_pkts, pkts, cmd, \\\n+\t\t\t\t\t (flags) | NIX_TX_MULTI_SEG_F); \\\n+\t}\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 58cc6b7..276e569 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -46,6 +46,10 @@\n #define CNXK_NIX_TX_NB_SEG_MAX 9\n #endif\n \n+#define CNXK_NIX_TX_MSEG_SG_DWORDS \\\n+\t((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \\\n+\t CNXK_NIX_TX_NB_SEG_MAX)\n+\n #define CNXK_NIX_RSS_L3_L4_SRC_DST \\\n \t(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \\\n \t ETH_RSS_L4_DST_ONLY)\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 6c2cd13..a3cd200 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -19,7 +19,8 @@ sources += files('cn9k_ethdev.c',\n \t\t 'cn9k_rx.c',\n \t\t 'cn9k_rx_mseg.c',\n \t\t 'cn9k_rx_vec.c',\n-\t\t 'cn9k_tx.c')\n+\t\t 'cn9k_tx.c',\n+\t\t 'cn9k_tx_mseg.c')\n # CN10K\n sources += files('cn10k_ethdev.c')\n \n", "prefixes": [ "v4", "23/62" ] }