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GET /api/patches/94716/?format=api
{ "id": 94716, "url": "https://patches.dpdk.org/api/patches/94716/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-21-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-21-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-21-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:20", "name": "[v4,20/62] net/cnxk: add Rx multi-segmented version for cn9k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5b6df1b70a30fe6c692348c84c10757254629d7c", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-21-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94716/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94716/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B241FA0C41;\n\tWed, 23 Jun 2021 06:49:42 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 445F741160;\n\tWed, 23 Jun 2021 06:48:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C0E50406A3\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k6fS025518 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:25 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gm3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:25 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:23 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:23 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 2FD915B6937;\n Tue, 22 Jun 2021 21:48:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=+5DhpvuwUESHCjkiByRZEkscRhXRipNq1WwxZInYOdc=;\n b=IHx013hKDQ+BksNO8VU7GKnB4jadYzuh4taldCSiTf0FUHW6WJ46Fy1vlMBqyJJ/iIym\n PnltHzV1FEa9FRrOqS3EEwPriJG1mVWlpJMU5tD5LJNZYdLdL5ag3Y6kgpdjCbUXSLv+\n wgqnZ0Usx2wAWqSIZCcMhPhVGJ7Qw+WCYSlOJXznH6Ffx9+iEbsyhjwplCdOmO3rJ0M+\n bjqPlBEAT9QomeT5HcOuRGZtsRczGEV0/XkAKs8qjGZEaQiuqhB6XQgFSRjBfllMlKRO\n +omGDL5HBT6xOT89jowBZg4cco9IjSFdMRbYaLYtXN5/HT0BR+5U5YR6UM6f7tguQTUc Dg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:20 +0530", "Message-ID": "<20210623044702.4240-21-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "IFRxnlWYkyRcGBbrJwE3qh03EE7jzwnY", "X-Proofpoint-GUID": "IFRxnlWYkyRcGBbrJwE3qh03EE7jzwnY", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 20/62] net/cnxk: add Rx multi-segmented\n version for cn9k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add Rx burst multi-segmented version for CN9K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/cnxk/cn9k_rx.c | 17 ++++++++++++\n drivers/net/cnxk/cn9k_rx.h | 60 ++++++++++++++++++++++++++++++++++++++---\n drivers/net/cnxk/cn9k_rx_mseg.c | 17 ++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 3 +++\n drivers/net/cnxk/meson.build | 3 ++-\n 5 files changed, 96 insertions(+), 4 deletions(-)\n create mode 100644 drivers/net/cnxk/cn9k_rx_mseg.c", "diff": "diff --git a/drivers/net/cnxk/cn9k_rx.c b/drivers/net/cnxk/cn9k_rx.c\nindex a4297f9..87a62c9 100644\n--- a/drivers/net/cnxk/cn9k_rx.c\n+++ b/drivers/net/cnxk/cn9k_rx.c\n@@ -32,6 +32,8 @@ pick_rx_func(struct rte_eth_dev *eth_dev,\n void\n cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n {\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n \tconst eth_rx_burst_t nix_eth_rx_burst[2][2][2][2] = {\n #define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t\\\n \t[f3][f2][f1][f0] = cn9k_nix_recv_pkts_##name,\n@@ -40,7 +42,22 @@ cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n #undef R\n \t};\n \n+\tconst eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t\\\n+\t[f3][f2][f1][f0] = cn9k_nix_recv_pkts_mseg_##name,\n+\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n \tpick_rx_func(eth_dev, nix_eth_rx_burst);\n \n+\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n+\n+\t/* Copy multi seg version with no offload for tear down sequence */\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n+\t\tdev->rx_pkt_burst_no_offload =\n+\t\t\tnix_eth_rx_burst_mseg[0][0][0][0];\n \trte_mb();\n }\ndiff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h\nindex 92f3c7c..49f80ce 100644\n--- a/drivers/net/cnxk/cn9k_rx.h\n+++ b/drivers/net/cnxk/cn9k_rx.h\n@@ -104,6 +104,53 @@ nix_update_match_id(const uint16_t match_id, uint64_t ol_flags,\n }\n \n static __rte_always_inline void\n+nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n+\t\t uint64_t rearm)\n+{\n+\tconst rte_iova_t *iova_list;\n+\tstruct rte_mbuf *head;\n+\tconst rte_iova_t *eol;\n+\tuint8_t nb_segs;\n+\tuint64_t sg;\n+\n+\tsg = *(const uint64_t *)(rx + 1);\n+\tnb_segs = (sg >> 48) & 0x3;\n+\tmbuf->nb_segs = nb_segs;\n+\tmbuf->data_len = sg & 0xFFFF;\n+\tsg = sg >> 16;\n+\n+\teol = ((const rte_iova_t *)(rx + 1) +\n+\t ((rx->cn9k.desc_sizem1 + 1) << 1));\n+\t/* Skip SG_S and first IOVA*/\n+\tiova_list = ((const rte_iova_t *)(rx + 1)) + 2;\n+\tnb_segs--;\n+\n+\trearm = rearm & ~0xFFFF;\n+\n+\thead = mbuf;\n+\twhile (nb_segs) {\n+\t\tmbuf->next = ((struct rte_mbuf *)*iova_list) - 1;\n+\t\tmbuf = mbuf->next;\n+\n+\t\t__mempool_check_cookies(mbuf->pool, (void **)&mbuf, 1, 1);\n+\n+\t\tmbuf->data_len = sg & 0xFFFF;\n+\t\tsg = sg >> 16;\n+\t\t*(uint64_t *)(&mbuf->rearm_data) = rearm;\n+\t\tnb_segs--;\n+\t\tiova_list++;\n+\n+\t\tif (!nb_segs && (iova_list + 1 < eol)) {\n+\t\t\tsg = *(const uint64_t *)(iova_list);\n+\t\t\tnb_segs = (sg >> 48) & 0x3;\n+\t\t\thead->nb_segs += nb_segs;\n+\t\t\tiova_list = (const rte_iova_t *)(iova_list + 1);\n+\t\t}\n+\t}\n+\tmbuf->next = NULL;\n+}\n+\n+static __rte_always_inline void\n cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t\t struct rte_mbuf *mbuf, const void *lookup_mem,\n \t\t const uint64_t val, const uint16_t flag)\n@@ -138,8 +185,12 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t*(uint64_t *)(&mbuf->rearm_data) = val;\n \tmbuf->pkt_len = len;\n \n-\tmbuf->data_len = len;\n-\tmbuf->next = NULL;\n+\tif (flag & NIX_RX_MULTI_SEG_F) {\n+\t\tnix_cqe_xtract_mseg(rx, mbuf, val);\n+\t} else {\n+\t\tmbuf->data_len = len;\n+\t\tmbuf->next = NULL;\n+\t}\n }\n \n static inline uint16_t\n@@ -239,8 +290,11 @@ R(mark_cksum_rss,\t\t1, 1, 0, 1, MARK_F | CKSUM_F | RSS_F) \\\n R(mark_cksum_ptype,\t\t1, 1, 1, 0, MARK_F | CKSUM_F | PTYPE_F)\\\n R(mark_cksum_ptype_rss,\t\t1, 1, 1, 1, MARK_F | CKSUM_F | PTYPE_F | RSS_F)\n \n-#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n+#define R(name, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_mseg_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts);\n \n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn9k_rx_mseg.c b/drivers/net/cnxk/cn9k_rx_mseg.c\nnew file mode 100644\nindex 0000000..6ad8c1d\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_rx_mseg.c\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_ethdev.h\"\n+#include \"cn9k_rx.h\"\n+\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_mseg_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n+\t{ \\\n+\t\treturn cn9k_nix_recv_pkts(rx_queue, rx_pkts, pkts, \\\n+\t\t\t\t\t (flags) | NIX_RX_MULTI_SEG_F); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex a6f5d36..333a54c 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -163,6 +163,9 @@ struct cnxk_eth_dev {\n \tstruct cnxk_eth_qconf *tx_qconf;\n \tstruct cnxk_eth_qconf *rx_qconf;\n \n+\t/* Rx burst for cleanup(Only Primary) */\n+\teth_rx_burst_t rx_pkt_burst_no_offload;\n+\n \t/* Default mac address */\n \tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n \ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 7a44001..5bfab21 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -16,7 +16,8 @@ sources = files('cnxk_ethdev.c',\n \n # CN9K\n sources += files('cn9k_ethdev.c',\n-\t\t 'cn9k_rx.c')\n+\t\t 'cn9k_rx.c',\n+\t\t 'cn9k_rx_mseg.c')\n # CN10K\n sources += files('cn10k_ethdev.c')\n \n", "prefixes": [ "v4", "20/62" ] }