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GET /api/patches/94715/?format=api
{ "id": 94715, "url": "https://patches.dpdk.org/api/patches/94715/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-20-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-20-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-20-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:19", "name": "[v4,19/62] net/cnxk: add Rx burst for cn9k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "51ba39f5bc01fac100f10fcb022869f26445dbc3", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-20-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94715/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94715/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4AD8CA0C41;\n\tWed, 23 Jun 2021 06:49:36 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1E1C041140;\n\tWed, 23 Jun 2021 06:48:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 985804069C\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:22 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k7XM025541 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:22 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gkw-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:21 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:19 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 0FF4D5B6936;\n Tue, 22 Jun 2021 21:48:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=Q8OsGfYx+eE9SNY9doOrP09SW5AmIOQYxU86uwOnhMs=;\n b=haoIixjuleCtOiNeo6ghUtVOCF63kAx6xX6631eGSgeHbx2FPFxAvz5WrmK2ioEpTQtu\n VC+4/8C5ylqyQyvq3gKSu4bOjfVkPmjPM9x7cO1YU3krJEejQD3EFrxvFj6N9S4ALgY7\n u9P0Ia0Tt51b4JreTKm1HxCyP9SH4oBGZHzi8of3F7HzH+cbjo51DVKa5KGPj4YtAc5X\n nqX4qhs6pHjLiLf95a5aVRjMeiCBDnJphEIU+Zvfx/um7HjEXV8iRNFoUXo0gQ68MD0x\n nQOTcEmvG0Tk5mDWpaewC4WFweQ/CoLgCEdfIqup2D12d1F5L1dKpSw4TZxFdHLOIZcK Yg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:19 +0530", "Message-ID": "<20210623044702.4240-20-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "FMyDJPjN9ILHLJPcBvg95R21b4io4dhK", "X-Proofpoint-GUID": "FMyDJPjN9ILHLJPcBvg95R21b4io4dhK", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 19/62] net/cnxk: add Rx burst for cn9k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Rx burst scalar version for CN9K.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/net/cnxk/cn9k_ethdev.h | 3 +\n drivers/net/cnxk/cn9k_rx.c | 46 ++++++++\n drivers/net/cnxk/cn9k_rx.h | 237 +++++++++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 3 +\n drivers/net/cnxk/meson.build | 3 +-\n 5 files changed, 291 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/cnxk/cn9k_rx.c", "diff": "diff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h\nindex bd7bf50..bab5540 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.h\n+++ b/drivers/net/cnxk/cn9k_ethdev.h\n@@ -31,4 +31,7 @@ struct cn9k_eth_rxq {\n \tuint16_t rq;\n } __plt_cache_aligned;\n \n+/* Rx and Tx routines */\n+void cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev);\n+\n #endif /* __CN9K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cn9k_rx.c b/drivers/net/cnxk/cn9k_rx.c\nnew file mode 100644\nindex 0000000..a4297f9\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_rx.c\n@@ -0,0 +1,46 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_ethdev.h\"\n+#include \"cn9k_rx.h\"\n+\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_##name(\t \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n+\t{ \\\n+\t\treturn cn9k_nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags)); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n+\n+static inline void\n+pick_rx_func(struct rte_eth_dev *eth_dev,\n+\t const eth_rx_burst_t rx_burst[2][2][2][2])\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n+\t/* [MARK] [CKSUM] [PTYPE] [RSS] */\n+\teth_dev->rx_pkt_burst = rx_burst\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];\n+}\n+\n+void\n+cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n+{\n+\tconst eth_rx_burst_t nix_eth_rx_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t\\\n+\t[f3][f2][f1][f0] = cn9k_nix_recv_pkts_##name,\n+\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\n+\trte_mb();\n+}\ndiff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h\nindex 95a1e69..92f3c7c 100644\n--- a/drivers/net/cnxk/cn9k_rx.h\n+++ b/drivers/net/cnxk/cn9k_rx.h\n@@ -7,6 +7,243 @@\n \n #include <rte_ether.h>\n \n+#define NIX_RX_OFFLOAD_NONE\t (0)\n+#define NIX_RX_OFFLOAD_RSS_F\t BIT(0)\n #define NIX_RX_OFFLOAD_PTYPE_F\t BIT(1)\n+#define NIX_RX_OFFLOAD_CHECKSUM_F BIT(2)\n+#define NIX_RX_OFFLOAD_MARK_UPDATE_F BIT(3)\n+\n+/* Flags to control cqe_to_mbuf conversion function.\n+ * Defining it from backwards to denote its been\n+ * not used as offload flags to pick function\n+ */\n+#define NIX_RX_MULTI_SEG_F BIT(15)\n+\n+#define CNXK_NIX_CQ_ENTRY_SZ 128\n+#define NIX_DESCS_PER_LOOP 4\n+#define CQE_CAST(x)\t ((struct nix_cqe_hdr_s *)(x))\n+#define CQE_SZ(x)\t ((x) * CNXK_NIX_CQ_ENTRY_SZ)\n+\n+union mbuf_initializer {\n+\tstruct {\n+\t\tuint16_t data_off;\n+\t\tuint16_t refcnt;\n+\t\tuint16_t nb_segs;\n+\t\tuint16_t port;\n+\t} fields;\n+\tuint64_t value;\n+};\n+\n+static __rte_always_inline uint64_t\n+nix_clear_data_off(uint64_t oldval)\n+{\n+\tunion mbuf_initializer mbuf_init = {.value = oldval};\n+\n+\tmbuf_init.fields.data_off = 0;\n+\treturn mbuf_init.value;\n+}\n+\n+static __rte_always_inline struct rte_mbuf *\n+nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)\n+{\n+\trte_iova_t buff;\n+\n+\t/* Skip CQE, NIX_RX_PARSE_S and SG HDR(9 DWORDs) and peek buff addr */\n+\tbuff = *((rte_iova_t *)((uint64_t *)cq + 9));\n+\treturn (struct rte_mbuf *)(buff - data_off);\n+}\n+\n+static __rte_always_inline uint32_t\n+nix_ptype_get(const void *const lookup_mem, const uint64_t in)\n+{\n+\tconst uint16_t *const ptype = lookup_mem;\n+\tconst uint16_t lh_lg_lf = (in & 0xFFF0000000000000) >> 52;\n+\tconst uint16_t tu_l2 = ptype[(in & 0x000FFFF000000000) >> 36];\n+\tconst uint16_t il4_tu = ptype[PTYPE_NON_TUNNEL_ARRAY_SZ + lh_lg_lf];\n+\n+\treturn (il4_tu << PTYPE_NON_TUNNEL_WIDTH) | tu_l2;\n+}\n+\n+static __rte_always_inline uint32_t\n+nix_rx_olflags_get(const void *const lookup_mem, const uint64_t in)\n+{\n+\tconst uint32_t *const ol_flags =\n+\t\t(const uint32_t *)((const uint8_t *)lookup_mem +\n+\t\t\t\t PTYPE_ARRAY_SZ);\n+\n+\treturn ol_flags[(in & 0xfff00000) >> 20];\n+}\n+\n+static inline uint64_t\n+nix_update_match_id(const uint16_t match_id, uint64_t ol_flags,\n+\t\t struct rte_mbuf *mbuf)\n+{\n+\t/* There is no separate bit to check match_id\n+\t * is valid or not? and no flag to identify it is an\n+\t * RTE_FLOW_ACTION_TYPE_FLAG vs RTE_FLOW_ACTION_TYPE_MARK\n+\t * action. The former case addressed through 0 being invalid\n+\t * value and inc/dec match_id pair when MARK is activated.\n+\t * The later case addressed through defining\n+\t * CNXK_FLOW_MARK_DEFAULT as value for\n+\t * RTE_FLOW_ACTION_TYPE_MARK.\n+\t * This would translate to not use\n+\t * CNXK_FLOW_ACTION_FLAG_DEFAULT - 1 and\n+\t * CNXK_FLOW_ACTION_FLAG_DEFAULT for match_id.\n+\t * i.e valid mark_id's are from\n+\t * 0 to CNXK_FLOW_ACTION_FLAG_DEFAULT - 2\n+\t */\n+\tif (likely(match_id)) {\n+\t\tol_flags |= PKT_RX_FDIR;\n+\t\tif (match_id != CNXK_FLOW_ACTION_FLAG_DEFAULT) {\n+\t\t\tol_flags |= PKT_RX_FDIR_ID;\n+\t\t\tmbuf->hash.fdir.hi = match_id - 1;\n+\t\t}\n+\t}\n+\n+\treturn ol_flags;\n+}\n+\n+static __rte_always_inline void\n+cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n+\t\t struct rte_mbuf *mbuf, const void *lookup_mem,\n+\t\t const uint64_t val, const uint16_t flag)\n+{\n+\tconst union nix_rx_parse_u *rx =\n+\t\t(const union nix_rx_parse_u *)((const uint64_t *)cq + 1);\n+\tconst uint16_t len = rx->cn9k.pkt_lenm1 + 1;\n+\tconst uint64_t w1 = *(const uint64_t *)rx;\n+\tuint64_t ol_flags = 0;\n+\n+\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t__mempool_check_cookies(mbuf->pool, (void **)&mbuf, 1, 1);\n+\n+\tif (flag & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\tmbuf->packet_type = nix_ptype_get(lookup_mem, w1);\n+\telse\n+\t\tmbuf->packet_type = 0;\n+\n+\tif (flag & NIX_RX_OFFLOAD_RSS_F) {\n+\t\tmbuf->hash.rss = tag;\n+\t\tol_flags |= PKT_RX_RSS_HASH;\n+\t}\n+\n+\tif (flag & NIX_RX_OFFLOAD_CHECKSUM_F)\n+\t\tol_flags |= nix_rx_olflags_get(lookup_mem, w1);\n+\n+\tif (flag & NIX_RX_OFFLOAD_MARK_UPDATE_F)\n+\t\tol_flags =\n+\t\t\tnix_update_match_id(rx->cn9k.match_id, ol_flags, mbuf);\n+\n+\tmbuf->ol_flags = ol_flags;\n+\t*(uint64_t *)(&mbuf->rearm_data) = val;\n+\tmbuf->pkt_len = len;\n+\n+\tmbuf->data_len = len;\n+\tmbuf->next = NULL;\n+}\n+\n+static inline uint16_t\n+nix_rx_nb_pkts(struct cn9k_eth_rxq *rxq, const uint64_t wdata,\n+\t const uint16_t pkts, const uint32_t qmask)\n+{\n+\tuint32_t available = rxq->available;\n+\n+\t/* Update the available count if cached value is not enough */\n+\tif (unlikely(available < pkts)) {\n+\t\tuint64_t reg, head, tail;\n+\n+\t\t/* Use LDADDA version to avoid reorder */\n+\t\treg = roc_atomic64_add_sync(wdata, rxq->cq_status);\n+\t\t/* CQ_OP_STATUS operation error */\n+\t\tif (reg & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR) ||\n+\t\t reg & BIT_ULL(NIX_CQ_OP_STAT_CQ_ERR))\n+\t\t\treturn 0;\n+\n+\t\ttail = reg & 0xFFFFF;\n+\t\thead = (reg >> 20) & 0xFFFFF;\n+\t\tif (tail < head)\n+\t\t\tavailable = tail - head + qmask + 1;\n+\t\telse\n+\t\t\tavailable = tail - head;\n+\n+\t\trxq->available = available;\n+\t}\n+\n+\treturn RTE_MIN(pkts, available);\n+}\n+\n+static __rte_always_inline uint16_t\n+cn9k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n+\t\t const uint16_t flags)\n+{\n+\tstruct cn9k_eth_rxq *rxq = rx_queue;\n+\tconst uint64_t mbuf_init = rxq->mbuf_initializer;\n+\tconst void *lookup_mem = rxq->lookup_mem;\n+\tconst uint64_t data_off = rxq->data_off;\n+\tconst uintptr_t desc = rxq->desc;\n+\tconst uint64_t wdata = rxq->wdata;\n+\tconst uint32_t qmask = rxq->qmask;\n+\tuint16_t packets = 0, nb_pkts;\n+\tuint32_t head = rxq->head;\n+\tstruct nix_cqe_hdr_s *cq;\n+\tstruct rte_mbuf *mbuf;\n+\n+\tnb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\n+\twhile (packets < nb_pkts) {\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal(\n+\t\t\t(void *)(desc + (CQE_SZ((head + 2) & qmask))));\n+\t\tcq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));\n+\n+\t\tmbuf = nix_get_mbuf_from_cqe(cq, data_off);\n+\n+\t\tcn9k_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,\n+\t\t\t\t flags);\n+\t\trx_pkts[packets++] = mbuf;\n+\t\troc_prefetch_store_keep(mbuf);\n+\t\thead++;\n+\t\thead &= qmask;\n+\t}\n+\n+\trxq->head = head;\n+\trxq->available -= nb_pkts;\n+\n+\t/* Free all the CQs that we've processed */\n+\tplt_write64((wdata | nb_pkts), rxq->cq_door);\n+\n+\treturn nb_pkts;\n+}\n+\n+#define RSS_F\t NIX_RX_OFFLOAD_RSS_F\n+#define PTYPE_F\t NIX_RX_OFFLOAD_PTYPE_F\n+#define CKSUM_F\t NIX_RX_OFFLOAD_CHECKSUM_F\n+#define MARK_F\t NIX_RX_OFFLOAD_MARK_UPDATE_F\n+\n+/* [MARK] [CKSUM] [PTYPE] [RSS] */\n+#define NIX_RX_FASTPATH_MODES\t\t\t\t\t \\\n+R(no_offload,\t\t\t0, 0, 0, 0, NIX_RX_OFFLOAD_NONE) \\\n+R(rss,\t\t\t\t0, 0, 0, 1, RSS_F)\t\t \\\n+R(ptype,\t\t\t0, 0, 1, 0, PTYPE_F)\t\t \\\n+R(ptype_rss,\t\t\t0, 0, 1, 1, PTYPE_F | RSS_F)\t \\\n+R(cksum,\t\t\t0, 1, 0, 0, CKSUM_F)\t\t \\\n+R(cksum_rss,\t\t\t0, 1, 0, 1, CKSUM_F | RSS_F)\t \\\n+R(cksum_ptype,\t\t\t0, 1, 1, 0, CKSUM_F | PTYPE_F)\t \\\n+R(cksum_ptype_rss,\t\t0, 1, 1, 1, CKSUM_F | PTYPE_F | RSS_F) \\\n+R(mark,\t\t\t\t1, 0, 0, 0, MARK_F)\t\t \\\n+R(mark_rss,\t\t\t1, 0, 0, 1, MARK_F | RSS_F)\t \\\n+R(mark_ptype,\t\t\t1, 0, 1, 0, MARK_F | PTYPE_F)\t \\\n+R(mark_ptype_rss,\t\t1, 0, 1, 1, MARK_F | PTYPE_F | RSS_F) \\\n+R(mark_cksum,\t\t\t1, 1, 0, 0, MARK_F | CKSUM_F)\t \\\n+R(mark_cksum_rss,\t\t1, 1, 0, 1, MARK_F | CKSUM_F | RSS_F) \\\n+R(mark_cksum_ptype,\t\t1, 1, 1, 0, MARK_F | CKSUM_F | PTYPE_F)\\\n+R(mark_cksum_ptype_rss,\t\t1, 1, 1, 1, MARK_F | CKSUM_F | PTYPE_F | RSS_F)\n+\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n \n #endif /* __CN9K_RX_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 5a52489..a6f5d36 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -91,6 +91,9 @@\n #define RSS_SCTP_INDEX 4\n #define RSS_DMAC_INDEX 5\n \n+/* Default mark value used when none is provided. */\n+#define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff\n+\n #define PTYPE_NON_TUNNEL_WIDTH\t 16\n #define PTYPE_TUNNEL_WIDTH\t 12\n #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 5bc0bb5..7a44001 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -15,7 +15,8 @@ sources = files('cnxk_ethdev.c',\n \t\t'cnxk_lookup.c')\n \n # CN9K\n-sources += files('cn9k_ethdev.c')\n+sources += files('cn9k_ethdev.c',\n+\t\t 'cn9k_rx.c')\n # CN10K\n sources += files('cn10k_ethdev.c')\n \n", "prefixes": [ "v4", "19/62" ] }