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GET /api/patches/94711/?format=api
{ "id": 94711, "url": "https://patches.dpdk.org/api/patches/94711/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-16-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-16-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-16-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:15", "name": "[v4,15/62] net/cnxk: add Rx queue setup and release", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "047239449fa70f3e765b62f7dc99b4dee626fd12", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-16-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94711/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94711/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EE44DA0C41;\n\tWed, 23 Jun 2021 06:49:07 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5AB5141102;\n\tWed, 23 Jun 2021 06:48:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D414A41101\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:48:08 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4jY9T026990 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:08 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39bx5j80pk-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:48:07 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:48:06 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:48:06 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 864015B693E;\n Tue, 22 Jun 2021 21:48:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=CvuSxHSB91D6hg/xVgFenK6FmhB0XfBYDiJg0+9paLw=;\n b=C2h5sa3wi4Obkuv1sTFN7X1NswSSfx2+mM4UwKMBRKso84JBhVMwE64xE8wS0+1sIG3i\n zr1HoiFGRz9I5HZfI3encAWsNv9LFW706Ls2eP+Utne+OolCuXfnd4HJGW1ujDJ+X7IO\n OFZycyEkMXt3l4Znusvxa8rKtTcQFJ3YP+UpOyxLMYnmpQmeS1pceUM1TO6oz8lhnu0k\n FR/ms+GtjCJJTG8IOVVDuo5RZJZOjOgqxUBbg5rzZrgrwHLj73pTSNqS9H+1LOviG1BS\n rQPWnZ9Amb71xIHGB2FPrre3/F6E0A8JeYqe3/inTaAd5CSanVRbgwkqJBtx5peeauSS Jg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:15 +0530", "Message-ID": "<20210623044702.4240-16-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "VbTZxOgA79mcwVOVXQZmcgnCFzgUQ_n_", "X-Proofpoint-GUID": "VbTZxOgA79mcwVOVXQZmcgnCFzgUQ_n_", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 15/62] net/cnxk: add Rx queue setup and release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add Rx queue setup and release op for CN9K and CN10K\nSoC. Release is completely common while setup is platform\ndependent due to fast path Rx queue structure variation.\nFastpath is platform dependent partly due to core cacheline\nsize difference.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/features/cnxk.ini | 1 +\n doc/guides/nics/features/cnxk_vec.ini | 1 +\n doc/guides/nics/features/cnxk_vf.ini | 1 +\n drivers/net/cnxk/cn10k_ethdev.c | 44 +++++++++\n drivers/net/cnxk/cn10k_ethdev.h | 14 +++\n drivers/net/cnxk/cn9k_ethdev.c | 44 +++++++++\n drivers/net/cnxk/cn9k_ethdev.h | 14 +++\n drivers/net/cnxk/cnxk_ethdev.c | 172 ++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 9 ++\n 9 files changed, 300 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex affbbd9..a9d2b03 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -10,6 +10,7 @@ SR-IOV = Y\n Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n+Runtime Rx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n Linux = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex 836cc9f..6a8ca1f 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -10,6 +10,7 @@ SR-IOV = Y\n Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n+Runtime Rx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n Linux = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex 29bb24f..f761638 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -9,6 +9,7 @@ Lock-free Tx queue = Y\n Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n+Runtime Rx queue setup = Y\n RSS hash = Y\n Inner RSS = Y\n Linux = Y\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex d971bbd..b87c4e5 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -4,6 +4,49 @@\n #include \"cn10k_ethdev.h\"\n \n static int\n+cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t uint16_t nb_desc, unsigned int socket,\n+\t\t\t const struct rte_eth_rxconf *rx_conf,\n+\t\t\t struct rte_mempool *mp)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cn10k_eth_rxq *rxq;\n+\tstruct roc_nix_rq *rq;\n+\tstruct roc_nix_cq *cq;\n+\tint rc;\n+\n+\tRTE_SET_USED(socket);\n+\n+\t/* CQ Errata needs min 4K ring */\n+\tif (dev->cq_min_4k && nb_desc < 4096)\n+\t\tnb_desc = 4096;\n+\n+\t/* Common Rx queue setup */\n+\trc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,\n+\t\t\t\t sizeof(struct cn10k_eth_rxq), rx_conf, mp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trq = &dev->rqs[qid];\n+\tcq = &dev->cqs[qid];\n+\n+\t/* Update fast path queue */\n+\trxq = eth_dev->data->rx_queues[qid];\n+\trxq->rq = qid;\n+\trxq->desc = (uintptr_t)cq->desc_base;\n+\trxq->cq_door = cq->door;\n+\trxq->cq_status = cq->status;\n+\trxq->wdata = cq->wdata;\n+\trxq->head = cq->head;\n+\trxq->qmask = cq->qmask;\n+\n+\t/* Data offset from data to start of mbuf is first_skip */\n+\trxq->data_off = rq->first_skip;\n+\trxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);\n+\treturn 0;\n+}\n+\n+static int\n cn10k_nix_configure(struct rte_eth_dev *eth_dev)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n@@ -33,6 +76,7 @@ nix_eth_dev_ops_override(void)\n \n \t/* Update platform specific ops */\n \tcnxk_eth_dev_ops.dev_configure = cn10k_nix_configure;\n+\tcnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup;\n }\n \n static int\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex 1bf4a65..08e11bb 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -6,4 +6,18 @@\n \n #include <cnxk_ethdev.h>\n \n+struct cn10k_eth_rxq {\n+\tuint64_t mbuf_initializer;\n+\tuintptr_t desc;\n+\tvoid *lookup_mem;\n+\tuintptr_t cq_door;\n+\tuint64_t wdata;\n+\tint64_t *cq_status;\n+\tuint32_t head;\n+\tuint32_t qmask;\n+\tuint32_t available;\n+\tuint16_t data_off;\n+\tuint16_t rq;\n+} __plt_cache_aligned;\n+\n #endif /* __CN10K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex 2fb7c14..2ab035e 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -4,6 +4,49 @@\n #include \"cn9k_ethdev.h\"\n \n static int\n+cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\tuint16_t nb_desc, unsigned int socket,\n+\t\t\tconst struct rte_eth_rxconf *rx_conf,\n+\t\t\tstruct rte_mempool *mp)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cn9k_eth_rxq *rxq;\n+\tstruct roc_nix_rq *rq;\n+\tstruct roc_nix_cq *cq;\n+\tint rc;\n+\n+\tRTE_SET_USED(socket);\n+\n+\t/* CQ Errata needs min 4K ring */\n+\tif (dev->cq_min_4k && nb_desc < 4096)\n+\t\tnb_desc = 4096;\n+\n+\t/* Common Rx queue setup */\n+\trc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc,\n+\t\t\t\t sizeof(struct cn9k_eth_rxq), rx_conf, mp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trq = &dev->rqs[qid];\n+\tcq = &dev->cqs[qid];\n+\n+\t/* Update fast path queue */\n+\trxq = eth_dev->data->rx_queues[qid];\n+\trxq->rq = qid;\n+\trxq->desc = (uintptr_t)cq->desc_base;\n+\trxq->cq_door = cq->door;\n+\trxq->cq_status = cq->status;\n+\trxq->wdata = cq->wdata;\n+\trxq->head = cq->head;\n+\trxq->qmask = cq->qmask;\n+\n+\t/* Data offset from data to start of mbuf is first_skip */\n+\trxq->data_off = rq->first_skip;\n+\trxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);\n+\treturn 0;\n+}\n+\n+static int\n cn9k_nix_configure(struct rte_eth_dev *eth_dev)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n@@ -44,6 +87,7 @@ nix_eth_dev_ops_override(void)\n \n \t/* Update platform specific ops */\n \tcnxk_eth_dev_ops.dev_configure = cn9k_nix_configure;\n+\tcnxk_eth_dev_ops.rx_queue_setup = cn9k_nix_rx_queue_setup;\n }\n \n static int\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h\nindex 15d9397..6384609 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.h\n+++ b/drivers/net/cnxk/cn9k_ethdev.h\n@@ -6,4 +6,18 @@\n \n #include <cnxk_ethdev.h>\n \n+struct cn9k_eth_rxq {\n+\tuint64_t mbuf_initializer;\n+\tuint64_t data_off;\n+\tuintptr_t desc;\n+\tvoid *lookup_mem;\n+\tuintptr_t cq_door;\n+\tuint64_t wdata;\n+\tint64_t *cq_status;\n+\tuint32_t head;\n+\tuint32_t qmask;\n+\tuint32_t available;\n+\tuint16_t rq;\n+} __plt_cache_aligned;\n+\n #endif /* __CN9K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex ea49809..2775fe4 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -37,6 +37,177 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev)\n \treturn speed_capa;\n }\n \n+uint64_t\n+cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev)\n+{\n+\tuint16_t port_id = dev->eth_dev->data->port_id;\n+\tstruct rte_mbuf mb_def;\n+\tuint64_t *tmp;\n+\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -\n+\t\t\t\t offsetof(struct rte_mbuf, data_off) !=\n+\t\t\t 2);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -\n+\t\t\t\t offsetof(struct rte_mbuf, data_off) !=\n+\t\t\t 4);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -\n+\t\t\t\t offsetof(struct rte_mbuf, data_off) !=\n+\t\t\t 6);\n+\tmb_def.nb_segs = 1;\n+\tmb_def.data_off = RTE_PKTMBUF_HEADROOM;\n+\tmb_def.port = port_id;\n+\trte_mbuf_refcnt_set(&mb_def, 1);\n+\n+\t/* Prevent compiler reordering: rearm_data covers previous fields */\n+\trte_compiler_barrier();\n+\ttmp = (uint64_t *)&mb_def.rearm_data;\n+\n+\treturn *tmp;\n+}\n+\n+int\n+cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\tuint16_t nb_desc, uint16_t fp_rx_q_sz,\n+\t\t\tconst struct rte_eth_rxconf *rx_conf,\n+\t\t\tstruct rte_mempool *mp)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct cnxk_eth_rxq_sp *rxq_sp;\n+\tstruct rte_mempool_ops *ops;\n+\tconst char *platform_ops;\n+\tstruct roc_nix_rq *rq;\n+\tstruct roc_nix_cq *cq;\n+\tuint16_t first_skip;\n+\tint rc = -EINVAL;\n+\tsize_t rxq_sz;\n+\n+\t/* Sanity checks */\n+\tif (rx_conf->rx_deferred_start == 1) {\n+\t\tplt_err(\"Deferred Rx start is not supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\tplatform_ops = rte_mbuf_platform_mempool_ops();\n+\t/* This driver needs cnxk_npa mempool ops to work */\n+\tops = rte_mempool_get_ops(mp->ops_index);\n+\tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n+\t\tplt_err(\"mempool ops should be of cnxk_npa type\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (mp->pool_id == 0) {\n+\t\tplt_err(\"Invalid pool_id\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed */\n+\tif (eth_dev->data->rx_queues[qid] != NULL) {\n+\t\tconst struct eth_dev_ops *dev_ops = eth_dev->dev_ops;\n+\n+\t\tplt_nix_dbg(\"Freeing memory prior to re-allocation %d\", qid);\n+\t\tdev_ops->rx_queue_release(eth_dev->data->rx_queues[qid]);\n+\t\teth_dev->data->rx_queues[qid] = NULL;\n+\t}\n+\n+\t/* Setup ROC CQ */\n+\tcq = &dev->cqs[qid];\n+\tcq->qid = qid;\n+\tcq->nb_desc = nb_desc;\n+\trc = roc_nix_cq_init(&dev->nix, cq);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc cq for rq=%d, rc=%d\", qid, rc);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Setup ROC RQ */\n+\trq = &dev->rqs[qid];\n+\trq->qid = qid;\n+\trq->aura_handle = mp->pool_id;\n+\trq->flow_tag_width = 32;\n+\trq->sso_ena = false;\n+\n+\t/* Calculate first mbuf skip */\n+\tfirst_skip = (sizeof(struct rte_mbuf));\n+\tfirst_skip += RTE_PKTMBUF_HEADROOM;\n+\tfirst_skip += rte_pktmbuf_priv_size(mp);\n+\trq->first_skip = first_skip;\n+\trq->later_skip = sizeof(struct rte_mbuf);\n+\trq->lpb_size = mp->elt_size;\n+\n+\trc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc rq for rq=%d, rc=%d\", qid, rc);\n+\t\tgoto cq_fini;\n+\t}\n+\n+\t/* Allocate and setup fast path rx queue */\n+\trc = -ENOMEM;\n+\trxq_sz = sizeof(struct cnxk_eth_rxq_sp) + fp_rx_q_sz;\n+\trxq_sp = plt_zmalloc(rxq_sz, PLT_CACHE_LINE_SIZE);\n+\tif (!rxq_sp) {\n+\t\tplt_err(\"Failed to alloc rx queue for rq=%d\", qid);\n+\t\tgoto rq_fini;\n+\t}\n+\n+\t/* Setup slow path fields */\n+\trxq_sp->dev = dev;\n+\trxq_sp->qid = qid;\n+\trxq_sp->qconf.conf.rx = *rx_conf;\n+\trxq_sp->qconf.nb_desc = nb_desc;\n+\trxq_sp->qconf.mp = mp;\n+\n+\tplt_nix_dbg(\"rq=%d pool=%s nb_desc=%d->%d\", qid, mp->name, nb_desc,\n+\t\t cq->nb_desc);\n+\n+\t/* Store start of fast path area */\n+\teth_dev->data->rx_queues[qid] = rxq_sp + 1;\n+\teth_dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+rq_fini:\n+\trc |= roc_nix_rq_fini(rq);\n+cq_fini:\n+\trc |= roc_nix_cq_fini(cq);\n+fail:\n+\treturn rc;\n+}\n+\n+static void\n+cnxk_nix_rx_queue_release(void *rxq)\n+{\n+\tstruct cnxk_eth_rxq_sp *rxq_sp;\n+\tstruct cnxk_eth_dev *dev;\n+\tstruct roc_nix_rq *rq;\n+\tstruct roc_nix_cq *cq;\n+\tuint16_t qid;\n+\tint rc;\n+\n+\tif (!rxq)\n+\t\treturn;\n+\n+\trxq_sp = cnxk_eth_rxq_to_sp(rxq);\n+\tdev = rxq_sp->dev;\n+\tqid = rxq_sp->qid;\n+\n+\tplt_nix_dbg(\"Releasing rxq %u\", qid);\n+\n+\t/* Cleanup ROC RQ */\n+\trq = &dev->rqs[qid];\n+\trc = roc_nix_rq_fini(rq);\n+\tif (rc)\n+\t\tplt_err(\"Failed to cleanup rq, rc=%d\", rc);\n+\n+\t/* Cleanup ROC CQ */\n+\tcq = &dev->cqs[qid];\n+\trc = roc_nix_cq_fini(cq);\n+\tif (rc)\n+\t\tplt_err(\"Failed to cleanup cq, rc=%d\", rc);\n+\n+\t/* Finally free fast path area */\n+\tplt_free(rxq_sp);\n+}\n+\n uint32_t\n cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,\n \t\t uint8_t rss_level)\n@@ -602,6 +773,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n struct eth_dev_ops cnxk_eth_dev_ops = {\n \t.dev_infos_get = cnxk_nix_info_get,\n \t.link_update = cnxk_nix_link_update,\n+\t.rx_queue_release = cnxk_nix_rx_queue_release,\n };\n \n static int\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex daa87af..4a7c2ca 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -10,6 +10,9 @@\n #include <ethdev_driver.h>\n #include <ethdev_pci.h>\n #include <rte_kvargs.h>\n+#include <rte_mbuf.h>\n+#include <rte_mbuf_pool_ops.h>\n+#include <rte_mempool.h>\n \n #include \"roc_api.h\"\n \n@@ -194,6 +197,12 @@ int cnxk_nix_remove(struct rte_pci_device *pci_dev);\n int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_dev_info *dev_info);\n int cnxk_nix_configure(struct rte_eth_dev *eth_dev);\n+int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t uint16_t nb_desc, uint16_t fp_rx_q_sz,\n+\t\t\t const struct rte_eth_rxconf *rx_conf,\n+\t\t\t struct rte_mempool *mp);\n+\n+uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);\n \n /* RSS */\n uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,\n", "prefixes": [ "v4", "15/62" ] }