Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94708/?format=api
{ "id": 94708, "url": "https://patches.dpdk.org/api/patches/94708/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-13-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-13-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-13-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:12", "name": "[v4,12/62] net/cnxk: support common dev infos get", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "90dddca05edacd7b86ca155fd87c799e2b8009d3", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-13-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94708/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94708/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4FAC9A0C41;\n\tWed, 23 Jun 2021 06:48:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6C678410EB;\n\tWed, 23 Jun 2021 06:48:00 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 9921D40E5A\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:47:58 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4jXM6026976 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:57 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39bx5j80nx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:57 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:56 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:56 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 6A6085B6937;\n Tue, 22 Jun 2021 21:47:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=bdhcjQ+//NAY7xU+a71wAiPSrt+ZTZsKjOwy2GpsX9I=;\n b=aAjKJEhjnG2HrrUzL/hd8Abps9c4P5m/L6108dF8xzw0fA3b6GiGjvQ/H8/BMiK+FuuO\n hiq23rJ4dIcBDUijmh2DI1fBd8nG95vW+gtkzijQDHhSRwUFEgu49ymeaXv6J+PGGNDO\n GYvww1HQ+BQC1irsRO0IAyCPzAI28noYM6rWO6JagMKOE7Gn4Y7616MTRQhd465JM6HV\n Z8TQ1/jCINUZFnWI9VmaccApb7JkWfIwcpO32B7lcumgCsvyWkBFpxBlH4Dregkc/K7I\n uHBkwdsKI9gI7HJJBgg842E4qfayJfW+tRsup1Om+TYp+5znjEsq+J7rTv5vOHjItwDy ig==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:12 +0530", "Message-ID": "<20210623044702.4240-13-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "SQcjLMFSCZnD_r0Ugo9yRsgskMThqEst", "X-Proofpoint-GUID": "SQcjLMFSCZnD_r0Ugo9yRsgskMThqEst", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 12/62] net/cnxk: support common dev infos get", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support to retrieve dev infos get for CN9K and CN10K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 3 ++\n doc/guides/nics/features/cnxk.ini | 4 ++\n doc/guides/nics/features/cnxk_vec.ini | 4 ++\n doc/guides/nics/features/cnxk_vf.ini | 3 ++\n drivers/net/cnxk/cnxk_ethdev.c | 4 +-\n drivers/net/cnxk/cnxk_ethdev.h | 33 ++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev_ops.c | 71 +++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/meson.build | 1 +\n 8 files changed, 122 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/cnxk/cnxk_ethdev_ops.c", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 6652e17..6bd410b 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -16,6 +16,9 @@ Features\n \n Features of the CNXK Ethdev PMD are:\n \n+- SR-IOV VF\n+- Lock-free Tx queue\n+\n Prerequisites\n -------------\n \ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex 2c23464..b426340 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -4,6 +4,10 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Speed capabilities = Y\n+Lock-free Tx queue = Y\n+SR-IOV = Y\n+Multiprocess aware = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex de78516..292ac1e 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -4,6 +4,10 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Speed capabilities = Y\n+Lock-free Tx queue = Y\n+SR-IOV = Y\n+Multiprocess aware = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex 9c96351..bc2eb8a 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -4,6 +4,9 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Speed capabilities = Y\n+Lock-free Tx queue = Y\n+Multiprocess aware = Y\n Linux = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 109fd35..066e01c 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -38,7 +38,9 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev)\n }\n \n /* CNXK platform independent eth dev ops */\n-struct eth_dev_ops cnxk_eth_dev_ops;\n+struct eth_dev_ops cnxk_eth_dev_ops = {\n+\t.dev_infos_get = cnxk_nix_info_get,\n+};\n \n static int\n cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 97e3a15..8d9a7e0 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -15,9 +15,40 @@\n \n #define CNXK_ETH_DEV_PMD_VERSION \"1.0\"\n \n+/* VLAN tag inserted by NIX_TX_VTAG_ACTION.\n+ * In Tx space is always reserved for this in FRS.\n+ */\n+#define CNXK_NIX_MAX_VTAG_INS\t 2\n+#define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)\n+\n+/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */\n+#define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)\n+\n+#define CNXK_NIX_RX_MIN_DESC\t 16\n+#define CNXK_NIX_RX_MIN_DESC_ALIGN 16\n+#define CNXK_NIX_RX_NB_SEG_MAX\t 6\n+#define CNXK_NIX_RX_DEFAULT_RING_SZ 4096\n /* Max supported SQB count */\n #define CNXK_NIX_TX_MAX_SQB 512\n \n+/* If PTP is enabled additional SEND MEM DESC is required which\n+ * takes 2 words, hence max 7 iova address are possible\n+ */\n+#if defined(RTE_LIBRTE_IEEE1588)\n+#define CNXK_NIX_TX_NB_SEG_MAX 7\n+#else\n+#define CNXK_NIX_TX_NB_SEG_MAX 9\n+#endif\n+\n+#define CNXK_NIX_RSS_L3_L4_SRC_DST \\\n+\t(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \\\n+\t ETH_RSS_L4_DST_ONLY)\n+\n+#define CNXK_NIX_RSS_OFFLOAD \\\n+\t(ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \\\n+\t ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \\\n+\t CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)\n+\n #define CNXK_NIX_TX_OFFLOAD_CAPA \\\n \t(DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \\\n \t DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \\\n@@ -77,6 +108,8 @@ extern struct eth_dev_ops cnxk_eth_dev_ops;\n int cnxk_nix_probe(struct rte_pci_driver *pci_drv,\n \t\t struct rte_pci_device *pci_dev);\n int cnxk_nix_remove(struct rte_pci_device *pci_dev);\n+int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_dev_info *dev_info);\n \n /* Devargs */\n int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nnew file mode 100644\nindex 0000000..4a45956\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -0,0 +1,71 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <cnxk_ethdev.h>\n+\n+int\n+cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tint max_rx_pktlen;\n+\n+\tmax_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN -\n+\t\t\t CNXK_NIX_MAX_VTAG_ACT_SIZE);\n+\n+\tdevinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN;\n+\tdevinfo->max_rx_pktlen = max_rx_pktlen;\n+\tdevinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;\n+\tdevinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;\n+\tdevinfo->max_mac_addrs = dev->max_mac_entries;\n+\tdevinfo->max_vfs = pci_dev->max_vfs;\n+\tdevinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD;\n+\tdevinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;\n+\n+\tdevinfo->rx_offload_capa = dev->rx_offload_capa;\n+\tdevinfo->tx_offload_capa = dev->tx_offload_capa;\n+\tdevinfo->rx_queue_offload_capa = 0;\n+\tdevinfo->tx_queue_offload_capa = 0;\n+\n+\tdevinfo->reta_size = dev->nix.reta_sz;\n+\tdevinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN;\n+\tdevinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD;\n+\n+\tdevinfo->default_rxconf = (struct rte_eth_rxconf){\n+\t\t.rx_drop_en = 0,\n+\t\t.offloads = 0,\n+\t};\n+\n+\tdevinfo->default_txconf = (struct rte_eth_txconf){\n+\t\t.offloads = 0,\n+\t};\n+\n+\tdevinfo->default_rxportconf = (struct rte_eth_dev_portconf){\n+\t\t.ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ,\n+\t};\n+\n+\tdevinfo->rx_desc_lim = (struct rte_eth_desc_lim){\n+\t\t.nb_max = UINT16_MAX,\n+\t\t.nb_min = CNXK_NIX_RX_MIN_DESC,\n+\t\t.nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN,\n+\t\t.nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX,\n+\t\t.nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX,\n+\t};\n+\tdevinfo->rx_desc_lim.nb_max =\n+\t\tRTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,\n+\t\t\t\t CNXK_NIX_RX_MIN_DESC_ALIGN);\n+\n+\tdevinfo->tx_desc_lim = (struct rte_eth_desc_lim){\n+\t\t.nb_max = UINT16_MAX,\n+\t\t.nb_min = 1,\n+\t\t.nb_align = 1,\n+\t\t.nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX,\n+\t\t.nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX,\n+\t};\n+\n+\tdevinfo->speed_capa = dev->speed_capa;\n+\tdevinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n+\t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;\n+\treturn 0;\n+}\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex e7e43f0..8495732 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -9,6 +9,7 @@ if not dpdk_conf.get('RTE_ARCH_64')\n endif\n \n sources = files('cnxk_ethdev.c',\n+\t\t'cnxk_ethdev_ops.c',\n \t\t'cnxk_ethdev_devargs.c')\n \n # CN9K\n", "prefixes": [ "v4", "12/62" ] }