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GET /api/patches/94706/?format=api
{ "id": 94706, "url": "https://patches.dpdk.org/api/patches/94706/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-11-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-11-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-11-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:10", "name": "[v4,10/62] net/cnxk: add platform specific probe and remove", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "994ac2b210323e4a094d0864f7770406a9fc4ec9", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-11-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94706/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94706/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 889B9A0C41;\n\tWed, 23 Jun 2021 06:48:32 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B72FF4113E;\n\tWed, 23 Jun 2021 06:47:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 018B640E09\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:47:52 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k6Yg025521 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:52 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gjb-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:52 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:49 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:49 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id AA2A05B6937;\n Tue, 22 Jun 2021 21:47:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=uHxG+2qHc3alLeFR/d6AdRV1aRJEQM7NmJpf0yQDe7k=;\n b=Gm1lBUsOc7E/Ozw4ey8wGQgjjeojsSSgpaPh8NgOFB4l7YNR6conYfYlx1u+U1BVmI01\n 6MJP1JGt+Kb0aIlOOW/EUjEa3B/8kQiaSQZu8Wny5Yuv7C3/cJ2xh6t+US5zJ3rflyWd\n M38FHQvz2FTRTlZiQy8JhpudgWW5n6VD7/i0XL153Kcy7BiWrEH9anXc9FGZQpdR0KDW\n JqcjvlVoVOlkII3VznLI9wS2G+W2xw0oKgdhN8YVplXK4bXEB6jZ4R0ECbfjxufeI4rf\n HYIH2PikPxTd4fCqeS66ji/7I9dpYMmHfudgViYZ8yX8FSNEy3laiFGyvYM7SzlMCdDy lQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n \"Nithin Dabilpuram\" <ndabilpuram@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:10 +0530", "Message-ID": "<20210623044702.4240-11-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "-E_2tBjqcIqf0x8v-skVIgBPNdzc5oz0", "X-Proofpoint-GUID": "-E_2tBjqcIqf0x8v-skVIgBPNdzc5oz0", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 10/62] net/cnxk: add platform specific probe\n and remove", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add platform specific probe and remove callbacks for CN9K\nand CN10K which use common probe and remove functions.\nRegister ethdev driver for CN9K and CN10K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/cnxk/cn10k_ethdev.c | 64 ++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cn10k_ethdev.h | 9 +++++\n drivers/net/cnxk/cn9k_ethdev.c | 82 +++++++++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cn9k_ethdev.h | 9 +++++\n drivers/net/cnxk/cnxk_ethdev.c | 42 +++++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.h | 19 ++++++++++\n drivers/net/cnxk/meson.build | 5 +++\n 7 files changed, 230 insertions(+)\n create mode 100644 drivers/net/cnxk/cn10k_ethdev.c\n create mode 100644 drivers/net/cnxk/cn10k_ethdev.h\n create mode 100644 drivers/net/cnxk/cn9k_ethdev.c\n create mode 100644 drivers/net/cnxk/cn9k_ethdev.h", "diff": "diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nnew file mode 100644\nindex 0000000..ff8ce31\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#include \"cn10k_ethdev.h\"\n+\n+static int\n+cn10k_nix_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn cnxk_nix_remove(pci_dev);\n+}\n+\n+static int\n+cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_eth_dev *eth_dev;\n+\tint rc;\n+\n+\tif (RTE_CACHE_LINE_SIZE != 64) {\n+\t\tplt_err(\"Driver not compiled for CN10K\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\trc = roc_plt_init();\n+\tif (rc) {\n+\t\tplt_err(\"Failed to initialize platform model, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Common probe */\n+\trc = cnxk_nix_probe(pci_drv, pci_dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\teth_dev = rte_eth_dev_allocated(pci_dev->device.name);\n+\t\tif (!eth_dev)\n+\t\t\treturn -ENOENT;\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct rte_pci_id cn10k_pci_nix_map[] = {\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct rte_pci_driver cn10k_pci_nix = {\n+\t.id_table = cn10k_pci_nix_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |\n+\t\t RTE_PCI_DRV_INTR_LSC,\n+\t.probe = cn10k_nix_probe,\n+\t.remove = cn10k_nix_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);\n+RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);\n+RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, \"vfio-pci\");\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nnew file mode 100644\nindex 0000000..1bf4a65\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -0,0 +1,9 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CN10K_ETHDEV_H__\n+#define __CN10K_ETHDEV_H__\n+\n+#include <cnxk_ethdev.h>\n+\n+#endif /* __CN10K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nnew file mode 100644\nindex 0000000..98d2d3a\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -0,0 +1,82 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#include \"cn9k_ethdev.h\"\n+\n+static int\n+cn9k_nix_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn cnxk_nix_remove(pci_dev);\n+}\n+\n+static int\n+cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_eth_dev *eth_dev;\n+\tstruct cnxk_eth_dev *dev;\n+\tint rc;\n+\n+\tif (RTE_CACHE_LINE_SIZE != 128) {\n+\t\tplt_err(\"Driver not compiled for CN9K\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\trc = roc_plt_init();\n+\tif (rc) {\n+\t\tplt_err(\"Failed to initialize platform model, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Common probe */\n+\trc = cnxk_nix_probe(pci_drv, pci_dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Find eth dev allocated */\n+\teth_dev = rte_eth_dev_allocated(pci_dev->device.name);\n+\tif (!eth_dev)\n+\t\treturn -ENOENT;\n+\n+\tdev = cnxk_eth_pmd_priv(eth_dev);\n+\t/* Update capabilities already set for TSO.\n+\t * TSO not supported for earlier chip revisions\n+\t */\n+\tif (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())\n+\t\tdev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |\n+\t\t\t\t\t DEV_TX_OFFLOAD_VXLAN_TNL_TSO |\n+\t\t\t\t\t DEV_TX_OFFLOAD_GENEVE_TNL_TSO |\n+\t\t\t\t\t DEV_TX_OFFLOAD_GRE_TNL_TSO);\n+\n+\t/* 50G and 100G to be supported for board version C0\n+\t * and above of CN9K.\n+\t */\n+\tif (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {\n+\t\tdev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;\n+\t\tdev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;\n+\t}\n+\n+\tdev->hwcap = 0;\n+\n+\t/* Update HW erratas */\n+\tif (roc_model_is_cn96_a0() || roc_model_is_cn95_a0())\n+\t\tdev->cq_min_4k = 1;\n+\treturn 0;\n+}\n+\n+static const struct rte_pci_id cn9k_pci_nix_map[] = {\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct rte_pci_driver cn9k_pci_nix = {\n+\t.id_table = cn9k_pci_nix_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |\n+\t\t RTE_PCI_DRV_INTR_LSC,\n+\t.probe = cn9k_nix_probe,\n+\t.remove = cn9k_nix_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);\n+RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);\n+RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, \"vfio-pci\");\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h\nnew file mode 100644\nindex 0000000..15d9397\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_ethdev.h\n@@ -0,0 +1,9 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CN9K_ETHDEV_H__\n+#define __CN9K_ETHDEV_H__\n+\n+#include <cnxk_ethdev.h>\n+\n+#endif /* __CN9K_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 589b0da..526c19b 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -3,6 +3,40 @@\n */\n #include <cnxk_ethdev.h>\n \n+static inline uint64_t\n+nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)\n+{\n+\tuint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;\n+\n+\tif (roc_nix_is_vf_or_sdp(&dev->nix))\n+\t\tcapa &= ~DEV_RX_OFFLOAD_TIMESTAMP;\n+\n+\treturn capa;\n+}\n+\n+static inline uint64_t\n+nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\treturn CNXK_NIX_TX_OFFLOAD_CAPA;\n+}\n+\n+static inline uint32_t\n+nix_get_speed_capa(struct cnxk_eth_dev *dev)\n+{\n+\tuint32_t speed_capa;\n+\n+\t/* Auto negotiation disabled */\n+\tspeed_capa = ETH_LINK_SPEED_FIXED;\n+\tif (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {\n+\t\tspeed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |\n+\t\t\t ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |\n+\t\t\t ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;\n+\t}\n+\n+\treturn speed_capa;\n+}\n+\n /* CNXK platform independent eth dev ops */\n struct eth_dev_ops cnxk_eth_dev_ops;\n \n@@ -76,6 +110,14 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t\t}\n \t}\n \n+\t/* Union of all capabilities supported by CNXK.\n+\t * Platform specific capabilities will be\n+\t * updated later.\n+\t */\n+\tdev->rx_offload_capa = nix_get_rx_offload_capa(dev);\n+\tdev->tx_offload_capa = nix_get_tx_offload_capa(dev);\n+\tdev->speed_capa = nix_get_speed_capa(dev);\n+\n \t/* Initialize roc npc */\n \tplt_nix_dbg(\"Port=%d pf=%d vf=%d ver=%s hwcap=0x%\" PRIx64\n \t\t \" rxoffload_capa=0x%\" PRIx64 \" txoffload_capa=0x%\" PRIx64,\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 0460d1e..ba2bfcd 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -14,6 +14,22 @@\n \n #define CNXK_ETH_DEV_PMD_VERSION \"1.0\"\n \n+#define CNXK_NIX_TX_OFFLOAD_CAPA \\\n+\t(DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \\\n+\t DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \\\n+\t DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \\\n+\t DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \\\n+\t DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \\\n+\t DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \\\n+\t DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \\\n+\t DEV_TX_OFFLOAD_IPV4_CKSUM)\n+\n+#define CNXK_NIX_RX_OFFLOAD_CAPA \\\n+\t(DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \\\n+\t DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \\\n+\t DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \\\n+\t DEV_RX_OFFLOAD_RSS_HASH)\n+\n struct cnxk_eth_dev {\n \t/* ROC NIX */\n \tstruct roc_nix nix;\n@@ -28,6 +44,9 @@ struct cnxk_eth_dev {\n \n \t/* HW capabilities / Limitations */\n \tunion {\n+\t\tstruct {\n+\t\t\tuint64_t cq_min_4k : 1;\n+\t\t};\n \t\tuint64_t hwcap;\n \t};\n \ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 7dd4bca..089e4fc 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -10,5 +10,10 @@ endif\n \n sources = files('cnxk_ethdev.c')\n \n+# CN9K\n+sources += files('cn9k_ethdev.c')\n+# CN10K\n+sources += files('cn10k_ethdev.c')\n+\n deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']\n deps += ['common_cnxk', 'mempool_cnxk']\n", "prefixes": [ "v4", "10/62" ] }