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GET /api/patches/94698/?format=api
{ "id": 94698, "url": "https://patches.dpdk.org/api/patches/94698/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-3-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-3-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-3-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:02", "name": "[v4,02/62] common/cnxk: fix batch alloc completion poll logic", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4e99d277ec8963a04f90c601e84601b97941bfb5", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-3-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94698/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 917D4A0C41;\n\tWed, 23 Jun 2021 06:47:38 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4FD24410EA;\n\tWed, 23 Jun 2021 06:47:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C11EF4069C;\n Wed, 23 Jun 2021 06:47:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4kORp026099; Tue, 22 Jun 2021 21:47:25 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1ggx-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 22 Jun 2021 21:47:25 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:23 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:23 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id DBE535B6938;\n Tue, 22 Jun 2021 21:47:20 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=z1XMpE5sfpnUPPBDDNvjLzhHe7qQkkdWhojDV3Ar18I=;\n b=SzRDtK31Ne/Uu7kU1mmUHtqaT9Q36egIMtf9v+SAlHvEWAOKftHE4CTbrnMMql2Q3lJ8\n 6SX1itUR/v1bypNGVEWfcD1D0iKWKVaWQ99SjXzVJ3csL3u65vF0+XwcpCK0vEEK1215\n wHNyFOi5/8NLepIUPEWCqzU9bXGxG72Yn1gmOs11QWO8oaHWa+kfg+h8JwaFu0Vv0nLh\n ZckGf5/HIsnGh+G7WW5cT4JOlubJWeE9YsGWFXLg1JT1ocq/T3JZ7orA6MSaBRDEQQlf\n owDGxjiMKDXQ2W1eAE8kRXpRQdCfSLIVgRds9yB+iRd619D5F8JYiDxIz7YzukEoN8CD zg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>,\n <stable@dpdk.org>", "Date": "Wed, 23 Jun 2021 10:16:02 +0530", "Message-ID": "<20210623044702.4240-3-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "gkbsuBzPAn9ysVMJAXEozIdX08cXIHlq", "X-Proofpoint-GUID": "gkbsuBzPAn9ysVMJAXEozIdX08cXIHlq", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 02/62] common/cnxk: fix batch alloc completion\n poll logic", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe instruction generation was not correct due to\nfact that volatile suppose to use with ccode variable\nas well.\n\nChange the logic to use gcc atomic builtin to\nsimplify and avoid explicit volatile from the code.\n\nFixes: 81af26789316 (\"common/cnxk: support NPA batch alloc/free\")\nCc: stable@dpdk.org\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/roc_npa.c | 2 +-\n drivers/common/cnxk/roc_npa.h | 30 +++++++++++++++---------------\n 2 files changed, 16 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex f1e03b7..5ba6e81 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -236,7 +236,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \n \t/* Block size should be cache line aligned and in range of 128B-128KB */\n \tif (block_size % ROC_ALIGN || block_size < 128 ||\n-\t block_size > 128 * 1024)\n+\t block_size > ROC_NPA_MAX_BLOCK_SZ)\n \t\treturn NPA_ERR_INVALID_BLOCK_SZ;\n \n \tpos = 0;\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex 89f5c6f..59d6223 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -8,6 +8,7 @@\n #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1)\n #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)\n \n+#define ROC_NPA_MAX_BLOCK_SZ\t\t (128 * 1024)\n #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512\n #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15\n \n@@ -219,6 +220,17 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,\n \treturn 0;\n }\n \n+static inline void\n+roc_npa_batch_alloc_wait(uint64_t *cache_line)\n+{\n+\t/* Batch alloc status code is updated in bits [5:6] of the first word\n+\t * of the 128 byte cache line.\n+\t */\n+\twhile (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x3) ==\n+\t ALLOC_CCODE_INVAL)\n+\t\t;\n+}\n+\n static inline unsigned int\n roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num)\n {\n@@ -231,17 +243,10 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num)\n \t/* Check each ROC cache line one by one */\n \tfor (i = 0; i < num; i += (ROC_ALIGN >> 3)) {\n \t\tstruct npa_batch_alloc_status_s *status;\n-\t\tint ccode;\n \n \t\tstatus = (struct npa_batch_alloc_status_s *)&aligned_buf[i];\n \n-\t\t/* Status is updated in first 7 bits of each 128 byte cache\n-\t\t * line. Wait until the status gets updated.\n-\t\t */\n-\t\tdo {\n-\t\t\tccode = (volatile int)status->ccode;\n-\t\t} while (ccode == ALLOC_CCODE_INVAL);\n-\n+\t\troc_npa_batch_alloc_wait(&aligned_buf[i]);\n \t\tcount += status->count;\n \t}\n \n@@ -261,16 +266,11 @@ roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf,\n \t/* Check each ROC cache line one by one */\n \tfor (i = 0; i < num; i += (ROC_ALIGN >> 3)) {\n \t\tstruct npa_batch_alloc_status_s *status;\n-\t\tint line_count, ccode;\n+\t\tint line_count;\n \n \t\tstatus = (struct npa_batch_alloc_status_s *)&aligned_buf[i];\n \n-\t\t/* Status is updated in first 7 bits of each 128 byte cache\n-\t\t * line. Wait until the status gets updated.\n-\t\t */\n-\t\tdo {\n-\t\t\tccode = (volatile int)status->ccode;\n-\t\t} while (ccode == ALLOC_CCODE_INVAL);\n+\t\troc_npa_batch_alloc_wait(&aligned_buf[i]);\n \n \t\tline_count = status->count;\n \n", "prefixes": [ "v4", "02/62" ] }