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GET /api/patches/94697/?format=api
{ "id": 94697, "url": "https://patches.dpdk.org/api/patches/94697/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-2-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210623044702.4240-2-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210623044702.4240-2-ndabilpuram@marvell.com", "date": "2021-06-23T04:46:01", "name": "[v4,01/62] common/cnxk: add support to lock NIX RQ contexts", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6178b220b4f790790044fbfc051b3b15562a2ff3", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623044702.4240-2-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 17449, "url": "https://patches.dpdk.org/api/series/17449/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17449", "date": "2021-06-23T04:46:00", "name": "Marvell CNXK Ethdev Driver", "version": 4, "mbox": "https://patches.dpdk.org/series/17449/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94697/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94697/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 718AFA0C41;\n\tWed, 23 Jun 2021 06:47:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C5A4B406A3;\n\tWed, 23 Jun 2021 06:47:25 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 8139C4067A\n for <dev@dpdk.org>; Wed, 23 Jun 2021 06:47:23 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15N4k6fI025518 for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:22 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1ggv-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 22 Jun 2021 21:47:22 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 21:47:20 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 21:47:20 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id BBE985B6936;\n Tue, 22 Jun 2021 21:47:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=ZcOtloOcbJVvU3JUsaAbHubj9+kpC+o/WmWdMZavXyA=;\n b=UvKmMMZsMmEvUDyn99bLY86dOUJvGsTBQKX1eTD+7WqjGCCUVf4qhcdltEXAGfl1K2Bk\n tlNbZmwCVfYQP3dZpC2oCjrBvRf9SkhOjE+IAqpH9MBtzAaUbjYDj2l/f508VFv3ztsx\n rvFZzaw9zEkKesw97Vw5dSsXv7YPpWPrpNECOTT6bDG2BthPvL8EXCoJzYYvSGiR9tuE\n 564bNzFFVTf6jlQscwFw1O+8Bz2y0o0I9y8+gpUKmNXVKuMJHpxDqSEnM+49GOFTpMgy\n JP6Wfsv5ViW8ohcpOaXErtHTZnCwTy5Nh3uDixe/JjLnwkJP6J9mcm5o231YTSX8GcDF TA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, <hkalra@marvell.com>", "Date": "Wed, 23 Jun 2021 10:16:01 +0530", "Message-ID": "<20210623044702.4240-2-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210623044702.4240-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>\n <20210623044702.4240-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "aCx9iNVOPe7lp0Qbik0GDP41pHUQ1-9_", "X-Proofpoint-GUID": "aCx9iNVOPe7lp0Qbik0GDP41pHUQ1-9_", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-23_01:2021-06-22,\n 2021-06-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 01/62] common/cnxk: add support to lock NIX RQ\n contexts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nThis patch will consider device argument to lock rss table\nin NIX.\n\nThis patch also adds few misc fixes such as disabling NIX Tx\nvlan insertion conf in SMQ, enabling SSO in NIX Tx SQ\nfor Tx completions and TM related stats API.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 31 ++++++++++--\n drivers/common/cnxk/roc_nix_queue.c | 2 +\n drivers/common/cnxk/roc_nix_rss.c | 51 ++++++++++++++++++--\n drivers/common/cnxk/roc_nix_tm_utils.c | 86 +++++++++++++++++++++++++++++++++-\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/version.map | 1 +\n 6 files changed, 163 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex b39f461..6d9ac10 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -85,10 +85,11 @@ struct roc_nix_eeprom_info {\n #define ROC_NIX_LF_RX_CFG_LEN_OL3 BIT_ULL(41)\n \n /* Group 0 will be used for RSS, 1 -7 will be used for npc_flow RSS action*/\n-#define ROC_NIX_RSS_GROUP_DEFAULT 0\n-#define ROC_NIX_RSS_GRPS\t 8\n-#define ROC_NIX_RSS_RETA_MAX\t ROC_NIX_RSS_RETA_SZ_256\n-#define ROC_NIX_RSS_KEY_LEN\t 48 /* 352 Bits */\n+#define ROC_NIX_RSS_GROUP_DEFAULT 0\n+#define ROC_NIX_RSS_GRPS\t 8\n+#define ROC_NIX_RSS_RETA_MAX\t ROC_NIX_RSS_RETA_SZ_256\n+#define ROC_NIX_RSS_KEY_LEN\t 48 /* 352 Bits */\n+#define ROC_NIX_RSS_MCAM_IDX_DEFAULT (-1)\n \n #define ROC_NIX_DEFAULT_HW_FRS 1514\n \n@@ -184,6 +185,7 @@ struct roc_nix_sq {\n \tenum roc_nix_sq_max_sqe_sz max_sqe_sz;\n \tuint32_t nb_desc;\n \tuint16_t qid;\n+\tbool sso_ena;\n \t/* End of Input parameters */\n \tuint16_t sqes_per_sqb_log2;\n \tstruct roc_nix *roc_nix;\n@@ -241,6 +243,8 @@ struct roc_nix {\n \tuint16_t max_sqb_count;\n \tenum roc_nix_rss_reta_sz reta_sz;\n \tbool enable_loop;\n+\tbool hw_vlan_ins;\n+\tuint8_t lock_rx_ctx;\n \t/* End of input parameters */\n \t/* LMT line base for \"Per Core Tx LMT line\" mode*/\n \tuintptr_t lmt_base;\n@@ -371,6 +375,22 @@ struct roc_nix_tm_shaper_profile {\n \tvoid (*free_fn)(void *profile);\n };\n \n+enum roc_nix_tm_node_stats_type {\n+\tROC_NIX_TM_NODE_PKTS_DROPPED,\n+\tROC_NIX_TM_NODE_BYTES_DROPPED,\n+\tROC_NIX_TM_NODE_GREEN_PKTS,\n+\tROC_NIX_TM_NODE_GREEN_BYTES,\n+\tROC_NIX_TM_NODE_YELLOW_PKTS,\n+\tROC_NIX_TM_NODE_YELLOW_BYTES,\n+\tROC_NIX_TM_NODE_RED_PKTS,\n+\tROC_NIX_TM_NODE_RED_BYTES,\n+\tROC_NIX_TM_NODE_STATS_MAX,\n+};\n+\n+struct roc_nix_tm_node_stats {\n+\tuint64_t stats[ROC_NIX_TM_NODE_STATS_MAX];\n+};\n+\n int __roc_api roc_nix_tm_node_add(struct roc_nix *roc_nix,\n \t\t\t\t struct roc_nix_tm_node *roc_node);\n int __roc_api roc_nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n@@ -408,6 +428,9 @@ roc_nix_tm_shaper_profile_get(struct roc_nix *roc_nix, uint32_t profile_id);\n struct roc_nix_tm_shaper_profile *__roc_api roc_nix_tm_shaper_profile_next(\n \tstruct roc_nix *roc_nix, struct roc_nix_tm_shaper_profile *__prev);\n \n+int __roc_api roc_nix_tm_node_stats_get(struct roc_nix *roc_nix,\n+\t\t\t\t\tuint32_t node_id, bool clear,\n+\t\t\t\t\tstruct roc_nix_tm_node_stats *stats);\n /*\n * TM ratelimit tree API.\n */\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex fbf7efa..1c62aa2 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -582,6 +582,7 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \taq->sq.default_chan = nix->tx_chan_base;\n \taq->sq.sqe_stype = NIX_STYPE_STF;\n \taq->sq.ena = 1;\n+\taq->sq.sso_ena = !!sq->sso_ena;\n \tif (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)\n \t\taq->sq.sqe_stype = NIX_STYPE_STP;\n \taq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);\n@@ -679,6 +680,7 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \taq->sq.default_chan = nix->tx_chan_base;\n \taq->sq.sqe_stype = NIX_STYPE_STF;\n \taq->sq.ena = 1;\n+\taq->sq.sso_ena = !!sq->sso_ena;\n \tif (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)\n \t\taq->sq.sqe_stype = NIX_STYPE_STP;\n \taq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);\ndiff --git a/drivers/common/cnxk/roc_nix_rss.c b/drivers/common/cnxk/roc_nix_rss.c\nindex 2d7b84a..7de69aa 100644\n--- a/drivers/common/cnxk/roc_nix_rss.c\n+++ b/drivers/common/cnxk/roc_nix_rss.c\n@@ -52,7 +52,7 @@ roc_nix_rss_key_get(struct roc_nix *roc_nix, uint8_t key[ROC_NIX_RSS_KEY_LEN])\n \n static int\n nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n-\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX])\n+\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX], uint8_t lock_rx_ctx)\n {\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n \tstruct nix_aq_enq_req *req;\n@@ -77,6 +77,27 @@ nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n \t\treq->qidx = (group * nix->reta_sz) + idx;\n \t\treq->ctype = NIX_AQ_CTYPE_RSS;\n \t\treq->op = NIX_AQ_INSTOP_INIT;\n+\n+\t\tif (!lock_rx_ctx)\n+\t\t\tcontinue;\n+\n+\t\treq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!req) {\n+\t\t\t/* The shared memory buffer can be full.\n+\t\t\t * Flush it and retry\n+\t\t\t */\n+\t\t\trc = mbox_process(mbox);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\t\t\treq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\t\tif (!req)\n+\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t}\n+\t\treq->rss.rq = reta[idx];\n+\t\t/* Fill AQ info */\n+\t\treq->qidx = (group * nix->reta_sz) + idx;\n+\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n+\t\treq->op = NIX_AQ_INSTOP_LOCK;\n \t}\n \n \trc = mbox_process(mbox);\n@@ -88,7 +109,7 @@ nix_cn9k_rss_reta_set(struct nix *nix, uint8_t group,\n \n static int\n nix_rss_reta_set(struct nix *nix, uint8_t group,\n-\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX])\n+\t\t uint16_t reta[ROC_NIX_RSS_RETA_MAX], uint8_t lock_rx_ctx)\n {\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n \tstruct nix_cn10k_aq_enq_req *req;\n@@ -113,6 +134,27 @@ nix_rss_reta_set(struct nix *nix, uint8_t group,\n \t\treq->qidx = (group * nix->reta_sz) + idx;\n \t\treq->ctype = NIX_AQ_CTYPE_RSS;\n \t\treq->op = NIX_AQ_INSTOP_INIT;\n+\n+\t\tif (!lock_rx_ctx)\n+\t\t\tcontinue;\n+\n+\t\treq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!req) {\n+\t\t\t/* The shared memory buffer can be full.\n+\t\t\t * Flush it and retry\n+\t\t\t */\n+\t\t\trc = mbox_process(mbox);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\t\t\treq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\t\tif (!req)\n+\t\t\t\treturn NIX_ERR_NO_MEM;\n+\t\t}\n+\t\treq->rss.rq = reta[idx];\n+\t\t/* Fill AQ info */\n+\t\treq->qidx = (group * nix->reta_sz) + idx;\n+\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n+\t\treq->op = NIX_AQ_INSTOP_LOCK;\n \t}\n \n \trc = mbox_process(mbox);\n@@ -133,9 +175,10 @@ roc_nix_rss_reta_set(struct roc_nix *roc_nix, uint8_t group,\n \t\treturn NIX_ERR_PARAM;\n \n \tif (roc_model_is_cn9k())\n-\t\trc = nix_cn9k_rss_reta_set(nix, group, reta);\n+\t\trc = nix_cn9k_rss_reta_set(nix, group, reta,\n+\t\t\t\t\t roc_nix->lock_rx_ctx);\n \telse\n-\t\trc = nix_rss_reta_set(nix, group, reta);\n+\t\trc = nix_rss_reta_set(nix, group, reta, roc_nix->lock_rx_ctx);\n \tif (rc)\n \t\treturn rc;\n \ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex 1d7dd68..6b9543e 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -409,6 +409,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t\t\t volatile uint64_t *reg, volatile uint64_t *regval,\n \t\t\t volatile uint64_t *regval_mask)\n {\n+\tstruct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);\n \tuint8_t k = 0, hw_lvl, parent_lvl;\n \tuint64_t parent = 0, child = 0;\n \tenum roc_nix_tm_tree tree;\n@@ -454,8 +455,11 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t\treg[k] = NIX_AF_SMQX_CFG(schq);\n \t\tregval[k] = (BIT_ULL(50) | NIX_MIN_HW_FRS |\n \t\t\t ((nix->mtu & 0xFFFF) << 8));\n-\t\tregval_mask[k] =\n-\t\t\t~(BIT_ULL(50) | GENMASK_ULL(6, 0) | GENMASK_ULL(23, 8));\n+\t\t/* Maximum Vtag insertion size as a multiple of four bytes */\n+\t\tif (roc_nix->hw_vlan_ins)\n+\t\t\tregval[k] |= (0x2ULL << 36);\n+\t\tregval_mask[k] = ~(BIT_ULL(50) | GENMASK_ULL(6, 0) |\n+\t\t\t\t GENMASK_ULL(23, 8) | GENMASK_ULL(38, 36));\n \t\tk++;\n \n \t\t/* Parent and schedule conf */\n@@ -1000,3 +1004,81 @@ nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile)\n \n \t(profile->free_fn)(profile);\n }\n+\n+int\n+roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, uint32_t node_id, bool clear,\n+\t\t\t struct roc_nix_tm_node_stats *n_stats)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txschq_config *req, *rsp;\n+\tstruct nix_tm_node *node;\n+\tuint32_t schq;\n+\tint rc, i;\n+\n+\tnode = nix_tm_node_search(nix, node_id, ROC_NIX_TM_USER);\n+\tif (!node)\n+\t\treturn NIX_ERR_TM_INVALID_NODE;\n+\n+\tif (node->hw_lvl != NIX_TXSCH_LVL_TL1)\n+\t\treturn NIX_ERR_OP_NOTSUP;\n+\n+\tschq = node->hw_id;\n+\t/* Skip fetch if not requested */\n+\tif (!n_stats)\n+\t\tgoto clear_stats;\n+\n+\tmemset(n_stats, 0, sizeof(struct roc_nix_tm_node_stats));\n+\t/* Check if node has HW resource */\n+\tif (!(node->flags & NIX_TM_NODE_HWRES))\n+\t\treturn 0;\n+\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->read = 1;\n+\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\n+\ti = 0;\n+\treq->reg[i++] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_DROPPED_BYTES(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_GREEN_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_GREEN_BYTES(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_YELLOW_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_YELLOW_BYTES(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_RED_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_RED_BYTES(schq);\n+\treq->num_regs = i;\n+\n+\trc = mbox_process_msg(mbox, (void **)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Return stats */\n+\tn_stats->stats[ROC_NIX_TM_NODE_PKTS_DROPPED] = rsp->regval[0];\n+\tn_stats->stats[ROC_NIX_TM_NODE_BYTES_DROPPED] = rsp->regval[1];\n+\tn_stats->stats[ROC_NIX_TM_NODE_GREEN_PKTS] = rsp->regval[2];\n+\tn_stats->stats[ROC_NIX_TM_NODE_GREEN_BYTES] = rsp->regval[3];\n+\tn_stats->stats[ROC_NIX_TM_NODE_YELLOW_PKTS] = rsp->regval[4];\n+\tn_stats->stats[ROC_NIX_TM_NODE_YELLOW_BYTES] = rsp->regval[5];\n+\tn_stats->stats[ROC_NIX_TM_NODE_RED_PKTS] = rsp->regval[6];\n+\tn_stats->stats[ROC_NIX_TM_NODE_RED_BYTES] = rsp->regval[7];\n+\n+clear_stats:\n+\tif (!clear)\n+\t\treturn 0;\n+\n+\t/* Clear all the stats */\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\ti = 0;\n+\treq->reg[i++] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_DROPPED_BYTES(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_GREEN_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_GREEN_BYTES(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_YELLOW_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_YELLOW_BYTES(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_RED_PACKETS(schq);\n+\treq->reg[i++] = NIX_AF_TL1X_RED_BYTES(schq);\n+\treq->num_regs = i;\n+\n+\treturn mbox_process_msg(mbox, (void **)&rsp);\n+}\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 7864fa4..911ae15 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -127,6 +127,8 @@\n #define plt_memzone_reserve_cache_align(name, sz) \\\n \trte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE)\n #define plt_memzone_free rte_memzone_free\n+#define plt_memzone_reserve_aligned(name, len, flags, align) \\\n+\trte_memzone_reserve_aligned((name), (len), 0, (flags), (align))\n \n #define plt_tsc_hz rte_get_tsc_hz\n #define plt_delay_ms rte_delay_ms\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 8e67c83..c39d76f 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -123,6 +123,7 @@ INTERNAL {\n \troc_nix_tm_node_parent_update;\n \troc_nix_tm_node_pkt_mode_update;\n \troc_nix_tm_node_shaper_update;\n+\troc_nix_tm_node_stats_get;\n \troc_nix_tm_node_suspend_resume;\n \troc_nix_tm_prealloc_res;\n \troc_nix_tm_rlimit_sq;\n", "prefixes": [ "v4", "01/62" ] }