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{
    "id": 94694,
    "url": "https://patches.dpdk.org/api/patches/94694/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210623035541.50543-2-richael.zhuang@arm.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210623035541.50543-2-richael.zhuang@arm.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210623035541.50543-2-richael.zhuang@arm.com",
    "date": "2021-06-23T03:55:40",
    "name": "[v4,1/2] power: add support for cppc cpufreq",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7a6f1cb9139f54fa05de1be9237f41fe5889d92d",
    "submitter": {
        "id": 2178,
        "url": "https://patches.dpdk.org/api/people/2178/?format=api",
        "name": "Richael Zhuang",
        "email": "richael.zhuang@arm.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210623035541.50543-2-richael.zhuang@arm.com/mbox/",
    "series": [
        {
            "id": 17448,
            "url": "https://patches.dpdk.org/api/series/17448/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17448",
            "date": "2021-06-23T03:55:39",
            "name": "power: add support for cppc cpufreq driver",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/17448/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/94694/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/94694/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5032A0C41;\n\tWed, 23 Jun 2021 05:56:03 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 09B884069C;\n\tWed, 23 Jun 2021 05:56:03 +0200 (CEST)",
            "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id 4643040687\n for <dev@dpdk.org>; Wed, 23 Jun 2021 05:56:01 +0200 (CEST)",
            "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A3E2D31B;\n Tue, 22 Jun 2021 20:56:00 -0700 (PDT)",
            "from wls-arm-cavium06.shanghai.arm.com\n (wls-arm-cavium06.shanghai.arm.com [10.169.206.120])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D02823F694;\n Tue, 22 Jun 2021 20:55:58 -0700 (PDT)"
        ],
        "From": "Richael Zhuang <richael.zhuang@arm.com>",
        "To": "dev@dpdk.org",
        "Cc": "yux.jiang@intel.com,\n\tDavid Hunt <david.hunt@intel.com>",
        "Date": "Wed, 23 Jun 2021 11:55:40 +0800",
        "Message-Id": "<20210623035541.50543-2-richael.zhuang@arm.com>",
        "X-Mailer": "git-send-email 2.20.1",
        "In-Reply-To": "<20210623035541.50543-1-richael.zhuang@arm.com>",
        "References": "<20210512035709.37755-2-richael.zhuang@arm.com>\n <20210623035541.50543-1-richael.zhuang@arm.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v4 1/2] power: add support for cppc cpufreq",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Currently in DPDK only acpi_cpufreq and pstate_cpufreq drivers are\nsupported, which are both not available on arm64 platforms. Add\nsupport for cppc_cpufreq driver which works on most arm64 platforms.\n\nSigned-off-by: Richael Zhuang <richael.zhuang@arm.com>\n---\n app/test/test_power.c          |   3 +-\n app/test/test_power_cpufreq.c  |   3 +-\n lib/power/meson.build          |   1 +\n lib/power/power_cppc_cpufreq.c | 632 +++++++++++++++++++++++++++++++++\n lib/power/power_cppc_cpufreq.h | 229 ++++++++++++\n lib/power/rte_power.c          |  26 ++\n lib/power/rte_power.h          |   2 +-\n 7 files changed, 893 insertions(+), 3 deletions(-)\n create mode 100644 lib/power/power_cppc_cpufreq.c\n create mode 100644 lib/power/power_cppc_cpufreq.h",
    "diff": "diff --git a/app/test/test_power.c b/app/test/test_power.c\nindex da1d67c0a..b7b556134 100644\n--- a/app/test/test_power.c\n+++ b/app/test/test_power.c\n@@ -133,7 +133,8 @@ test_power(void)\n \t/* Perform tests for valid environments.*/\n \tconst enum power_management_env envs[] = {PM_ENV_ACPI_CPUFREQ,\n \t\t\tPM_ENV_KVM_VM,\n-\t\t\tPM_ENV_PSTATE_CPUFREQ};\n+\t\t\tPM_ENV_PSTATE_CPUFREQ,\n+\t\t\tPM_ENV_CPPC_CPUFREQ};\n \n \tunsigned int i;\n \tfor (i = 0; i < RTE_DIM(envs); ++i) {\ndiff --git a/app/test/test_power_cpufreq.c b/app/test/test_power_cpufreq.c\nindex 0c3adc5f3..8516df4ca 100644\n--- a/app/test/test_power_cpufreq.c\n+++ b/app/test/test_power_cpufreq.c\n@@ -496,7 +496,8 @@ test_power_cpufreq(void)\n \n \t/* Test environment configuration */\n \tenv = rte_power_get_env();\n-\tif ((env != PM_ENV_ACPI_CPUFREQ) && (env != PM_ENV_PSTATE_CPUFREQ)) {\n+\tif ((env != PM_ENV_ACPI_CPUFREQ) && (env != PM_ENV_PSTATE_CPUFREQ) &&\n+\t\t\t(env != PM_ENV_CPPC_CPUFREQ)) {\n \t\tprintf(\"Unexpectedly got an environment other than ACPI/PSTATE\\n\");\n \t\tgoto fail_all;\n \t}\ndiff --git a/lib/power/meson.build b/lib/power/meson.build\nindex 74c5f3a29..4a5b07292 100644\n--- a/lib/power/meson.build\n+++ b/lib/power/meson.build\n@@ -21,6 +21,7 @@ sources = files(\n         'rte_power.c',\n         'rte_power_empty_poll.c',\n         'rte_power_pmd_mgmt.c',\n+\t'power_cppc_cpufreq.c',\n )\n headers = files(\n         'rte_power.h',\ndiff --git a/lib/power/power_cppc_cpufreq.c b/lib/power/power_cppc_cpufreq.c\nnew file mode 100644\nindex 000000000..fd4483e52\n--- /dev/null\n+++ b/lib/power/power_cppc_cpufreq.c\n@@ -0,0 +1,632 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Arm Limited\n+ */\n+\n+#include <rte_memcpy.h>\n+#include <rte_memory.h>\n+\n+#include \"power_cppc_cpufreq.h\"\n+#include \"power_common.h\"\n+\n+/* macros used for rounding frequency to nearest 100000 */\n+#define FREQ_ROUNDING_DELTA 50000\n+#define ROUND_FREQ_TO_N_100000 100000\n+\n+/* the unit of highest_perf and nominal_perf differs on different arm platforms.\n+ * For highest_perf, it maybe 300 or 3000000, both means 3.0GHz.\n+ */\n+#define UNIT_DIFF 10000\n+\n+#define POWER_CONVERT_TO_DECIMAL 10\n+\n+#define POWER_GOVERNOR_USERSPACE \"userspace\"\n+#define POWER_SYSFILE_SETSPEED   \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_setspeed\"\n+#define POWER_SYSFILE_SCALING_MAX_FREQ \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_max_freq\"\n+#define POWER_SYSFILE_SCALING_MIN_FREQ  \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_min_freq\"\n+#define POWER_SYSFILE_HIGHEST_PERF \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/acpi_cppc/highest_perf\"\n+#define POWER_SYSFILE_NOMINAL_PERF \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/acpi_cppc/nominal_perf\"\n+#define POWER_SYSFILE_SYS_MAX \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/cpuinfo_max_freq\"\n+\n+#define POWER_CPPC_DRIVER \"cppc-cpufreq\"\n+#define BUS_FREQ     100000\n+\n+enum power_state {\n+\tPOWER_IDLE = 0,\n+\tPOWER_ONGOING,\n+\tPOWER_USED,\n+\tPOWER_UNKNOWN\n+};\n+\n+/**\n+ * Power info per lcore.\n+ */\n+struct cppc_power_info {\n+\tunsigned int lcore_id;                   /**< Logical core id */\n+\tuint32_t state;                      /**< Power in use state */\n+\tFILE *f;                             /**< FD of scaling_setspeed */\n+\tchar governor_ori[32];               /**< Original governor name */\n+\tuint32_t curr_idx;                   /**< Freq index in freqs array */\n+\tuint32_t highest_perf;\t\t     /**< system wide max freq */\n+\tuint32_t nominal_perf;\t\t     /**< system wide nominal freq */\n+\tuint16_t turbo_available;            /**< Turbo Boost available */\n+\tuint16_t turbo_enable;               /**< Turbo Boost enable/disable */\n+\tuint32_t nb_freqs;                   /**< number of available freqs */\n+\tuint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */\n+} __rte_cache_aligned;\n+\n+static struct cppc_power_info lcore_power_info[RTE_MAX_LCORE];\n+\n+/**\n+ * It is to set specific freq for specific logical core, according to the index\n+ * of supported frequencies.\n+ */\n+static int\n+set_freq_internal(struct cppc_power_info *pi, uint32_t idx)\n+{\n+\tif (idx >= RTE_MAX_LCORE_FREQS || idx >= pi->nb_freqs) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid frequency index %u, which \"\n+\t\t\t\t\"should be less than %u\\n\", idx, pi->nb_freqs);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Check if it is the same as current */\n+\tif (idx == pi->curr_idx)\n+\t\treturn 0;\n+\n+\tPOWER_DEBUG_TRACE(\"Frequency[%u] %u to be set for lcore %u\\n\",\n+\t\t\tidx, pi->freqs[idx], pi->lcore_id);\n+\tif (fseek(pi->f, 0, SEEK_SET) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Fail to set file position indicator to 0 \"\n+\t\t\t\"for setting frequency for lcore %u\\n\", pi->lcore_id);\n+\t\treturn -1;\n+\t}\n+\tif (fprintf(pi->f, \"%u\", pi->freqs[idx]) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Fail to write new frequency for \"\n+\t\t\t\t\"lcore %u\\n\", pi->lcore_id);\n+\t\treturn -1;\n+\t}\n+\tfflush(pi->f);\n+\tpi->curr_idx = idx;\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * It is to check the current scaling governor by reading sys file, and then\n+ * set it into 'userspace' if it is not by writing the sys file. The original\n+ * governor will be saved for rolling back.\n+ */\n+static int\n+power_set_governor_userspace(struct cppc_power_info *pi)\n+{\n+\treturn power_set_governor(pi->lcore_id, POWER_GOVERNOR_USERSPACE,\n+\t\t\tpi->governor_ori, sizeof(pi->governor_ori));\n+}\n+\n+static int\n+power_check_turbo(struct cppc_power_info *pi)\n+{\n+\tFILE *f_nom, *f_max, *f_cmax;\n+\tint ret = -1;\n+\tuint32_t nominal_perf = 0, highest_perf = 0, cpuinfo_max_freq = 0;\n+\n+\topen_core_sysfs_file(POWER_SYSFILE_HIGHEST_PERF, pi->lcore_id, \"r\",\n+\t\t\t&f_max);\n+\tFOPEN_OR_ERR_GOTO(f_max, err);\n+\n+\topen_core_sysfs_file(POWER_SYSFILE_NOMINAL_PERF, pi->lcore_id, \"r\",\n+\t\t\t&f_nom);\n+\tFOPEN_OR_ERR_GOTO(f_nom, err);\n+\n+\topen_core_sysfs_file(POWER_SYSFILE_SYS_MAX, pi->lcore_id, \"r\",\n+\t\t\t&f_cmax);\n+\tFOPEN_OR_ERR_GOTO(f_cmax, err);\n+\n+\tret = read_core_sysfs_u32(f_max, &highest_perf);\n+\tFOPS_OR_ERR_GOTO(ret, err);\n+\n+\tret = read_core_sysfs_u32(f_nom, &nominal_perf);\n+\tFOPS_OR_ERR_GOTO(ret, err);\n+\n+\tret = read_core_sysfs_u32(f_cmax, &cpuinfo_max_freq);\n+\tFOPS_OR_ERR_GOTO(ret, err);\n+\n+\tpi->highest_perf = highest_perf;\n+\tpi->nominal_perf = nominal_perf;\n+\n+\tif ((highest_perf > nominal_perf) && ((cpuinfo_max_freq == highest_perf) ||\n+\t\t\t\tcpuinfo_max_freq == highest_perf * UNIT_DIFF)) {\n+\t\tpi->turbo_available = 1;\n+\t\tpi->turbo_enable = 1;\n+\t\tret = 0;\n+\t\tPOWER_DEBUG_TRACE(\"Lcore %u can do Turbo Boost! highest perf %u, \"\n+\t\t\t\t\"nominal perf %u\\n\",\n+\t\t\t\tpi->lcore_id, highest_perf, nominal_perf);\n+\t} else {\n+\t\tpi->turbo_available = 0;\n+\t\tpi->turbo_enable = 0;\n+\t\tPOWER_DEBUG_TRACE(\"Lcore %u Turbo not available! highest perf %u, \"\n+\t\t\t\t\"nominal perf %u\\n\",\n+\t\t\t\tpi->lcore_id, highest_perf, nominal_perf);\n+\t}\n+\n+err:\n+\tif (f_max != NULL)\n+\t\tfclose(f_max);\n+\tif (f_nom != NULL)\n+\t\tfclose(f_nom);\n+\tif (f_cmax != NULL)\n+\t\tfclose(f_cmax);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * It is to get the available frequencies of the specific lcore by reading the\n+ * sys file.\n+ */\n+static int\n+power_get_available_freqs(struct cppc_power_info *pi)\n+{\n+\tFILE *f_min, *f_max;\n+\tint ret = -1;\n+\tuint32_t scaling_min_freq = 0, scaling_max_freq = 0, nominal_perf = 0;\n+\tuint32_t i, num_freqs = 0;\n+\n+\topen_core_sysfs_file(POWER_SYSFILE_SCALING_MAX_FREQ, pi->lcore_id, \"r\",\n+\t\t\t&f_max);\n+\tFOPEN_OR_ERR_GOTO(f_max, out);\n+\n+\topen_core_sysfs_file(POWER_SYSFILE_SCALING_MIN_FREQ, pi->lcore_id, \"r\",\n+\t\t\t&f_min);\n+\tFOPEN_OR_ERR_GOTO(f_min, out);\n+\n+\tret = read_core_sysfs_u32(f_max, &scaling_max_freq);\n+\tFOPS_OR_ERR_GOTO(ret, out);\n+\n+\tret = read_core_sysfs_u32(f_min, &scaling_min_freq);\n+\tFOPS_OR_ERR_GOTO(ret, out);\n+\n+\tpower_check_turbo(pi);\n+\n+\tif (scaling_max_freq < scaling_min_freq)\n+\t\tgoto out;\n+\n+\t/* If turbo is available then there is one extra freq bucket\n+\t * to store the sys max freq which value is scaling_max_freq\n+\t */\n+\tnominal_perf = (pi->nominal_perf < UNIT_DIFF) ?\n+\t\t\tpi->nominal_perf * UNIT_DIFF : pi->nominal_perf;\n+\tnum_freqs = (nominal_perf - scaling_min_freq) / BUS_FREQ + 1 +\n+\t\tpi->turbo_available;\n+\n+\t/* Generate the freq bucket array. */\n+\tfor (i = 0, pi->nb_freqs = 0; i < num_freqs; i++) {\n+\t\tif ((i == 0) && pi->turbo_available)\n+\t\t\tpi->freqs[pi->nb_freqs++] = scaling_max_freq;\n+\t\telse\n+\t\t\tpi->freqs[pi->nb_freqs++] =\n+\t\t\tnominal_perf - (i - pi->turbo_available) * BUS_FREQ;\n+\t}\n+\n+\tret = 0;\n+\n+\tPOWER_DEBUG_TRACE(\"%d frequency(s) of lcore %u are available\\n\",\n+\t\t\tnum_freqs, pi->lcore_id);\n+\n+out:\n+\tif (f_min != NULL)\n+\t\tfclose(f_min);\n+\tif (f_max != NULL)\n+\t\tfclose(f_max);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * It is to fopen the sys file for the future setting the lcore frequency.\n+ */\n+static int\n+power_init_for_setting_freq(struct cppc_power_info *pi)\n+{\n+\tFILE *f;\n+\tchar buf[BUFSIZ];\n+\tuint32_t i, freq;\n+\tint ret;\n+\n+\topen_core_sysfs_file(POWER_SYSFILE_SETSPEED, pi->lcore_id, \"rw+\",\n+\t\t\t&f);\n+\tFOPEN_OR_ERR_GOTO(f, err);\n+\n+\tret = read_core_sysfs_s(f, buf, sizeof(buf));\n+\tFOPS_OR_ERR_GOTO(ret, err);\n+\n+\tfreq = strtoul(buf, NULL, POWER_CONVERT_TO_DECIMAL);\n+\n+\t/* convert the frequency to nearest 100000 value\n+\t * Ex: if freq=1396789 then freq_conv=1400000\n+\t * Ex: if freq=800030 then freq_conv=800000\n+\t */\n+\tunsigned int freq_conv = 0;\n+\tfreq_conv = (freq + FREQ_ROUNDING_DELTA)\n+\t\t\t\t/ ROUND_FREQ_TO_N_100000;\n+\tfreq_conv = freq_conv * ROUND_FREQ_TO_N_100000;\n+\n+\tfor (i = 0; i < pi->nb_freqs; i++) {\n+\t\tif (freq_conv == pi->freqs[i]) {\n+\t\t\tpi->curr_idx = i;\n+\t\t\tpi->f = f;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+err:\n+\tif (f != NULL)\n+\t\tfclose(f);\n+\n+\treturn -1;\n+}\n+\n+int\n+power_cppc_cpufreq_check_supported(void)\n+{\n+\treturn cpufreq_check_scaling_driver(POWER_CPPC_DRIVER);\n+}\n+\n+int\n+power_cppc_cpufreq_init(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\tuint32_t exp_state;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n+\t\t\t\tlcore_id, RTE_MAX_LCORE - 1U);\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\texp_state = POWER_IDLE;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n+\t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n+\t\t\t\t\"in use\\n\", lcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\tpi->lcore_id = lcore_id;\n+\t/* Check and set the governor */\n+\tif (power_set_governor_userspace(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot set governor of lcore %u to \"\n+\t\t\t\t\"userspace\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Get the available frequencies */\n+\tif (power_get_available_freqs(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot get available frequencies of \"\n+\t\t\t\t\"lcore %u\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Init for setting lcore frequency */\n+\tif (power_init_for_setting_freq(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot init for setting frequency for \"\n+\t\t\t\t\"lcore %u\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Set freq to max by default */\n+\tif (power_cppc_cpufreq_freq_max(lcore_id) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot set frequency of lcore %u \"\n+\t\t\t\t\"to max\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\tRTE_LOG(INFO, POWER, \"Initialized successfully for lcore %u \"\n+\t\t\t\"power management\\n\", lcore_id);\n+\n+\t__atomic_store_n(&(pi->state), POWER_USED, __ATOMIC_RELEASE);\n+\n+\treturn 0;\n+\n+fail:\n+\t__atomic_store_n(&(pi->state), POWER_UNKNOWN, __ATOMIC_RELEASE);\n+\treturn -1;\n+}\n+\n+/**\n+ * It is to check the governor and then set the original governor back if\n+ * needed by writing the sys file.\n+ */\n+static int\n+power_set_governor_original(struct cppc_power_info *pi)\n+{\n+\treturn power_set_governor(pi->lcore_id, pi->governor_ori, NULL, 0);\n+}\n+\n+int\n+power_cppc_cpufreq_exit(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\tuint32_t exp_state;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n+\t\t\t\tlcore_id, RTE_MAX_LCORE - 1U);\n+\t\treturn -1;\n+\t}\n+\tpi = &lcore_power_info[lcore_id];\n+\texp_state = POWER_USED;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n+\t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n+\t\t\t\t\"not used\\n\", lcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Close FD of setting freq */\n+\tfclose(pi->f);\n+\tpi->f = NULL;\n+\n+\t/* Set the governor back to the original */\n+\tif (power_set_governor_original(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot set the governor of %u back \"\n+\t\t\t\t\"to the original\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\tRTE_LOG(INFO, POWER, \"Power management of lcore %u has exited from \"\n+\t\t\t\"'userspace' mode and been set back to the \"\n+\t\t\t\"original\\n\", lcore_id);\n+\t__atomic_store_n(&(pi->state), POWER_IDLE, __ATOMIC_RELEASE);\n+\n+\treturn 0;\n+\n+fail:\n+\t__atomic_store_n(&(pi->state), POWER_UNKNOWN, __ATOMIC_RELEASE);\n+\n+\treturn -1;\n+}\n+\n+uint32_t\n+power_cppc_cpufreq_freqs(unsigned int lcore_id, uint32_t *freqs, uint32_t num)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (freqs == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"NULL buffer supplied\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tif (num < pi->nb_freqs) {\n+\t\tRTE_LOG(ERR, POWER, \"Buffer size is not enough\\n\");\n+\t\treturn 0;\n+\t}\n+\trte_memcpy(freqs, pi->freqs, pi->nb_freqs * sizeof(uint32_t));\n+\n+\treturn pi->nb_freqs;\n+}\n+\n+uint32_t\n+power_cppc_cpufreq_get_freq(unsigned int lcore_id)\n+{\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn RTE_POWER_INVALID_FREQ_INDEX;\n+\t}\n+\n+\treturn lcore_power_info[lcore_id].curr_idx;\n+}\n+\n+int\n+power_cppc_cpufreq_set_freq(unsigned int lcore_id, uint32_t index)\n+{\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn set_freq_internal(&(lcore_power_info[lcore_id]), index);\n+}\n+\n+int\n+power_cppc_cpufreq_freq_down(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tif (pi->curr_idx + 1 == pi->nb_freqs)\n+\t\treturn 0;\n+\n+\t/* Frequencies in the array are from high to low. */\n+\treturn set_freq_internal(pi, pi->curr_idx + 1);\n+}\n+\n+int\n+power_cppc_cpufreq_freq_up(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tif (pi->curr_idx == 0 || (pi->curr_idx == 1 &&\n+\t\tpi->turbo_available && !pi->turbo_enable))\n+\t\treturn 0;\n+\n+\t/* Frequencies in the array are from high to low. */\n+\treturn set_freq_internal(pi, pi->curr_idx - 1);\n+}\n+\n+int\n+power_cppc_cpufreq_freq_max(unsigned int lcore_id)\n+{\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* Frequencies in the array are from high to low. */\n+\tif (lcore_power_info[lcore_id].turbo_available) {\n+\t\tif (lcore_power_info[lcore_id].turbo_enable)\n+\t\t\t/* Set to Turbo */\n+\t\t\treturn set_freq_internal(\n+\t\t\t\t&lcore_power_info[lcore_id], 0);\n+\t\telse\n+\t\t\t/* Set to max non-turbo */\n+\t\t\treturn set_freq_internal(\n+\t\t\t\t&lcore_power_info[lcore_id], 1);\n+\t} else\n+\t\treturn set_freq_internal(&lcore_power_info[lcore_id], 0);\n+}\n+\n+int\n+power_cppc_cpufreq_freq_min(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\t/* Frequencies in the array are from high to low. */\n+\treturn set_freq_internal(pi, pi->nb_freqs - 1);\n+}\n+\n+int\n+power_cppc_turbo_status(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\treturn pi->turbo_enable;\n+}\n+\n+int\n+power_cppc_enable_turbo(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\tif (pi->turbo_available)\n+\t\tpi->turbo_enable = 1;\n+\telse {\n+\t\tpi->turbo_enable = 0;\n+\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\"Failed to enable turbo on lcore %u\\n\",\n+\t\t\tlcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\t/* TODO: must set to max once enbling Turbo? Considering add condition:\n+\t * if ((pi->turbo_available) && (pi->curr_idx <= 1))\n+\t */\n+\t/* Max may have changed, so call to max function */\n+\tif (power_cppc_cpufreq_freq_max(lcore_id) < 0) {\n+\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\"Failed to set frequency of lcore %u to max\\n\",\n+\t\t\tlcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+power_cppc_disable_turbo(unsigned int lcore_id)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\tpi->turbo_enable = 0;\n+\n+\tif ((pi->turbo_available) && (pi->curr_idx <= 1)) {\n+\t\t/* Try to set freq to max by default coming out of turbo */\n+\t\tif (power_cppc_cpufreq_freq_max(lcore_id) < 0) {\n+\t\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\t\"Failed to set frequency of lcore %u to max\\n\",\n+\t\t\t\tlcore_id);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+power_cppc_get_capabilities(unsigned int lcore_id,\n+\t\tstruct rte_power_core_capabilities *caps)\n+{\n+\tstruct cppc_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (caps == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid argument\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tcaps->capabilities = 0;\n+\tcaps->turbo = !!(pi->turbo_available);\n+\n+\treturn 0;\n+}\ndiff --git a/lib/power/power_cppc_cpufreq.h b/lib/power/power_cppc_cpufreq.h\nnew file mode 100644\nindex 000000000..427ce4f83\n--- /dev/null\n+++ b/lib/power/power_cppc_cpufreq.h\n@@ -0,0 +1,229 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Arm Limited\n+ */\n+\n+#ifndef _POWER_CPPC_CPUFREQ_H\n+#define _POWER_CPPC_CPUFREQ_H\n+\n+/**\n+ * @file\n+ * RTE Power Management via userspace CPPC cpufreq\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_byteorder.h>\n+#include <rte_log.h>\n+#include <rte_string_fns.h>\n+#include \"rte_power.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * Check if CPPC power management is supported.\n+ *\n+ * @return\n+ *   - 1 if supported\n+ *   - 0 if unsupported\n+ *   - -1 if error, with rte_errno indicating reason for error.\n+ */\n+int power_cppc_cpufreq_check_supported(void);\n+\n+/**\n+ * Initialize power management for a specific lcore. It will check and set the\n+ * governor to userspace for the lcore, get the available frequencies, and\n+ * prepare to set new lcore frequency.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 0 on success.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_init(unsigned int lcore_id);\n+\n+/**\n+ * Exit power management on a specific lcore. It will set the governor to which\n+ * is before initialized.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 0 on success.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_exit(unsigned int lcore_id);\n+\n+/**\n+ * Get the available frequencies of a specific lcore. The return value will be\n+ * the minimal one of the total number of available frequencies and the number\n+ * of buffer. The index of available frequencies used in other interfaces\n+ * should be in the range of 0 to this return value.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ * @param freqs\n+ *  The buffer array to save the frequencies.\n+ * @param num\n+ *  The number of frequencies to get.\n+ *\n+ * @return\n+ *  The number of available frequencies.\n+ */\n+uint32_t power_cppc_cpufreq_freqs(unsigned int lcore_id, uint32_t *freqs,\n+\t\tuint32_t num);\n+\n+/**\n+ * Return the current index of available frequencies of a specific lcore. It\n+ * will return 'RTE_POWER_INVALID_FREQ_INDEX = (~0)' if error.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  The current index of available frequencies.\n+ */\n+uint32_t power_cppc_cpufreq_get_freq(unsigned int lcore_id);\n+\n+/**\n+ * Set the new frequency for a specific lcore by indicating the index of\n+ * available frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ * @param index\n+ *  The index of available frequencies.\n+ *\n+ * @return\n+ *  - 1 on success with frequency changed.\n+ *  - 0 on success without frequency changed.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_set_freq(unsigned int lcore_id, uint32_t index);\n+\n+/**\n+ * Scale up the frequency of a specific lcore according to the available\n+ * frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 1 on success with frequency changed.\n+ *  - 0 on success without frequency changed.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_freq_up(unsigned int lcore_id);\n+\n+/**\n+ * Scale down the frequency of a specific lcore according to the available\n+ * frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 1 on success with frequency changed.\n+ *  - 0 on success without frequency changed.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_freq_down(unsigned int lcore_id);\n+\n+/**\n+ * Scale up the frequency of a specific lcore to the highest according to the\n+ * available frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 1 on success with frequency changed.\n+ *  - 0 on success without frequency changed.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_freq_max(unsigned int lcore_id);\n+\n+/**\n+ * Scale down the frequency of a specific lcore to the lowest according to the\n+ * available frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 1 on success with frequency changed.\n+ *  - 0 on success without frequency changed.\n+ *  - Negative on error.\n+ */\n+int power_cppc_cpufreq_freq_min(unsigned int lcore_id);\n+\n+/**\n+ * Get the turbo status of a specific lcore.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 1 Turbo Boost is enabled on this lcore.\n+ *  - 0 Turbo Boost is disabled on this lcore.\n+ *  - Negative on error.\n+ */\n+int power_cppc_turbo_status(unsigned int lcore_id);\n+\n+/**\n+ * Enable Turbo Boost on a specific lcore.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 0 Turbo Boost is enabled successfully on this lcore.\n+ *  - Negative on error.\n+ */\n+int power_cppc_enable_turbo(unsigned int lcore_id);\n+\n+/**\n+ * Disable Turbo Boost on a specific lcore.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ *\n+ * @return\n+ *  - 0 Turbo Boost disabled successfully on this lcore.\n+ *  - Negative on error.\n+ */\n+int power_cppc_disable_turbo(unsigned int lcore_id);\n+\n+/**\n+ * Returns power capabilities for a specific lcore.\n+ *\n+ * @param lcore_id\n+ *  lcore id.\n+ * @param caps\n+ *  pointer to rte_power_core_capabilities object.\n+ *\n+ * @return\n+ *  - 0 on success.\n+ *  - Negative on error.\n+ */\n+int power_cppc_get_capabilities(unsigned int lcore_id,\n+\t\tstruct rte_power_core_capabilities *caps);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\ndiff --git a/lib/power/rte_power.c b/lib/power/rte_power.c\nindex 98eaba915..3d51ff8be 100644\n--- a/lib/power/rte_power.c\n+++ b/lib/power/rte_power.c\n@@ -10,6 +10,7 @@\n #include \"power_kvm_vm.h\"\n #include \"power_pstate_cpufreq.h\"\n #include \"power_common.h\"\n+#include \"power_cppc_cpufreq.h\"\n \n enum power_management_env global_default_env = PM_ENV_NOT_SET;\n \n@@ -54,6 +55,8 @@ rte_power_check_env_supported(enum power_management_env env)\n \t\treturn power_pstate_cpufreq_check_supported();\n \tcase PM_ENV_KVM_VM:\n \t\treturn power_kvm_vm_check_supported();\n+\tcase PM_ENV_CPPC_CPUFREQ:\n+\t\treturn power_cppc_cpufreq_check_supported();\n \tdefault:\n \t\trte_errno = EINVAL;\n \t\treturn -1;\n@@ -110,6 +113,18 @@ rte_power_set_env(enum power_management_env env)\n \t\trte_power_freq_disable_turbo = power_pstate_disable_turbo;\n \t\trte_power_get_capabilities = power_pstate_get_capabilities;\n \n+\t} else if (env == PM_ENV_CPPC_CPUFREQ) {\n+\t\trte_power_freqs = power_cppc_cpufreq_freqs;\n+\t\trte_power_get_freq = power_cppc_cpufreq_get_freq;\n+\t\trte_power_set_freq = power_cppc_cpufreq_set_freq;\n+\t\trte_power_freq_up = power_cppc_cpufreq_freq_up;\n+\t\trte_power_freq_down = power_cppc_cpufreq_freq_down;\n+\t\trte_power_freq_min = power_cppc_cpufreq_freq_min;\n+\t\trte_power_freq_max = power_cppc_cpufreq_freq_max;\n+\t\trte_power_turbo_status = power_cppc_turbo_status;\n+\t\trte_power_freq_enable_turbo = power_cppc_enable_turbo;\n+\t\trte_power_freq_disable_turbo = power_cppc_disable_turbo;\n+\t\trte_power_get_capabilities = power_cppc_get_capabilities;\n \t} else {\n \t\tRTE_LOG(ERR, POWER, \"Invalid Power Management Environment(%d) set\\n\",\n \t\t\t\tenv);\n@@ -153,6 +168,8 @@ rte_power_init(unsigned int lcore_id)\n \t\treturn power_kvm_vm_init(lcore_id);\n \tcase PM_ENV_PSTATE_CPUFREQ:\n \t\treturn power_pstate_cpufreq_init(lcore_id);\n+\tcase PM_ENV_CPPC_CPUFREQ:\n+\t\treturn power_cppc_cpufreq_init(lcore_id);\n \tdefault:\n \t\tRTE_LOG(INFO, POWER, \"Env isn't set yet!\\n\");\n \t}\n@@ -172,6 +189,13 @@ rte_power_init(unsigned int lcore_id)\n \t\tgoto out;\n \t}\n \n+\tRTE_LOG(INFO, POWER, \"Attempting to initialise CPPC power management...\\n\");\n+\tret = power_cppc_cpufreq_init(lcore_id);\n+\tif (ret == 0) {\n+\t\trte_power_set_env(PM_ENV_CPPC_CPUFREQ);\n+\t\tgoto out;\n+\t}\n+\n \tRTE_LOG(INFO, POWER, \"Attempting to initialise VM power management...\\n\");\n \tret = power_kvm_vm_init(lcore_id);\n \tif (ret == 0) {\n@@ -194,6 +218,8 @@ rte_power_exit(unsigned int lcore_id)\n \t\treturn power_kvm_vm_exit(lcore_id);\n \tcase PM_ENV_PSTATE_CPUFREQ:\n \t\treturn power_pstate_cpufreq_exit(lcore_id);\n+\tcase PM_ENV_CPPC_CPUFREQ:\n+\t\treturn power_cppc_cpufreq_exit(lcore_id);\n \tdefault:\n \t\tRTE_LOG(ERR, POWER, \"Environment has not been set, unable to exit gracefully\\n\");\n \ndiff --git a/lib/power/rte_power.h b/lib/power/rte_power.h\nindex c8086bf6b..c5759afa3 100644\n--- a/lib/power/rte_power.h\n+++ b/lib/power/rte_power.h\n@@ -22,7 +22,7 @@ extern \"C\" {\n \n /* Power Management Environment State */\n enum power_management_env {PM_ENV_NOT_SET, PM_ENV_ACPI_CPUFREQ, PM_ENV_KVM_VM,\n-\t\tPM_ENV_PSTATE_CPUFREQ};\n+\t\tPM_ENV_PSTATE_CPUFREQ, PM_ENV_CPPC_CPUFREQ};\n \n /**\n  * @warning\n",
    "prefixes": [
        "v4",
        "1/2"
    ]
}