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GET /api/patches/94682/?format=api
{ "id": 94682, "url": "https://patches.dpdk.org/api/patches/94682/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624379833.git.sthotton@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624379833.git.sthotton@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624379833.git.sthotton@marvell.com", "date": "2021-06-22T16:48:08", "name": "[1/2] drivers: add octeontx crypto adapter framework", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e372903e15259ffb982a4a4b1c059308b32d5a8a", "submitter": { "id": 2049, "url": "https://patches.dpdk.org/api/people/2049/?format=api", "name": "Shijith Thotton", "email": "sthotton@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624379833.git.sthotton@marvell.com/mbox/", "series": [ { "id": 17444, "url": "https://patches.dpdk.org/api/series/17444/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17444", "date": "2021-06-22T16:48:07", "name": "OCTEONTX crypto adapter support", "version": 1, "mbox": "https://patches.dpdk.org/series/17444/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94682/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94682/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 91CE2A0548;\n\tTue, 22 Jun 2021 18:49:13 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7BE2D40040;\n\tTue, 22 Jun 2021 18:49:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 22A5F4003C\n for <dev@dpdk.org>; Tue, 22 Jun 2021 18:49:11 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15MGjMkx013066; Tue, 22 Jun 2021 09:49:11 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39b91haupy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 22 Jun 2021 09:49:11 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 22 Jun 2021 09:49:09 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 22 Jun 2021 09:49:09 -0700", "from localhost.localdomain (unknown [10.28.34.29])\n by maili.marvell.com (Postfix) with ESMTP id 870105B6925;\n Tue, 22 Jun 2021 09:49:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2hkGVyNBdmm2xUsUuUe2IvKDA7l0JryItnDO3NK0ZPw=;\n b=B5K1MZWILIrEAqJsbAmCNPzwcfEVSJ77EYCiZaAHluqmA2lfonHf+rKIfN8m1MBP3Nmp\n dpHulvfEEknpqQFATokRr1NhMlJJEXlttCbFzxSG4gP9aURUJHUZRalbJA2bBOOr3KeJ\n NquXR2LL1BS/MIMpw3Endl7/SCt5k85twgqPtjyf+ZfDesQ8vAUbwms8c4vbNFzspajE\n a732nmi2AaU6z+IQHjaWlHnMnaRCgzZ0GXCT2Hbqvm67v9gsr4wx3eT8lA6WhmfKAKI6\n h1LbKU8BPMlW5rSZfm0fVy+AxkK+b+wiL9Wt+3noGnehIeEAfw1/622FWSpVedpCkBRt JA==", "From": "Shijith Thotton <sthotton@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<sthotton@marvell.com>, <pbhagavatula@marvell.com>, <anoobj@marvell.com>,\n <jerinj@marvell.com>, <abhinandan.gujjar@intel.com>,\n <adwivedi@marvell.com>, <gakhil@marvell.com>", "Date": "Tue, 22 Jun 2021 22:18:08 +0530", "Message-ID": "\n <2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624379833.git.sthotton@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1624379833.git.sthotton@marvell.com>", "References": "<cover.1624379833.git.sthotton@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "oZIXbKS_ulqrSEOWOL4fNr5negpIxwDR", "X-Proofpoint-GUID": "oZIXbKS_ulqrSEOWOL4fNr5negpIxwDR", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-22_11:2021-06-22,\n 2021-06-22 signatures=0", "Subject": "[dpdk-dev] [PATCH 1/2] drivers: add octeontx crypto adapter\n framework", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Set crypto adapter event device slow-path call backs.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/crypto/octeontx/meson.build | 1 +\n drivers/crypto/octeontx/otx_cryptodev.c | 4 ++\n drivers/crypto/octeontx/otx_cryptodev.h | 4 --\n .../crypto/octeontx/otx_cryptodev_hw_access.h | 1 +\n drivers/event/octeontx/meson.build | 1 +\n drivers/event/octeontx/ssovf_evdev.c | 67 +++++++++++++++++++\n 6 files changed, 74 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build\nindex daef47a72f..37603c5c89 100644\n--- a/drivers/crypto/octeontx/meson.build\n+++ b/drivers/crypto/octeontx/meson.build\n@@ -7,6 +7,7 @@ endif\n \n deps += ['bus_pci']\n deps += ['common_cpt']\n+deps += ['eventdev']\n \n sources = files(\n 'otx_cryptodev.c',\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c\nindex ba73c2f939..7207909abb 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev.c\n@@ -14,6 +14,10 @@\n \n #include \"cpt_pmd_logs.h\"\n \n+/* Device ID */\n+#define PCI_VENDOR_ID_CAVIUM\t\t0x177d\n+#define CPT_81XX_PCI_VF_DEVICE_ID\t0xa041\n+\n uint8_t otx_cryptodev_driver_id;\n \n static struct rte_pci_id pci_id_cpt_table[] = {\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h\nindex b66ef4a8f7..5d8607eafb 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev.h\n@@ -8,10 +8,6 @@\n /* Cavium OCTEON TX crypto PMD device name */\n #define CRYPTODEV_NAME_OCTEONTX_PMD\tcrypto_octeontx\n \n-/* Device ID */\n-#define PCI_VENDOR_ID_CAVIUM\t\t0x177d\n-#define CPT_81XX_PCI_VF_DEVICE_ID\t0xa041\n-\n #define CPT_LOGTYPE otx_cpt_logtype\n \n extern int otx_cpt_logtype;\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 0ec258157a..f7b1e93402 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -45,6 +45,7 @@ struct cpt_instance {\n \tstruct rte_mempool *sess_mp;\n \tstruct rte_mempool *sess_mp_priv;\n \tstruct cpt_qp_meta_info meta_info;\n+\tuint8_t ca_enabled;\n };\n \n struct command_chunk {\ndiff --git a/drivers/event/octeontx/meson.build b/drivers/event/octeontx/meson.build\nindex 3cb140b4de..0d9eec3f2e 100644\n--- a/drivers/event/octeontx/meson.build\n+++ b/drivers/event/octeontx/meson.build\n@@ -12,3 +12,4 @@ sources = files(\n )\n \n deps += ['common_octeontx', 'mempool_octeontx', 'bus_vdev', 'net_octeontx']\n+deps += ['crypto_octeontx']\ndiff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c\nindex d8b359801a..25bf207db6 100644\n--- a/drivers/event/octeontx/ssovf_evdev.c\n+++ b/drivers/event/octeontx/ssovf_evdev.c\n@@ -5,6 +5,7 @@\n #include <inttypes.h>\n \n #include <rte_common.h>\n+#include <rte_cryptodev.h>\n #include <rte_debug.h>\n #include <rte_dev.h>\n #include <rte_eal.h>\n@@ -19,6 +20,7 @@\n \n #include \"ssovf_evdev.h\"\n #include \"timvf_evdev.h\"\n+#include \"otx_cryptodev_hw_access.h\"\n \n static uint8_t timvf_enable_stats;\n \n@@ -725,6 +727,67 @@ ssovf_timvf_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\t\ttimvf_enable_stats);\n }\n \n+static int\n+ssovf_crypto_adapter_caps_get(const struct rte_eventdev *dev,\n+\t\t\t const struct rte_cryptodev *cdev, uint32_t *caps)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(cdev);\n+\n+\t*caps = 0;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ssovf_crypto_adapter_qp_add(const struct rte_eventdev *dev,\n+\t\t\t const struct rte_cryptodev *cdev,\n+\t\t\t int32_t queue_pair_id,\n+\t\t\t const struct rte_event *event)\n+{\n+\tstruct cpt_instance *qp;\n+\tuint8_t qp_id;\n+\n+\tRTE_SET_USED(event);\n+\n+\tif (queue_pair_id == -1) {\n+\t\tfor (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {\n+\t\t\tqp = cdev->data->queue_pairs[qp_id];\n+\t\t\tqp->ca_enabled = 1;\n+\t\t}\n+\t} else {\n+\t\tqp = cdev->data->queue_pairs[queue_pair_id];\n+\t\tqp->ca_enabled = 1;\n+\t}\n+\n+\tssovf_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ssovf_crypto_adapter_qp_del(const struct rte_eventdev *dev,\n+\t\t\t const struct rte_cryptodev *cdev,\n+\t\t\t int32_t queue_pair_id)\n+{\n+\tstruct cpt_instance *qp;\n+\tuint8_t qp_id;\n+\n+\tRTE_SET_USED(dev);\n+\n+\tif (queue_pair_id == -1) {\n+\t\tfor (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {\n+\t\t\tqp = cdev->data->queue_pairs[qp_id];\n+\t\t\tqp->ca_enabled = 0;\n+\t\t}\n+\t} else {\n+\t\tqp = cdev->data->queue_pairs[queue_pair_id];\n+\t\tqp->ca_enabled = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Initialize and register event driver with DPDK Application */\n static struct rte_eventdev_ops ssovf_ops = {\n \t.dev_infos_get = ssovf_info_get,\n@@ -755,6 +818,10 @@ static struct rte_eventdev_ops ssovf_ops = {\n \n \t.timer_adapter_caps_get = ssovf_timvf_caps_get,\n \n+\t.crypto_adapter_caps_get = ssovf_crypto_adapter_caps_get,\n+\t.crypto_adapter_queue_pair_add = ssovf_crypto_adapter_qp_add,\n+\t.crypto_adapter_queue_pair_del = ssovf_crypto_adapter_qp_del,\n+\n \t.dev_selftest = test_eventdev_octeontx,\n \n \t.dump = ssovf_dump,\n", "prefixes": [ "1/2" ] }