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GET /api/patches/94680/?format=api
{ "id": 94680, "url": "https://patches.dpdk.org/api/patches/94680/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210622164049.9191-1-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210622164049.9191-1-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210622164049.9191-1-viacheslavo@nvidia.com", "date": "2021-06-22T16:40:49", "name": "net/mlx5: fix multi-segment inline for the first segment", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a6bf33b2b919b19a05aefa34e76894fe71d03167", "submitter": { "id": 1926, "url": "https://patches.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210622164049.9191-1-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 17443, "url": "https://patches.dpdk.org/api/series/17443/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17443", "date": "2021-06-22T16:40:49", "name": "net/mlx5: fix multi-segment inline for the first segment", "version": 1, "mbox": "https://patches.dpdk.org/series/17443/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94680/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94680/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9CB1BA0548;\n\tTue, 22 Jun 2021 18:41:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5A9084003F;\n\tTue, 22 Jun 2021 18:41:11 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2077.outbound.protection.outlook.com [40.107.220.77])\n by mails.dpdk.org (Postfix) with ESMTP id 5362A4003C;\n Tue, 22 Jun 2021 18:41:10 +0200 (CEST)", "from BN9PR03CA0538.namprd03.prod.outlook.com (2603:10b6:408:131::33)\n by DM8PR12MB5400.namprd12.prod.outlook.com (2603:10b6:8:3b::12) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.18; 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dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<rasland@nvidia.com>, <matan@nvidia.com>, <alialnu@nvidia.com>,\n <stable@dpdk.org>", "Date": "Tue, 22 Jun 2021 19:40:49 +0300", "Message-ID": "<20210622164049.9191-1-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "282edea8-a492-476f-8c09-08d9359c8953", "X-MS-TrafficTypeDiagnostic": "DM8PR12MB5400:", "X-Microsoft-Antispam-PRVS": "\n <DM8PR12MB5400A3C3853E0B584A2C8AC5DF099@DM8PR12MB5400.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:9508;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /ZKuiMvwUAkERmhKCyq5VIuyII/KB41YJVVj8ZEpbo97RUnOt9oNAXGw1XHFtGypXqaL3HQpIe1HLf1+i0GIoonYlCuePbY2mymP6NLITDwibk7BwbWhaG4WO0WRWilA64+QfVeT/EV4q7Y0BHkuriGCM67ZtP96frAgcapuU1lKUJdqBLRE5dPfBRGP10k99r2aK6N79sxoreJHjN2G770DARVLcwrfTZQdgBbk6oFw29lvP5yZMI+NAEUHqpy6yIyxfTDeTTJOIeZ+Nfn4diFrpzZzr8dYoTuud/IoXa+OmH+MU0QkN0dZwXdY9Bp0QmO+q6qxkZV9dQEUNmhKAU0MaRvQ7BXwP3MuZjPuw0tSqyAkFVDtbSpqHmZ3RipmCaLQ8A/BlpSzHytMxbBiai6kVTqAtVlBIJh34SzxNd4EDLSc/153FqrgadFvltGms1l2KVxpLh0Npvxatv+wB+/juJu5GFJnPYqFtXNxaUoBB+CYQlEmI+movtMquFc1x1JAE8ha3CFAvXs8Y879YCBLSy/fY2rp3muHR7wBs8WQUm6JrnDGhQ6S7AN4+u5mlCfWKDcX5rlcBz1pnUk9mG8mY8/wYxGGh9yDJSE+88srTUcuGluOdq9Qlx6Bjkla0cd6YH1qAEKr5RgngHtfYSH/ZPXYMtJwgogtYH9xv2fijPPwW4K3Ygqc4D0JfjFqxbPbD5JFt0+vkETrKVjYMw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(82310400003)(16526019)(7696005)(356005)(6666004)(6916009)(1076003)(186003)(2906002)(36756003)(26005)(6286002)(7636003)(5660300002)(426003)(2616005)(70206006)(83380400001)(47076005)(336012)(86362001)(450100002)(8936002)(36906005)(36860700001)(70586007)(8676002)(4326008)(498600001)(54906003)(55016002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Jun 2021 16:41:08.2961 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 282edea8-a492-476f-8c09-08d9359c8953", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT068.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM8PR12MB5400", "Subject": "[dpdk-dev] [PATCH] net/mlx5: fix multi-segment inline for the first\n segment", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "If the first segment in the multi-segment packet is short\nand below the inline threshold it should be inline into\nthe WQE to improve the performance. For example, the T-Rex\ntraffic generator might use small leading segments to\nhandle packet headers and performance was affected.\n\nFixes: cacb44a09962 (\"net/mlx5: add no-inline Tx flag\")\nCc: stable@dpdk.org\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_tx.h | 28 +++++++++++++---------------\n 1 file changed, 13 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex e8b1c0f108..1a35919371 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -2041,6 +2041,8 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,\n \t\tunsigned int nxlen;\n \t\tuintptr_t start;\n \n+\t\tmbuf = loc->mbuf;\n+\t\tnxlen = rte_pktmbuf_data_len(mbuf);\n \t\t/*\n \t\t * Packet length exceeds the allowed inline data length,\n \t\t * check whether the minimal inlining is required.\n@@ -2050,28 +2052,23 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t\t MLX5_ESEG_MIN_INLINE_SIZE);\n \t\t\tMLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);\n \t\t\tinlen = txq->inlen_mode;\n-\t\t} else {\n-\t\t\tif (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||\n-\t\t\t !vlan || txq->vlan_en) {\n-\t\t\t\t/*\n-\t\t\t\t * VLAN insertion will be done inside by HW.\n-\t\t\t\t * It is not utmost effective - VLAN flag is\n-\t\t\t\t * checked twice, but we should proceed the\n-\t\t\t\t * inlining length correctly and take into\n-\t\t\t\t * account the VLAN header being inserted.\n-\t\t\t\t */\n-\t\t\t\treturn mlx5_tx_packet_multi_send\n-\t\t\t\t\t\t\t(txq, loc, olx);\n-\t\t\t}\n+\t\t} else if (vlan && !txq->vlan_en) {\n+\t\t\t/*\n+\t\t\t * VLAN insertion is requested and hardware does not\n+\t\t\t * support the offload, will do with software inline.\n+\t\t\t */\n \t\t\tinlen = MLX5_ESEG_MIN_INLINE_SIZE;\n+\t\t} else if (mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||\n+\t\t\t nxlen > txq->inlen_send) {\n+\t\t\treturn mlx5_tx_packet_multi_send(txq, loc, olx);\n+\t\t} else {\n+\t\t\tgoto do_first;\n \t\t}\n \t\t/*\n \t\t * Now we know the minimal amount of data is requested\n \t\t * to inline. Check whether we should inline the buffers\n \t\t * from the chain beginning to eliminate some mbufs.\n \t\t */\n-\t\tmbuf = loc->mbuf;\n-\t\tnxlen = rte_pktmbuf_data_len(mbuf);\n \t\tif (unlikely(nxlen <= txq->inlen_send)) {\n \t\t\t/* We can inline first mbuf at least. */\n \t\t\tif (nxlen < inlen) {\n@@ -2093,6 +2090,7 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t\t\tgoto do_align;\n \t\t\t\t}\n \t\t\t}\n+do_first:\n \t\t\tdo {\n \t\t\t\tinlen = nxlen;\n \t\t\t\tmbuf = NEXT(mbuf);\n", "prefixes": [] }