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GET /api/patches/94647/?format=api
{ "id": 94647, "url": "https://patches.dpdk.org/api/patches/94647/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-24-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-24-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-24-tduszynski@marvell.com", "date": "2021-06-21T15:04:40", "name": "[v3,23/32] raw/cnxk_bphy: add baseband PHY skeleton driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5f1f15342f90d9dd6f8421eb737eff0e0a64c649", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-24-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94647/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94647/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DB411A0547;\n\tMon, 21 Jun 2021 17:07:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 522D941231;\n\tMon, 21 Jun 2021 17:06:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D320B41231\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:06:05 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LEui8a003874; Mon, 21 Jun 2021 08:06:05 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39ap171gjm-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:06:05 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:06:03 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:06:03 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id 244433F7063;\n Mon, 21 Jun 2021 08:06:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=oQv7IpIwXP7VbW2stT+6vHdgtY9hS+JFFzSgAv72IlU=;\n b=gr4eTOW92gmUJvVRs8Af72WoPjnnbzu7SQq49qYw2BOswj2qEYil0jxuRPF9c9U+L4zs\n t+2Tfp4pjZq0YLIMKeaw6dqDFK6Z204r88bOaf7HAEr7X00t6VHGEe842EC2oM0pXOWq\n QjyzYD3TNLcP/1IAlkx3Tkrk7onPd/e8oyXT52fR5Di0IB5BGzpAav9m9iSO9uX//H2c\n ernRxzvHTaCGkLhEDBtLvcr6G6/1t/FI87UbK1hSQ47VdT8MySDi2vc9s0WBAmw69J6B\n XJY1QCZS3un8G9WsSI6/LG8uPbcRaey0Yg3KLNFoHuMW9KAhiO4e5KYbbp5qA+iXt+YJ GQ==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Jakub Palider <jpalider@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>, Anatoly Burakov <anatoly.burakov@intel.com>", "CC": "<thomas@monjalon.net>, <dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:40 +0200", "Message-ID": "<20210621150449.19070-24-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "OhZArAnE7_HS5wNPPkKB3RnIJCpznKWa", "X-Proofpoint-ORIG-GUID": "OhZArAnE7_HS5wNPPkKB3RnIJCpznKWa", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 23/32] raw/cnxk_bphy: add baseband PHY\n skeleton driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add baseband phy skeleton driver. Baseband phy is a hardware subsystem\naccelerating 5G/LTE related tasks. Note this driver isn't involved into\nany sort baseband protocol processing. Instead it just provides means\nfor configuring hardware.\n\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/raw/cnxk_bphy/cnxk_bphy.c | 113 ++++++++++++++++++++++++++\n drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 23 ++++++\n drivers/raw/cnxk_bphy/meson.build | 1 +\n usertools/dpdk-devbind.py | 4 +-\n 4 files changed, 140 insertions(+), 1 deletion(-)\n create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c\n create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h", "diff": "diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c\nnew file mode 100644\nindex 000000000..cd26b9717\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c\n@@ -0,0 +1,113 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_eal.h>\n+#include <rte_lcore.h>\n+#include <rte_pci.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include <roc_api.h>\n+\n+#include \"cnxk_bphy_irq.h\"\n+\n+static const struct rte_pci_id pci_bphy_map[] = {\n+\t{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static void\n+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)\n+{\n+\tsnprintf(name, RTE_RAWDEV_NAME_MAX_LEN, \"BPHY:%x:%02x.%x\",\n+\t\t pci_dev->addr.bus, pci_dev->addr.devid,\n+\t\t pci_dev->addr.function);\n+}\n+\n+static const struct rte_rawdev_ops bphy_rawdev_ops = {\n+};\n+\n+static int\n+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tstruct bphy_device *bphy_dev = NULL;\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *bphy_rawdev;\n+\tint ret;\n+\n+\tRTE_SET_USED(pci_drv);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (!pci_dev->mem_resource[0].addr) {\n+\t\tplt_err(\"BARs have invalid values: BAR0 %p\\n BAR2 %p\",\n+\t\t\tpci_dev->mem_resource[0].addr,\n+\t\t\tpci_dev->mem_resource[2].addr);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = roc_plt_init();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tbphy_rawdev_get_name(name, pci_dev);\n+\tbphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),\n+\t\t\t\t\t rte_socket_id());\n+\tif (bphy_rawdev == NULL) {\n+\t\tplt_err(\"Failed to allocate rawdev\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tbphy_rawdev->dev_ops = &bphy_rawdev_ops;\n+\tbphy_rawdev->device = &pci_dev->device;\n+\tbphy_rawdev->driver_name = pci_dev->driver->driver.name;\n+\n+\tbphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;\n+\tbphy_dev->mem.res0 = pci_dev->mem_resource[0];\n+\tbphy_dev->mem.res2 = pci_dev->mem_resource[2];\n+\n+\treturn 0;\n+}\n+\n+static int\n+bphy_rawdev_remove(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *rawdev;\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (pci_dev == NULL) {\n+\t\tplt_err(\"invalid pci_dev\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trawdev = rte_rawdev_pmd_get_named_dev(name);\n+\tif (rawdev == NULL) {\n+\t\tplt_err(\"invalid device name (%s)\", name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbphy_rawdev_get_name(name, pci_dev);\n+\n+\treturn rte_rawdev_pmd_release(rawdev);\n+}\n+\n+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {\n+\t.id_table = pci_bphy_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n+\t.probe = bphy_rawdev_probe,\n+\t.remove = bphy_rawdev_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);\n+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, \"vfio-pci\");\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h\nnew file mode 100644\nindex 000000000..77169b1b7\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h\n@@ -0,0 +1,23 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CNXK_BPHY_IRQ_\n+#define _CNXK_BPHY_IRQ_\n+\n+#include <rte_bus_pci.h>\n+#include <rte_dev.h>\n+\n+#include <roc_api.h>\n+\n+struct bphy_mem {\n+\tstruct rte_mem_resource res0;\n+\tstruct rte_mem_resource res2;\n+};\n+\n+struct bphy_device {\n+\tstruct roc_bphy_irq_chip *irq_chip;\n+\tstruct bphy_mem mem;\n+};\n+\n+#endif /* _CNXK_BPHY_IRQ_ */\ndiff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build\nindex dc5558ee8..f2868fd68 100644\n--- a/drivers/raw/cnxk_bphy/meson.build\n+++ b/drivers/raw/cnxk_bphy/meson.build\n@@ -4,6 +4,7 @@\n \n deps += ['bus_pci', 'common_cnxk', 'rawdev']\n sources = files(\n+ 'cnxk_bphy.c',\n 'cnxk_bphy_cgx.c',\n 'cnxk_bphy_cgx_test.c',\n )\ndiff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py\nindex 55a73961d..74d16e4c4 100755\n--- a/usertools/dpdk-devbind.py\n+++ b/usertools/dpdk-devbind.py\n@@ -45,6 +45,8 @@\n 'SVendor': None, 'SDevice': None}\n octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',\n 'SVendor': None, 'SDevice': None}\n+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089',\n+ 'SVendor': None, 'SDevice': None}\n cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',\n 'SVendor': None, 'SDevice': None}\n \n@@ -71,7 +73,7 @@\n mempool_devices = [cavium_fpa, octeontx2_npa]\n compress_devices = [cavium_zip]\n regex_devices = [octeontx2_ree]\n-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,\n+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,\n intel_ntb_skx, intel_ntb_icx,\n octeontx2_dma]\n \n", "prefixes": [ "v3", "23/32" ] }