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GET /api/patches/94637/?format=api
{ "id": 94637, "url": "https://patches.dpdk.org/api/patches/94637/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-13-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-13-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-13-tduszynski@marvell.com", "date": "2021-06-21T15:04:29", "name": "[v3,12/32] raw/cnxk_bphy: support for enqueue operation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a27513039d34f8436100ce0455fdec43d393454d", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-13-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94637/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94637/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 09A3BA0547;\n\tMon, 21 Jun 2021 17:06:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EA26A411F9;\n\tMon, 21 Jun 2021 17:05:38 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 8F4B8411F7\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:05:35 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LF5EUg008501; Mon, 21 Jun 2021 08:05:34 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xja10-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:05:34 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:05:33 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:05:33 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id D88033F705E;\n Mon, 21 Jun 2021 08:05:31 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=CN3HsG/VdsDB6XfkVoT0pB+IyZ8gC4Zg4BIQXx49EuQ=;\n b=BthLvfoeCa3xBfFME+asEKIxIOpp0v5ji4tGXPlScnmGJR2mkONTpfQ7uw9eD5cBsnVU\n fnj/n9St7UNcTpZ9zwjozZ3Su4le5o0gNJZRUYrcJjZ+6AWqpvzikrPNItP08sz3RbaW\n VYtayHN1vHKKAx/NK4zSm5CASBs9fixwQAy4CQrAhVu0cW3iQUasoIOu3eHTmKIjWQw6\n MbW6e+p3DTWaxqtgqr23JvhvM7uu+p1zZgS75wJI97TzqKEYqIovo4x9JRqicWepX7gE\n Uu7vCYuFDZZu3A3A1Y7Oh72X/okCE04KYKBjDolVqxAYqJwQv8nlgrch/XOa3ZEh1jwB Wg==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Jakub Palider <jpalider@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>", "CC": "<thomas@monjalon.net>, <dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:29 +0200", "Message-ID": "<20210621150449.19070-13-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "SNSK0rjN41BXWGSqD9RaCsfVuWmkBvz-", "X-Proofpoint-ORIG-GUID": "SNSK0rjN41BXWGSqD9RaCsfVuWmkBvz-", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 12/32] raw/cnxk_bphy: support for enqueue\n operation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for enqueueing messages.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n doc/guides/rawdevs/cnxk_bphy.rst | 68 ++++++++++++++++\n drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++\n drivers/raw/cnxk_bphy/meson.build | 1 +\n drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 104 ++++++++++++++++++++++++\n 4 files changed, 285 insertions(+)\n create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h", "diff": "diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst\nindex d6803e527..0d842a831 100644\n--- a/doc/guides/rawdevs/cnxk_bphy.rst\n+++ b/doc/guides/rawdevs/cnxk_bphy.rst\n@@ -11,6 +11,13 @@ backed by ethernet I/O block called CGX or RPM (depending on the chip version).\n RFOE stands for Radio Frequency Over Ethernet and provides support for\n IEEE 1904.3 (RoE) standard.\n \n+Features\n+--------\n+\n+The BPHY CGX/RPM implements following features in the rawdev API:\n+\n+- Access to BPHY CGX/RPM via a set of predefined messages\n+\n Device Setup\n ------------\n \n@@ -25,3 +32,64 @@ devices alone.\n Before performing actual data transfer one needs to first retrieve number of\n available queues with ``rte_rawdev_queue_count()`` and capacity of each\n using ``rte_rawdev_queue_conf_get()``.\n+\n+To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and\n+``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible\n+responses hence dequeueing is not always necessary.\n+\n+BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.\n+Message types along with description are listed below.\n+\n+Get link information\n+~~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to get information about link state.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO``. In response one will\n+get message containing payload i.e ``struct cnxk_bphy_cgx_msg_link_info`` filled with information\n+about current link state.\n+\n+Change internal loopback state\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to enable or disable internal loopback.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE`` or\n+``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate internal loopback while the latter\n+will do the opposite.\n+\n+Change PTP RX state\n+~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to enable or disable PTP mode.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE`` or\n+``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE``. Former will enable PTP while the latter will do the\n+opposite.\n+\n+Set link mode\n+~~~~~~~~~~~~~\n+\n+Message is used to change link mode.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE``. Prior to sending actual\n+message payload i.e ``struct cnxk_bphy_cgx_msg_link_mode`` needs to be filled with relevant\n+information.\n+\n+Change link state\n+~~~~~~~~~~~~~~~~~\n+\n+Message is used to set link up or down.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE``. Prior to sending actual\n+message payload i.e ``struct cnxk_bphy_cgx_msg_set_link_state`` needs to be filled with relevant\n+information.\n+\n+Start or stop RX/TX\n+~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to start or stop accepting traffic.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or\n+``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will\n+do the opposite.\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\nindex da4372642..637514406 100644\n--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n@@ -1,12 +1,16 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(C) 2021 Marvell.\n */\n+#include <string.h>\n+\n #include <rte_bus_pci.h>\n #include <rte_rawdev.h>\n #include <rte_rawdev_pmd.h>\n \n #include <roc_api.h>\n \n+#include \"rte_pmd_bphy.h\"\n+\n struct cnxk_bphy_cgx_queue {\n \tunsigned int lmac;\n \t/* queue holds up to one response */\n@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,\n \treturn 0;\n }\n \n+static int\n+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,\n+\t\t\t struct rte_rawdev_buf *buf)\n+{\n+\tstruct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];\n+\tstruct cnxk_bphy_cgx_msg_set_link_state *link_state;\n+\tstruct cnxk_bphy_cgx_msg *msg = buf->buf_addr;\n+\tstruct cnxk_bphy_cgx_msg_link_mode *link_mode;\n+\tstruct cnxk_bphy_cgx_msg_link_info *link_info;\n+\tstruct roc_bphy_cgx_link_info rlink_info;\n+\tstruct roc_bphy_cgx_link_mode rlink_mode;\n+\tunsigned int lmac = qp->lmac;\n+\tvoid *rsp = NULL;\n+\tint ret;\n+\n+\tswitch (msg->type) {\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:\n+\t\tmemset(&rlink_info, 0, sizeof(rlink_info));\n+\t\tret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\n+\t\tlink_info = rte_zmalloc(NULL, sizeof(*link_info), 0);\n+\t\tif (!link_info)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tlink_info->link_up = rlink_info.link_up;\n+\t\tlink_info->full_duplex = rlink_info.full_duplex;\n+\t\tlink_info->speed =\n+\t\t\t(enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed;\n+\t\tlink_info->autoneg = rlink_info.an;\n+\t\tlink_info->fec =\n+\t\t\t(enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec;\n+\t\tlink_info->mode =\n+\t\t\t(enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode;\n+\t\trsp = link_info;\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE:\n+\t\tret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE:\n+\t\tret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE:\n+\t\tret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE:\n+\t\tret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE:\n+\t\tlink_mode = msg->data;\n+\t\tmemset(&rlink_mode, 0, sizeof(rlink_mode));\n+\t\trlink_mode.full_duplex = link_mode->full_duplex;\n+\t\trlink_mode.an = link_mode->autoneg;\n+\t\trlink_mode.speed =\n+\t\t\t(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;\n+\t\trlink_mode.mode =\n+\t\t\t(enum roc_bphy_cgx_eth_link_mode)link_mode->mode;\n+\t\tret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:\n+\t\tlink_state = msg->data;\n+\t\tret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac,\n+\t\t\t\t\t\t link_state->state);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_START_RXTX:\n+\t\tret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac);\n+\t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX:\n+\t\tret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* get rid of last response if any */\n+\tif (qp->rsp) {\n+\t\tRTE_LOG(WARNING, PMD, \"Previous response got overwritten\\n\");\n+\t\trte_free(qp->rsp);\n+\t}\n+\tqp->rsp = rsp;\n+\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,\n+\t\t\t struct rte_rawdev_buf **buffers, unsigned int count,\n+\t\t\t rte_rawdev_obj_t context)\n+{\n+\tstruct cnxk_bphy_cgx *cgx = dev->dev_private;\n+\tunsigned int queue = (size_t)context;\n+\tint ret;\n+\n+\tif (queue >= cgx->num_queues)\n+\t\treturn -EINVAL;\n+\n+\tif (count == 0)\n+\t\treturn 0;\n+\n+\tret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 1;\n+}\n+\n static uint16_t\n cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)\n {\n@@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)\n \n static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {\n \t.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,\n+\t.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,\n \t.queue_count = cnxk_bphy_cgx_queue_count,\n };\n \ndiff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build\nindex 78d8081fe..0d65fc5c8 100644\n--- a/drivers/raw/cnxk_bphy/meson.build\n+++ b/drivers/raw/cnxk_bphy/meson.build\n@@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']\n sources = files(\n 'cnxk_bphy_cgx.c',\n )\n+headers = files('rte_pmd_bphy.h')\ndiff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\nnew file mode 100644\nindex 000000000..fed7916fe\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n@@ -0,0 +1,104 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _CNXK_BPHY_H_\n+#define _CNXK_BPHY_H_\n+\n+enum cnxk_bphy_cgx_msg_type {\n+\tCNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,\n+\tCNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,\n+\tCNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,\n+\tCNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,\n+\tCNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,\n+\tCNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,\n+\tCNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,\n+\tCNXK_BPHY_CGX_MSG_TYPE_START_RXTX,\n+\tCNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,\n+};\n+\n+enum cnxk_bphy_cgx_eth_link_speed {\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_10M,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_100M,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_1G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_5G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_10G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_20G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_25G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_40G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_50G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_80G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_100G,\n+\t__CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX\n+};\n+\n+enum cnxk_bphy_cgx_eth_link_fec {\n+\tCNXK_BPHY_CGX_ETH_LINK_FEC_NONE,\n+\tCNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,\n+\tCNXK_BPHY_CGX_ETH_LINK_FEC_RS,\n+\t__CNXK_BPHY_CGX_ETH_LINK_FEC_MAX\n+};\n+\n+enum cnxk_bphy_cgx_eth_link_mode {\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,\n+\t__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX\n+};\n+\n+struct cnxk_bphy_cgx_msg_link_mode {\n+\tbool full_duplex;\n+\tbool autoneg;\n+\tenum cnxk_bphy_cgx_eth_link_speed speed;\n+\tenum cnxk_bphy_cgx_eth_link_mode mode;\n+};\n+\n+struct cnxk_bphy_cgx_msg_link_info {\n+\tbool link_up;\n+\tbool full_duplex;\n+\tenum cnxk_bphy_cgx_eth_link_speed speed;\n+\tbool autoneg;\n+\tenum cnxk_bphy_cgx_eth_link_fec fec;\n+\tenum cnxk_bphy_cgx_eth_link_mode mode;\n+};\n+\n+struct cnxk_bphy_cgx_msg_set_link_state {\n+\tbool state; /* up or down */\n+};\n+\n+struct cnxk_bphy_cgx_msg {\n+\tenum cnxk_bphy_cgx_msg_type type;\n+\t/*\n+\t * data depends on message type and whether\n+\t * it's a request or a response\n+\t */\n+\tvoid *data;\n+};\n+\n+#endif /* _CNXK_BPHY_H_ */\n", "prefixes": [ "v3", "12/32" ] }