Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94635/?format=api
{ "id": 94635, "url": "https://patches.dpdk.org/api/patches/94635/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-10-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-10-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-10-tduszynski@marvell.com", "date": "2021-06-21T15:04:26", "name": "[v3,09/32] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e6d3153320abbe1631f1ce1537471f8a175efb5c", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-10-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94635/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94635/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 61411A0547;\n\tMon, 21 Jun 2021 17:06:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3B501411F3;\n\tMon, 21 Jun 2021 17:05:35 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 110E5411F5\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:05:31 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LF5HT3008514; Mon, 21 Jun 2021 08:05:29 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xja0c-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:05:29 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:05:27 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:05:27 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id D6FF93F7065;\n Mon, 21 Jun 2021 08:05:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2DKrPRoDThbULoeoO3TfufLeu9ploLibZUzdWEpImNY=;\n b=Wf4PfayqTKttjInO/x6l+NOOdu0WQgxXDOgiVZY72Io3cvrbqBxIAoyRpVOXshY98Mug\n weqqUDlUbPh92Wk0kaTj+q6y88cCmRpsrYylLZRjEmCFUEXizTMOHvTpxd7m6Gio+0Gp\n gjaVIozR+Xhldp4/DrYWLLOS6yMsOr2AZkXiB7PnhyCWqAs0TuMu8gbwiSzUiQOcd/qz\n QOqAjKBVJZnztHIWKlfSa1qQAs0lRpOdntLp9Ernfq3I1V3D9QJd2V+v8bjE8WEMHLB1\n xky5snrzBhNbiejmlWTJ30X7RpprWVEIV8HJOm8iT4T00x6n/uLx0xTSkWC0BVMEBx1y ig==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, \"Sunil\n Kumar Kori\" <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>, \"Jakub\n Palider\" <jpalider@marvell.com>, Tomasz Duszynski <tduszynski@marvell.com>,\n Ray Kinsella <mdr@ashroe.eu>, Neil Horman <nhorman@tuxdriver.com>, \"Anatoly\n Burakov\" <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:26 +0200", "Message-ID": "<20210621150449.19070-10-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "NYb-poydWWnrHvzi-EKNgxc9EW16MThM", "X-Proofpoint-ORIG-GUID": "NYb-poydWWnrHvzi-EKNgxc9EW16MThM", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 09/32] raw/cnxk_bphy: add bphy cgx/rpm\n skeleton driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add baseband phy cgx/rpm skeleton driver which merely probes a matching\ndevice. CGX/RPM are Ethernet MACs hardwired to baseband subsystem.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n MAINTAINERS | 7 +-\n doc/guides/platform/cnxk.rst | 3 +\n doc/guides/rawdevs/cnxk_bphy.rst | 23 ++++\n doc/guides/rawdevs/index.rst | 1 +\n doc/guides/rel_notes/release_21_08.rst | 7 ++\n drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 +++++++++++++++++++++++++\n drivers/raw/cnxk_bphy/meson.build | 8 ++\n drivers/raw/cnxk_bphy/version.map | 3 +\n drivers/raw/meson.build | 1 +\n usertools/dpdk-devbind.py | 4 +-\n 10 files changed, 206 insertions(+), 2 deletions(-)\n create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst\n create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n create mode 100644 drivers/raw/cnxk_bphy/meson.build\n create mode 100644 drivers/raw/cnxk_bphy/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 5877a1697..4f533fcdb 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1287,6 +1287,12 @@ M: Nipun Gupta <nipun.gupta@nxp.com>\n F: drivers/raw/dpaa2_cmdif/\n F: doc/guides/rawdevs/dpaa2_cmdif.rst\n \n+Marvell CNXK BPHY\n+M: Jakub Palider <jpalider@marvell.com>\n+M: Tomasz Duszynski <tduszynski@marvell.com>\n+F: doc/guides/rawdevs/cnxk_bphy.rst\n+F: drivers/raw/cnxk_bphy/\n+\n Marvell OCTEON TX2 DMA\n M: Radha Mohan Chintakuntla <radhac@marvell.com>\n M: Veerasenareddy Burru <vburru@marvell.com>\n@@ -1307,7 +1313,6 @@ F: doc/guides/rawdevs/ntb.rst\n F: examples/ntb/\n F: doc/guides/sample_app_ug/ntb.rst\n \n-\n Packet processing\n -----------------\n \ndiff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst\nindex cebb3d08a..a6ba42249 100644\n--- a/doc/guides/platform/cnxk.rst\n+++ b/doc/guides/platform/cnxk.rst\n@@ -145,6 +145,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.\n #. **Mempool Driver**\n See :doc:`../mempool/cnxk` for NPA mempool driver information.\n \n+#. **Baseband PHY Driver**\n+ See :doc:`../rawdevs/cnxk_bphy` for Baseband PHY driver information.\n+\n Procedure to Setup Platform\n ---------------------------\n \ndiff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst\nnew file mode 100644\nindex 000000000..96ab68435\n--- /dev/null\n+++ b/doc/guides/rawdevs/cnxk_bphy.rst\n@@ -0,0 +1,23 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2021 Marvell.\n+\n+Marvell CNXK BPHY Driver\n+========================\n+\n+CN10K/CN9K Fusion product families offer an internal BPHY unit which provides\n+set of hardware accelerators for performing baseband related operations.\n+Connectivity to the outside world happens through a block called RFOE which is\n+backed by ethernet I/O block called CGX or RPM (depending on the chip version).\n+RFOE stands for Radio Frequency Over Ethernet and provides support for\n+IEEE 1904.3 (RoE) standard.\n+\n+Device Setup\n+------------\n+\n+The BPHY CGX/RPM devices will need to be bound to a user-space IO driver for\n+use. The script ``dpdk-devbind.py`` script included with DPDK can be used to\n+view the state of the devices and to bind them to a suitable DPDK-supported\n+kernel driver. When querying the status of the devices, they will appear under\n+the category of \"Misc (rawdev) devices\", i.e. the command\n+``dpdk-devbind.py --status-dev misc`` can be used to see the state of those\n+devices alone.\ndiff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst\nindex f64ec4427..7fbae40ea 100644\n--- a/doc/guides/rawdevs/index.rst\n+++ b/doc/guides/rawdevs/index.rst\n@@ -11,6 +11,7 @@ application through rawdev API.\n :maxdepth: 2\n :numbered:\n \n+ cnxk_bphy\n dpaa2_cmdif\n dpaa2_qdma\n ifpga\ndiff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst\nindex a6ecfdf3c..d3f4d6847 100644\n--- a/doc/guides/rel_notes/release_21_08.rst\n+++ b/doc/guides/rel_notes/release_21_08.rst\n@@ -55,6 +55,13 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added Baseband phy CNXK PMD.**\n+\n+ Added Baseband phy PMD which allows to configure BPHY hardware block\n+ comprising accelerators and DSPs specifically tailored for 5G/LTE inline\n+ usecases. Configuration happens via standard rawdev enq/deq operations. See\n+ the :doc:`../rawdevs/cnxk_bphy` rawdev guide for more details on this driver.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\nnew file mode 100644\nindex 000000000..e537888f9\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n@@ -0,0 +1,151 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#include <rte_bus_pci.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include <roc_api.h>\n+\n+struct cnxk_bphy_cgx_queue {\n+\tunsigned int lmac;\n+\t/* queue holds up to one response */\n+\tvoid *rsp;\n+};\n+\n+struct cnxk_bphy_cgx {\n+\tstruct roc_bphy_cgx *rcgx;\n+\tstruct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX];\n+\tunsigned int num_queues;\n+};\n+\n+static void\n+cnxk_bphy_cgx_format_name(char *name, unsigned int len,\n+\t\t\t struct rte_pci_device *pci_dev)\n+{\n+\tsnprintf(name, len, \"BPHY_CGX:%x:%02x.%x\", pci_dev->addr.bus,\n+\t\t pci_dev->addr.devid, pci_dev->addr.function);\n+}\n+\n+static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {\n+};\n+\n+static void\n+cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx)\n+{\n+\tstruct roc_bphy_cgx *rcgx = cgx->rcgx;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < RTE_DIM(cgx->queues); i++) {\n+\t\tif (!(rcgx->lmac_bmap & BIT_ULL(i)))\n+\t\t\tcontinue;\n+\n+\t\tcgx->queues[cgx->num_queues++].lmac = i;\n+\t}\n+}\n+\n+static void\n+cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < cgx->num_queues; i++) {\n+\t\tif (cgx->queues[i].rsp)\n+\t\t\trte_free(cgx->queues[i].rsp);\n+\t}\n+\n+\tcgx->num_queues = 0;\n+}\n+\n+static int\n+cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv,\n+\t\t\t struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *rawdev;\n+\tstruct cnxk_bphy_cgx *cgx;\n+\tstruct roc_bphy_cgx *rcgx;\n+\tint ret;\n+\n+\tRTE_SET_USED(pci_drv);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (!pci_dev->mem_resource[0].addr)\n+\t\treturn -ENODEV;\n+\n+\tret = roc_plt_init();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tcnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);\n+\trawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id());\n+\tif (!rawdev)\n+\t\treturn -ENOMEM;\n+\n+\trawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops;\n+\trawdev->device = &pci_dev->device;\n+\trawdev->driver_name = pci_dev->driver->driver.name;\n+\n+\tcgx = rawdev->dev_private;\n+\tcgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0);\n+\tif (!cgx->rcgx) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out_pmd_release;\n+\t}\n+\n+\trcgx = cgx->rcgx;\n+\trcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr;\n+\trcgx->bar0_va = pci_dev->mem_resource[0].addr;\n+\tret = roc_bphy_cgx_dev_init(rcgx);\n+\tif (ret)\n+\t\tgoto out_free;\n+\n+\tcnxk_bphy_cgx_init_queues(cgx);\n+\n+\treturn 0;\n+out_free:\n+\trte_free(rcgx);\n+out_pmd_release:\n+\trte_rawdev_pmd_release(rawdev);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *rawdev;\n+\tstruct cnxk_bphy_cgx *cgx;\n+\n+\tcnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);\n+\trawdev = rte_rawdev_pmd_get_named_dev(name);\n+\tif (!rawdev)\n+\t\treturn -ENODEV;\n+\n+\tcgx = rawdev->dev_private;\n+\tcnxk_bphy_cgx_fini_queues(cgx);\n+\troc_bphy_cgx_dev_fini(cgx->rcgx);\n+\trte_free(cgx->rcgx);\n+\n+\treturn rte_rawdev_pmd_release(rawdev);\n+}\n+\n+static const struct rte_pci_id cnxk_bphy_cgx_map[] = {\n+\t{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)},\n+\t{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)},\n+\t{} /* sentinel */\n+};\n+\n+static struct rte_pci_driver bphy_cgx_rawdev_pmd = {\n+\t.id_table = cnxk_bphy_cgx_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = cnxk_bphy_cgx_rawdev_probe,\n+\t.remove = cnxk_bphy_cgx_rawdev_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map);\n+RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, \"vfio-pci\");\ndiff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build\nnew file mode 100644\nindex 000000000..78d8081fe\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/meson.build\n@@ -0,0 +1,8 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2021 Marvell.\n+#\n+\n+deps += ['bus_pci', 'common_cnxk', 'rawdev']\n+sources = files(\n+ 'cnxk_bphy_cgx.c',\n+)\ndiff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map\nnew file mode 100644\nindex 000000000..4a76d1d52\n--- /dev/null\n+++ b/drivers/raw/cnxk_bphy/version.map\n@@ -0,0 +1,3 @@\n+DPDK_21 {\n+\tlocal: *;\n+};\ndiff --git a/drivers/raw/meson.build b/drivers/raw/meson.build\nindex c33a7c5f3..b51536f8a 100644\n--- a/drivers/raw/meson.build\n+++ b/drivers/raw/meson.build\n@@ -6,6 +6,7 @@ if is_windows\n endif\n \n drivers = [\n+ 'cnxk_bphy',\n 'dpaa2_cmdif',\n 'dpaa2_qdma',\n 'ifpga',\ndiff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py\nindex 2fe0c6a6a..55a73961d 100755\n--- a/usertools/dpdk-devbind.py\n+++ b/usertools/dpdk-devbind.py\n@@ -45,6 +45,8 @@\n 'SVendor': None, 'SDevice': None}\n octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',\n 'SVendor': None, 'SDevice': None}\n+cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',\n+ 'SVendor': None, 'SDevice': None}\n \n intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714',\n 'SVendor': None, 'SDevice': None}\n@@ -69,7 +71,7 @@\n mempool_devices = [cavium_fpa, octeontx2_npa]\n compress_devices = [cavium_zip]\n regex_devices = [octeontx2_ree]\n-misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,\n+misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,\n intel_ntb_skx, intel_ntb_icx,\n octeontx2_dma]\n \n", "prefixes": [ "v3", "09/32" ] }