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GET /api/patches/94631/?format=api
{ "id": 94631, "url": "https://patches.dpdk.org/api/patches/94631/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-7-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-7-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-7-tduszynski@marvell.com", "date": "2021-06-21T15:04:23", "name": "[v3,06/32] common/cnxk: support for setting link mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "040a7ceed90d3ce84a79cc36e4b347d322748a58", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-7-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94631/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94631/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 148E7A0547;\n\tMon, 21 Jun 2021 17:05:51 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A566F411E9;\n\tMon, 21 Jun 2021 17:05:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C061B411BF\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:05:22 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LF5D0a008464; Mon, 21 Jun 2021 08:05:19 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xj9y4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:05:19 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:05:18 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:05:18 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id A9E1D3F7070;\n Mon, 21 Jun 2021 08:05:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Akdhjv3JiGm3Iz5HpXsKCJK3+YpC6rfgQiiLgO1pzJQ=;\n b=OF5lnvUIQTtOfXJ3spOfAp9D+sHN0DOUWfU7H5LbHQwcmlGLBNXUvP3P7MALz0r59feo\n u+uBDmfz1sqLvZaBKdBx+8pRriG2nojJCXd+2C0BaEA6n9UJXwpSIlfIlzqtqGzo1vAE\n oWtH2vugpZx8JwnlCX4CmCMbDKTwLhPZXA3PLPyUy57Wkr9cEdbWmkHkQ/CaRFXShG6O\n Knv2Mgdsgeqr10zKCnVUnDU8VNaJjz7hbpwSBVDqrrSXNjhYwf78T5C+Al9aeSlPxAkB\n CsVxaLg+UYoZYqjIZ66+d+u3Ya1lr1uY9ttIzXhEcLuOo1fZwmWELJvNfxuvQAkew7dX uA==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, Neil Horman\n <nhorman@tuxdriver.com>", "CC": "<thomas@monjalon.net>, <dev@dpdk.org>, Tomasz Duszynski\n <tduszynski@marvell.com>, Jakub Palider <jpalider@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:23 +0200", "Message-ID": "<20210621150449.19070-7-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "erXSH9tCRP-R3w7ZIkGF_duB-6l2xNNX", "X-Proofpoint-ORIG-GUID": "erXSH9tCRP-R3w7ZIkGF_duB-6l2xNNX", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 06/32] common/cnxk: support for setting link\n mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for setting link mode.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/roc_bphy_cgx.c | 28 ++++++++++++\n drivers/common/cnxk/roc_bphy_cgx.h | 11 +++++\n drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 1 +\n 4 files changed, 101 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nindex a2da80284..09d988b1b 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.c\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -284,6 +284,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n \treturn 0;\n }\n \n+int\n+roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t struct roc_bphy_cgx_link_mode *mode)\n+{\n+\tuint64_t scr1, scr0;\n+\n+\tif (roc_model_is_cn10k())\n+\t\treturn -ENOTSUP;\n+\n+\tif (!roc_cgx)\n+\t\treturn -EINVAL;\n+\n+\tif (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))\n+\t\treturn -ENODEV;\n+\n+\tif (!mode)\n+\t\treturn -EINVAL;\n+\n+\tscr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));\n+\n+\treturn roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\n+}\n+\n int\n roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)\n {\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nindex 992e2d3ed..b9a6e0be0 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {\n \t__ROC_BPHY_CGX_ETH_LINK_MODE_MAX\n };\n \n+struct roc_bphy_cgx_link_mode {\n+\tbool full_duplex;\n+\tbool an;\n+\tunsigned int port;\n+\tenum roc_bphy_cgx_eth_link_speed speed;\n+\tenum roc_bphy_cgx_eth_link_mode mode;\n+};\n+\n struct roc_bphy_cgx_link_info {\n \tbool link_up;\n \tbool full_duplex;\n@@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);\n __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,\n \t\t\t\t\tunsigned int lmac,\n \t\t\t\t\tstruct roc_bphy_cgx_link_info *info);\n+__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,\n+\t\t\t\t\t unsigned int lmac,\n+\t\t\t\t\t struct roc_bphy_cgx_link_mode *mode);\n __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,\n \t\t\t\t\t unsigned int lmac);\n __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h\nindex 4e86ae4ea..ee7578423 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h\n@@ -5,10 +5,64 @@\n #ifndef _ROC_BPHY_CGX_PRIV_H_\n #define _ROC_BPHY_CGX_PRIV_H_\n \n+/* LINK speed types */\n+enum eth_link_speed {\n+\tETH_LINK_NONE,\n+\tETH_LINK_10M,\n+\tETH_LINK_100M,\n+\tETH_LINK_1G,\n+\tETH_LINK_2HG, /* 2.5 Gbps */\n+\tETH_LINK_5G,\n+\tETH_LINK_10G,\n+\tETH_LINK_20G,\n+\tETH_LINK_25G,\n+\tETH_LINK_40G,\n+\tETH_LINK_50G,\n+\tETH_LINK_80G,\n+\tETH_LINK_100G,\n+\tETH_LINK_MAX,\n+};\n+\n+/* Supported LINK MODE enums\n+ * Each link mode is a bit mask of these\n+ * enums which are represented as bits\n+ */\n+enum eth_mode {\n+\tETH_MODE_SGMII_BIT = 0,\n+\tETH_MODE_1000_BASEX_BIT,\n+\tETH_MODE_QSGMII_BIT,\n+\tETH_MODE_10G_C2C_BIT,\n+\tETH_MODE_10G_C2M_BIT,\n+\tETH_MODE_10G_KR_BIT, /* = 5 */\n+\tETH_MODE_20G_C2C_BIT,\n+\tETH_MODE_25G_C2C_BIT,\n+\tETH_MODE_25G_C2M_BIT,\n+\tETH_MODE_25G_2_C2C_BIT,\n+\tETH_MODE_25G_CR_BIT, /* = 10 */\n+\tETH_MODE_25G_KR_BIT,\n+\tETH_MODE_40G_C2C_BIT,\n+\tETH_MODE_40G_C2M_BIT,\n+\tETH_MODE_40G_CR4_BIT,\n+\tETH_MODE_40G_KR4_BIT, /* = 15 */\n+\tETH_MODE_40GAUI_C2C_BIT,\n+\tETH_MODE_50G_C2C_BIT,\n+\tETH_MODE_50G_C2M_BIT,\n+\tETH_MODE_50G_4_C2C_BIT,\n+\tETH_MODE_50G_CR_BIT, /* = 20 */\n+\tETH_MODE_50G_KR_BIT,\n+\tETH_MODE_80GAUI_C2C_BIT,\n+\tETH_MODE_100G_C2C_BIT,\n+\tETH_MODE_100G_C2M_BIT,\n+\tETH_MODE_100G_CR4_BIT, /* = 25 */\n+\tETH_MODE_100G_KR4_BIT,\n+\tETH_MODE_MAX_BIT /* = 27 */\n+};\n+\n /* REQUEST ID types. Input to firmware */\n enum eth_cmd_id {\n \tETH_CMD_GET_LINK_STS = 4,\n \tETH_CMD_INTERNAL_LBK = 7,\n+\tETH_CMD_MODE_CHANGE = 11, /* hot plug support */\n \tETH_CMD_INTF_SHUTDOWN = 12,\n \tETH_CMD_SET_PTP_MODE = 34,\n };\n@@ -63,6 +117,13 @@ enum eth_cmd_own {\n /* struct eth_ctl_args */\n #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)\n \n+/* struct eth_mode_change_args */\n+#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED\t GENMASK_ULL(11, 8)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_AN\t BIT_ULL(13)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_PORT\t GENMASK_ULL(21, 14)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE\t GENMASK_ULL(63, 22)\n+\n #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)\n \n #endif /* _ROC_BPHY_CGX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 205a0602b..15a6d3a3b 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -16,6 +16,7 @@ INTERNAL {\n \troc_bphy_cgx_intlbk_enable;\n \troc_bphy_cgx_ptp_rx_disable;\n \troc_bphy_cgx_ptp_rx_enable;\n+\troc_bphy_cgx_set_link_mode;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n", "prefixes": [ "v3", "06/32" ] }