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GET /api/patches/94627/?format=api
{ "id": 94627, "url": "https://patches.dpdk.org/api/patches/94627/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-2-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-2-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-2-tduszynski@marvell.com", "date": "2021-06-21T15:04:18", "name": "[v3,01/32] common/cnxk: add bphy cgx/rpm initialization and cleanup", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8915a4e66372c3d68968a23efa21bedd521ff2bd", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-2-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94627/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6742EA0547;\n\tMon, 21 Jun 2021 17:05:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A1E1B411CC;\n\tMon, 21 Jun 2021 17:05:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7E1E6411B9\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:05:16 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LF5D0T008464; Mon, 21 Jun 2021 08:05:13 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xj9wt-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:05:13 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:05:03 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:05:03 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id A287B3F7075;\n Mon, 21 Jun 2021 08:05:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=YDa7JqGrb6mL6+PIaKe9HSyWYi1/mzYCKpNL18QNOjM=;\n b=ibaLgX/3xJop41JIAvg2d6HppfueR8IRxt+LETBwERR+/M//HkSfLaXIu6zOnseTVAci\n BrSy/A7ABVs2HzRxwbe6IKuz/kHfH3sdismXu0WASa9zOEF1FhWQr9gHEy8StCTHkFis\n qz2dYMU4k3cH5+BvfPuc0GI7dmsPlILe9dr/CqI9laaKDOg5fUMbXmWe2QtZ8F7Cq8+m\n 3HPRGJkKn29H8Qslw9OtdrLSyZcafZMG7vhjjyLip16Vwq/dVSy1wa3nGgl8Soyu7LbO\n 25I3dfj9AyofbejbXtAttPPqkakaHqAOXceAl7oR7q7J3w/TUzgXZon4LgUCmlLOqMRo yw==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, Neil Horman\n <nhorman@tuxdriver.com>", "CC": "<thomas@monjalon.net>, <dev@dpdk.org>, Tomasz Duszynski\n <tduszynski@marvell.com>, Jakub Palider <jpalider@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:18 +0200", "Message-ID": "<20210621150449.19070-2-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Hq81RE_8qSmEs_MM2NMHubWJG8u-jFgp", "X-Proofpoint-ORIG-GUID": "Hq81RE_8qSmEs_MM2NMHubWJG8u-jFgp", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 01/32] common/cnxk: add bphy cgx/rpm\n initialization and cleanup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for low level initialization and cleanup of baseband\nphy cgx/rpm blocks.\n\nInitialization and cleanup are related hence are in the same patch.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 ++\n drivers/common/cnxk/roc_bphy_cgx.c | 62 ++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_bphy_cgx.h | 20 ++++++++++\n drivers/common/cnxk/version.map | 2 +\n 5 files changed, 88 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c\n create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 178bce7ab..59975fd34 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -11,6 +11,7 @@ endif\n config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'\n deps = ['eal', 'pci', 'bus_pci', 'mbuf']\n sources = files(\n+ 'roc_bphy_cgx.c',\n 'roc_dev.c',\n 'roc_idev.c',\n 'roc_irq.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 67f5d13f0..256d8c68d 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -100,4 +100,7 @@\n /* Idev */\n #include \"roc_idev.h\"\n \n+/* Baseband phy cgx */\n+#include \"roc_bphy_cgx.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nnew file mode 100644\nindex 000000000..029d4102e\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+\n+/*\n+ * CN10K stores number of lmacs in 4 bit filed\n+ * in contraty to CN9K which uses only 3 bits.\n+ *\n+ * In theory masks should differ yet on CN9K\n+ * bits beyond specified range contain zeros.\n+ *\n+ * Hence common longer mask may be used.\n+ */\n+#define CGX_CMRX_RX_LMACS\t0x128\n+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)\n+\n+static uint64_t\n+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)\n+{\n+\tint shift = roc_model_is_cn10k() ? 20 : 18;\n+\tuint64_t base = (uint64_t)roc_cgx->bar0_va;\n+\n+\treturn plt_read64(base + (lmac << shift) + offset);\n+}\n+\n+static unsigned int\n+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)\n+{\n+\tuint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :\n+\t\t\t\t\t\t GENMASK_ULL(25, 24);\n+\n+\treturn FIELD_GET(cgx_id, roc_cgx->bar0_pa);\n+}\n+\n+int\n+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)\n+{\n+\tuint64_t val;\n+\n+\tif (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)\n+\t\treturn -EINVAL;\n+\n+\tval = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);\n+\tval = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);\n+\tif (roc_model_is_cn9k())\n+\t\tval = GENMASK_ULL(val - 1, 0);\n+\troc_cgx->lmac_bmap = val;\n+\troc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)\n+{\n+\tif (!roc_cgx)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nnew file mode 100644\nindex 000000000..aac2c262c\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_BPHY_CGX_H_\n+#define _ROC_BPHY_CGX_H_\n+\n+#include \"roc_api.h\"\n+\n+struct roc_bphy_cgx {\n+\tuint64_t bar0_pa;\n+\tvoid *bar0_va;\n+\tuint64_t lmac_bmap;\n+\tunsigned int id;\n+} __plt_cache_aligned;\n+\n+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);\n+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);\n+\n+#endif /* _ROC_BPHY_CGX_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 8e67c83a6..1db4d104a 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -9,6 +9,8 @@ INTERNAL {\n \tcnxk_logtype_sso;\n \tcnxk_logtype_tim;\n \tcnxk_logtype_tm;\n+\troc_bphy_cgx_dev_fini;\n+\troc_bphy_cgx_dev_init;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n", "prefixes": [ "v3", "01/32" ] }