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GET /api/patches/94626/?format=api
{ "id": 94626, "url": "https://patches.dpdk.org/api/patches/94626/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-3-tduszynski@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621150449.19070-3-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621150449.19070-3-tduszynski@marvell.com", "date": "2021-06-21T15:04:19", "name": "[v3,02/32] common/cnxk: support for communication with atf", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f72be99e9379659f7b6eddd93755759b81d3db59", "submitter": { "id": 2215, "url": "https://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621150449.19070-3-tduszynski@marvell.com/mbox/", "series": [ { "id": 17426, "url": "https://patches.dpdk.org/api/series/17426/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17426", "date": "2021-06-21T15:04:17", "name": "add support for baseband phy", "version": 3, "mbox": "https://patches.dpdk.org/series/17426/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94626/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94626/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 42EC9A0547;\n\tMon, 21 Jun 2021 17:05:16 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3161B41199;\n\tMon, 21 Jun 2021 17:05:16 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id AC49440040\n for <dev@dpdk.org>; Mon, 21 Jun 2021 17:05:14 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15LF5D0U008464; Mon, 21 Jun 2021 08:05:13 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xj9wt-5\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 21 Jun 2021 08:05:13 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 21 Jun 2021 08:05:05 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 21 Jun 2021 08:05:05 -0700", "from EH-LT0048.marvell.com (unknown [10.193.32.52])\n by maili.marvell.com (Postfix) with ESMTP id B95D13F705B;\n Mon, 21 Jun 2021 08:05:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=I7T8dFB1anB1PVwVddRxdbOxicxBkT8YzYigzHV9hr4=;\n b=VqZYUbkPQIXtzSjtc/MasZWiUsBejs/kW7OEjf40qTwRgdF5BWFa1rtpyDEpUpDZ7LWg\n b+HW0lpke66EPr9aa7yL/kYFW48VtXHKb2PfGnCEqJjsJ3E6LeL4lUYb7nCujDbIPO2e\n jH3KGYR904UDKIg67hS72Iaz+GOmARinY6nCql1m5zPZeDUBLkpBrNdaZsRXJaxw5jed\n qOE2oKgq7pG+Q2TlZUu0KgoeXApMI2C0hlL50FBXiDgJMCdLTpwejrfE9PDf/gpjH6ZA\n BypU/eGYRQT4hhxaVrjfhT7isiMTYDPsOxFvadBYe8SWKgs2wshP0obtw1OThDB2R/BC TA==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<thomas@monjalon.net>, <dev@dpdk.org>, Tomasz Duszynski\n <tduszynski@marvell.com>, Jakub Palider <jpalider@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>", "Date": "Mon, 21 Jun 2021 17:04:19 +0200", "Message-ID": "<20210621150449.19070-3-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621150449.19070-1-tduszynski@marvell.com>", "References": "<20210531214142.30167-1-tduszynski@marvell.com>\n <20210621150449.19070-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "aKGUFlBqwLA3bY5VYUHap8bW1LmMYvcF", "X-Proofpoint-ORIG-GUID": "aKGUFlBqwLA3bY5VYUHap8bW1LmMYvcF", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-21_06:2021-06-21,\n 2021-06-21 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 02/32] common/cnxk: support for communication\n with atf", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Messages can be exchanged between userspace software and firmware\nvia set of two dedicated registers, namely scratch1 and scratch0.\n\nscratch1 acts as a command register i.e message is sent to firmware,\nwhile scratch0 holds response to previously sent message.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/roc_bphy_cgx.c | 146 ++++++++++++++++++++++++\n drivers/common/cnxk/roc_bphy_cgx.h | 4 +\n drivers/common/cnxk/roc_bphy_cgx_priv.h | 54 +++++++++\n drivers/common/cnxk/roc_priv.h | 3 +\n 4 files changed, 207 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h", "diff": "diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nindex 029d4102e..7fedf5462 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.c\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -2,8 +2,13 @@\n * Copyright(C) 2021 Marvell.\n */\n \n+#include <pthread.h>\n+\n #include \"roc_api.h\"\n+#include \"roc_priv.h\"\n \n+#define CGX_CMRX_INT\t\t 0x40\n+#define CGX_CMRX_INT_OVERFLW\t BIT_ULL(1)\n /*\n * CN10K stores number of lmacs in 4 bit filed\n * in contraty to CN9K which uses only 3 bits.\n@@ -15,6 +20,8 @@\n */\n #define CGX_CMRX_RX_LMACS\t0x128\n #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)\n+#define CGX_CMRX_SCRATCH0\t0x1050\n+#define CGX_CMRX_SCRATCH1\t0x1058\n \n static uint64_t\n roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)\n@@ -25,6 +32,138 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)\n \treturn plt_read64(base + (lmac << shift) + offset);\n }\n \n+static void\n+roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,\n+\t\t uint64_t value)\n+{\n+\tint shift = roc_model_is_cn10k() ? 20 : 18;\n+\tuint64_t base = (uint64_t)roc_cgx->bar0_va;\n+\n+\tplt_write64(value, base + (lmac << shift) + offset);\n+}\n+\n+static void\n+roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t uint64_t *scr0)\n+{\n+\tuint64_t val;\n+\n+\t/* clear interrupt */\n+\tval = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);\n+\tval |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);\n+\troc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);\n+\n+\t/* ack fw response */\n+\t*scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;\n+\troc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);\n+}\n+\n+static int\n+roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t\tuint64_t *scr0)\n+{\n+\tint tries = 5000;\n+\tuint64_t scr1;\n+\n+\tdo {\n+\t\t*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);\n+\t\tscr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);\n+\n+\t\tif (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&\n+\t\t FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)\n+\t\t\tbreak;\n+\n+\t\t/* clear async events if any */\n+\t\tif (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==\n+\t\t ETH_EVT_ASYNC &&\n+\t\t FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))\n+\t\t\troc_bphy_cgx_ack(roc_cgx, lmac, scr0);\n+\n+\t\tplt_delay_ms(1);\n+\t} while (--tries);\n+\n+\treturn tries ? 0 : -ETIMEDOUT;\n+}\n+\n+static int\n+roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t uint64_t *scr0)\n+{\n+\tint tries = 5000;\n+\tuint64_t scr1;\n+\n+\tdo {\n+\t\t*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);\n+\t\tscr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);\n+\n+\t\tif (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&\n+\t\t FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))\n+\t\t\tbreak;\n+\n+\t\tplt_delay_ms(1);\n+\t} while (--tries);\n+\n+\treturn tries ? 0 : -ETIMEDOUT;\n+}\n+\n+static int __rte_unused\n+roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t uint64_t scr1, uint64_t *scr0)\n+{\n+\tuint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);\n+\tint ret;\n+\n+\tpthread_mutex_lock(&roc_cgx->lock);\n+\n+\t/* wait for ownership */\n+\tret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);\n+\tif (ret) {\n+\t\tplt_err(\"timed out waiting for ownership\");\n+\t\tgoto out;\n+\t}\n+\n+\t/* write command */\n+\tscr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);\n+\troc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);\n+\n+\t/* wait for command ack */\n+\tret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);\n+\tif (ret) {\n+\t\tplt_err(\"timed out waiting for response\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (cmd_id == ETH_CMD_INTF_SHUTDOWN)\n+\t\tgoto out;\n+\n+\tif (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {\n+\t\tplt_err(\"received async event instead of cmd resp event\");\n+\t\tret = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+\tif (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {\n+\t\tplt_err(\"received resp for cmd %d expected for cmd %d\",\n+\t\t\t(int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);\n+\t\tret = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+\tif (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {\n+\t\tplt_err(\"cmd %d failed on cgx%u lmac%u with errcode %d\", cmd_id,\n+\t\t\troc_cgx->id, lmac,\n+\t\t\t(int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));\n+\t\tret = -EIO;\n+\t}\n+\n+out:\n+\troc_bphy_cgx_ack(roc_cgx, lmac, scr0);\n+\n+\tpthread_mutex_unlock(&roc_cgx->lock);\n+\n+\treturn ret;\n+}\n+\n static unsigned int\n roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)\n {\n@@ -38,10 +177,15 @@ int\n roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)\n {\n \tuint64_t val;\n+\tint ret;\n \n \tif (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)\n \t\treturn -EINVAL;\n \n+\tret = pthread_mutex_init(&roc_cgx->lock, NULL);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tval = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);\n \tval = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);\n \tif (roc_model_is_cn9k())\n@@ -58,5 +202,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)\n \tif (!roc_cgx)\n \t\treturn -EINVAL;\n \n+\tpthread_mutex_destroy(&roc_cgx->lock);\n+\n \treturn 0;\n }\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nindex aac2c262c..37b5c2742 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -5,6 +5,8 @@\n #ifndef _ROC_BPHY_CGX_H_\n #define _ROC_BPHY_CGX_H_\n \n+#include <pthread.h>\n+\n #include \"roc_api.h\"\n \n struct roc_bphy_cgx {\n@@ -12,6 +14,8 @@ struct roc_bphy_cgx {\n \tvoid *bar0_va;\n \tuint64_t lmac_bmap;\n \tunsigned int id;\n+\t/* serialize access to the whole structure */\n+\tpthread_mutex_t lock;\n } __plt_cache_aligned;\n \n __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h\nnew file mode 100644\nindex 000000000..42d0bce7a\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h\n@@ -0,0 +1,54 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_BPHY_CGX_PRIV_H_\n+#define _ROC_BPHY_CGX_PRIV_H_\n+\n+/* REQUEST ID types. Input to firmware */\n+enum eth_cmd_id {\n+\tETH_CMD_INTF_SHUTDOWN = 12,\n+};\n+\n+/* event types - cause of interrupt */\n+enum eth_evt_type {\n+\tETH_EVT_ASYNC,\n+\tETH_EVT_CMD_RESP,\n+};\n+\n+enum eth_stat {\n+\tETH_STAT_SUCCESS,\n+\tETH_STAT_FAIL,\n+};\n+\n+enum eth_cmd_own {\n+\t/* default ownership with kernel/uefi/u-boot */\n+\tETH_OWN_NON_SECURE_SW,\n+\t/* set by kernel/uefi/u-boot after posting a new request to ATF */\n+\tETH_OWN_FIRMWARE,\n+};\n+\n+/* scratchx(0) CSR used for ATF->non-secure SW communication.\n+ * This acts as the status register\n+ * Provides details on command ack/status, link status, error details\n+ */\n+\n+/* struct eth_evt_sts_s */\n+#define SCR0_ETH_EVT_STS_S_ACK\t BIT_ULL(0)\n+#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)\n+#define SCR0_ETH_EVT_STS_S_STAT\t BIT_ULL(2)\n+#define SCR0_ETH_EVT_STS_S_ID\t GENMASK_ULL(8, 3)\n+\n+/* struct eth_lnk_sts_s */\n+#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)\n+\n+/* scratchx(1) CSR used for non-secure SW->ATF communication\n+ * This CSR acts as a command register\n+ */\n+\n+/* struct eth_cmd */\n+#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)\n+\n+#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)\n+\n+#endif /* _ROC_BPHY_CGX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 5e7564ce5..feca732a9 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -32,4 +32,7 @@\n /* TIM */\n #include \"roc_tim_priv.h\"\n \n+/* BPHY CGX */\n+#include \"roc_bphy_cgx_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\n", "prefixes": [ "v3", "02/32" ] }