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GET /api/patches/94610/?format=api
{ "id": 94610, "url": "https://patches.dpdk.org/api/patches/94610/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621075206.4020456-11-robinx.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210621075206.4020456-11-robinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210621075206.4020456-11-robinx.zhang@intel.com", "date": "2021-06-21T07:52:01", "name": "[v3,10/15] net/i40e/base: add flags and fields for double vlan processing", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "db805d81b032082eb63240c984d3b16eae157241", "submitter": { "id": 2004, "url": "https://patches.dpdk.org/api/people/2004/?format=api", "name": "Robin Zhang", "email": "robinx.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621075206.4020456-11-robinx.zhang@intel.com/mbox/", "series": [ { "id": 17420, "url": "https://patches.dpdk.org/api/series/17420/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17420", "date": "2021-06-21T07:51:52", "name": "i40e base code update", "version": 3, "mbox": "https://patches.dpdk.org/series/17420/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94610/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94610/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B9CB6A0547;\n\tMon, 21 Jun 2021 10:03:39 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 42AD6411C9;\n\tMon, 21 Jun 2021 10:03:02 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 3C516411BE\n for <dev@dpdk.org>; Mon, 21 Jun 2021 10:03:01 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jun 2021 01:03:00 -0700", "from unknown (HELO intel-npg-odc-srv03.cd.intel.com)\n ([10.240.178.145])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jun 2021 01:02:58 -0700" ], "IronPort-SDR": [ "\n 3FfgDuEKgFvpsGLhOl6CQZaVDhoVMPF0/5yYYnBBFYdwhDsWeAs8sCzcXRWzqTYgPZr6EzzkvR\n iqYSnQXUyaLw==", "\n jV1rYlqQ+A3/0BPVEpLYSTG+qGB3iXUbD1fwOxPZBcoFMr8jXk4K3/NMh+JLbdY4sMaMtD4Z2c\n yXL2lG+TfHaA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10021\"; a=\"270643245\"", "E=Sophos;i=\"5.83,289,1616482800\"; d=\"scan'208\";a=\"270643245\"", "E=Sophos;i=\"5.83,289,1616482800\"; d=\"scan'208\";a=\"452101994\"" ], "From": "Robin Zhang <robinx.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "beilei.xing@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com,\n Robin Zhang <robinx.zhang@intel.com>,\n Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>", "Date": "Mon, 21 Jun 2021 07:52:01 +0000", "Message-Id": "<20210621075206.4020456-11-robinx.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210621075206.4020456-1-robinx.zhang@intel.com>", "References": "<20210618063851.3694702-1-robinx.zhang@intel.com>\n <20210621075206.4020456-1-robinx.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 10/15] net/i40e/base: add flags and fields for\n double vlan processing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add flags for outer vlan and include set port parameters in Linux\ncompilation.\nAdd flags, which describe port and switch state for both double vlan\nfunctionality and outer vlan processing.\n\nSigned-off-by: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com>\nSigned-off-by: Robin Zhang <robinx.zhang@intel.com>\n---\n drivers/net/i40e/base/i40e_adminq_cmd.h | 22 ++++++++++++++++++++--\n 1 file changed, 20 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h\nindex 1aafe1de38..646cfd0398 100644\n--- a/drivers/net/i40e/base/i40e_adminq_cmd.h\n+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h\n@@ -768,6 +768,7 @@ struct i40e_aqc_set_switch_config {\n #define I40E_AQ_SET_SWITCH_CFG_PROMISC\t\t0x0001\n #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER\t0x0002\n #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT\t0x0004\n+#define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN\t0x0008\n \t__le16\tvalid_flags;\n \t/* The ethertype in switch_tag is dropped on ingress and used\n \t * internally by the switch. Set this to zero for the default\n@@ -904,7 +905,7 @@ struct i40e_aqc_vsi_properties_data {\n \tu8\tsec_reserved;\n \t/* VLAN section */\n \t__le16\tpvid; /* VLANS include priority bits */\n-\t__le16\tfcoe_pvid;\n+\t__le16\touter_vlan;\n \tu8\tport_vlan_flags;\n #define I40E_AQ_VSI_PVLAN_MODE_SHIFT\t0x00\n #define I40E_AQ_VSI_PVLAN_MODE_MASK\t(0x03 << \\\n@@ -920,7 +921,24 @@ struct i40e_aqc_vsi_properties_data {\n #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP\t0x08\n #define I40E_AQ_VSI_PVLAN_EMOD_STR\t0x10\n #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING\t0x18\n-\tu8\tpvlan_reserved[3];\n+\tu8\touter_vlan_flags;\n+#define I40E_AQ_VSI_OVLAN_MODE_SHIFT\t0x00\n+#define I40E_AQ_VSI_OVLAN_MODE_MASK\t(0x03 << \\\n+\t\t\t\t\t I40E_AQ_VSI_OVLAN_MODE_SHIFT)\n+#define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED\t0x01\n+#define I40E_AQ_VSI_OVLAN_MODE_TAGGED\t0x02\n+#define I40E_AQ_VSI_OVLAN_MODE_ALL\t0x03\n+#define I40E_AQ_VSI_OVLAN_INSERT_PVID\t0x04\n+#define I40E_AQ_VSI_OVLAN_EMOD_SHIFT\t0x03\n+#define I40E_AQ_VSI_OVLAN_EMOD_MASK\t(0x03 <<\\\n+\t\t\t\t\t I40E_AQ_VSI_OVLAN_EMOD_SHIFT)\n+#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL\t0x00\n+#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP\t0x01\n+#define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL\t0x02\n+#define I40E_AQ_VSI_OVLAN_EMOD_NOTHING\t0x03\n+#define I40E_AQ_VSI_OVLAN_CTRL_ENA\t0x04\n+\n+\tu8\tpvlan_reserved[2];\n \t/* ingress egress up sections */\n \t__le32\tingress_table; /* bitmap, 3 bits per up */\n #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT\t0\n", "prefixes": [ "v3", "10/15" ] }