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GET /api/patches/94605/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 94605,
    "url": "https://patches.dpdk.org/api/patches/94605/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210621075206.4020456-7-robinx.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210621075206.4020456-7-robinx.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210621075206.4020456-7-robinx.zhang@intel.com",
    "date": "2021-06-21T07:51:57",
    "name": "[v3,06/15] net/i40e/base: fix PHY type identifiers for 2.5G and 5G adapters",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "62c01f487c1ee51ae3aff60a457e3b6f6aff35ed",
    "submitter": {
        "id": 2004,
        "url": "https://patches.dpdk.org/api/people/2004/?format=api",
        "name": "Robin Zhang",
        "email": "robinx.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210621075206.4020456-7-robinx.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 17420,
            "url": "https://patches.dpdk.org/api/series/17420/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17420",
            "date": "2021-06-21T07:51:52",
            "name": "i40e base code update",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/17420/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/94605/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/94605/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9C317A0547;\n\tMon, 21 Jun 2021 10:03:02 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3829F411A4;\n\tMon, 21 Jun 2021 10:02:50 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 4087C4118D;\n Mon, 21 Jun 2021 10:02:48 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jun 2021 01:02:47 -0700",
            "from unknown (HELO intel-npg-odc-srv03.cd.intel.com)\n ([10.240.178.145])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jun 2021 01:02:43 -0700"
        ],
        "IronPort-SDR": [
            "\n N8hOeDb/1t+fg14kwAmu5xJF2pILuSGf7jmLFvndTw4HppoXcsIQm4j94IZXc9Exx+xMJwtHb/\n fnbgT3zmSeRg==",
            "\n e9r0int7bdBHQvOqCUzrIf4IGx4Prl/JH2M3cXem/IaGIm1Uo3InvT7RSG6UITZ6g448AQt34Q\n gfnUH6xG/Aww=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10021\"; a=\"270643215\"",
            "E=Sophos;i=\"5.83,289,1616482800\"; d=\"scan'208\";a=\"270643215\"",
            "E=Sophos;i=\"5.83,289,1616482800\"; d=\"scan'208\";a=\"452101894\""
        ],
        "From": "Robin Zhang <robinx.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "beilei.xing@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com,\n Robin Zhang <robinx.zhang@intel.com>, stable@dpdk.org,\n Dawid Lukwinski <dawid.lukwinski@intel.com>",
        "Date": "Mon, 21 Jun 2021 07:51:57 +0000",
        "Message-Id": "<20210621075206.4020456-7-robinx.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20210621075206.4020456-1-robinx.zhang@intel.com>",
        "References": "<20210618063851.3694702-1-robinx.zhang@intel.com>\n <20210621075206.4020456-1-robinx.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v3 06/15] net/i40e/base: fix PHY type identifiers\n for 2.5G and 5G adapters",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Unlike other supported adapters, 2.5G and 5G use different\nPHY type identifiers for reading/writing PHY settings\nand for reading link status. This commit intruduces\nseparate PHY identifiers for these two operation types.\n\nFixes: 988ed63c7441 (\"net/i40e/base: add support for Carlsville device\")\nCc: stable@dpdk.org\n\nSigned-off-by: Dawid Lukwinski <dawid.lukwinski@intel.com>\nSigned-off-by: Robin Zhang <robinx.zhang@intel.com>\n---\n drivers/net/i40e/base/i40e_adminq_cmd.h | 6 ++++--\n drivers/net/i40e/base/i40e_common.c     | 4 ++--\n drivers/net/i40e/base/i40e_type.h       | 8 ++------\n 3 files changed, 8 insertions(+), 10 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h\nindex a73a08aae6..1aafe1de38 100644\n--- a/drivers/net/i40e/base/i40e_adminq_cmd.h\n+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h\n@@ -1947,8 +1947,10 @@ enum i40e_aq_phy_type {\n \tI40E_PHY_TYPE_25GBASE_LR\t\t= 0x22,\n \tI40E_PHY_TYPE_25GBASE_AOC\t\t= 0x23,\n \tI40E_PHY_TYPE_25GBASE_ACC\t\t= 0x24,\n-\tI40E_PHY_TYPE_2_5GBASE_T\t\t= 0x30,\n-\tI40E_PHY_TYPE_5GBASE_T\t\t\t= 0x31,\n+\tI40E_PHY_TYPE_2_5GBASE_T\t\t= 0x26,\n+\tI40E_PHY_TYPE_5GBASE_T\t\t\t= 0x27,\n+\tI40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS\t= 0x30,\n+\tI40E_PHY_TYPE_5GBASE_T_LINK_STATUS\t= 0x31,\n \tI40E_PHY_TYPE_MAX,\n \tI40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP\t= 0xFD,\n \tI40E_PHY_TYPE_EMPTY\t\t\t= 0xFE,\ndiff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c\nindex 32642f3e2b..ceedec68bf 100644\n--- a/drivers/net/i40e/base/i40e_common.c\n+++ b/drivers/net/i40e/base/i40e_common.c\n@@ -1280,8 +1280,8 @@ STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)\n \t\tbreak;\n \tcase I40E_PHY_TYPE_100BASE_TX:\n \tcase I40E_PHY_TYPE_1000BASE_T:\n-\tcase I40E_PHY_TYPE_2_5GBASE_T:\n-\tcase I40E_PHY_TYPE_5GBASE_T:\n+\tcase I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:\n+\tcase I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:\n \tcase I40E_PHY_TYPE_10GBASE_T:\n \t\tmedia = I40E_MEDIA_TYPE_BASET;\n \t\tbreak;\ndiff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h\nindex e5a3729183..0323887550 100644\n--- a/drivers/net/i40e/base/i40e_type.h\n+++ b/drivers/net/i40e/base/i40e_type.h\n@@ -329,12 +329,8 @@ struct i40e_phy_info {\n \t\t\t\t\t     I40E_PHY_TYPE_OFFSET)\n #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \\\n \t\t\t\t\t     I40E_PHY_TYPE_OFFSET)\n-/* Offset for 2.5G/5G PHY Types value to bit number conversion */\n-#define I40E_PHY_TYPE_OFFSET2 (-10)\n-#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \\\n-\t\t\t\t\t     I40E_PHY_TYPE_OFFSET2)\n-#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \\\n-\t\t\t\t\t     I40E_PHY_TYPE_OFFSET2)\n+#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)\n+#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO\t\t0\n #define I40E_HW_CAP_MDIO_PORT_MODE_I2C\t\t1\n",
    "prefixes": [
        "v3",
        "06/15"
    ]
}