Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94595/?format=api
{ "id": 94595, "url": "https://patches.dpdk.org/api/patches/94595/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1624261125-22274-1-git-send-email-humin29@huawei.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1624261125-22274-1-git-send-email-humin29@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1624261125-22274-1-git-send-email-humin29@huawei.com", "date": "2021-06-21T07:38:45", "name": "net/hns3: fix traffic management", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "dddaafeb3dba1989b7dea09756394d7d8b72f9a8", "submitter": { "id": 1944, "url": "https://patches.dpdk.org/api/people/1944/?format=api", "name": "humin (Q)", "email": "humin29@huawei.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1624261125-22274-1-git-send-email-humin29@huawei.com/mbox/", "series": [ { "id": 17418, "url": "https://patches.dpdk.org/api/series/17418/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17418", "date": "2021-06-21T07:38:45", "name": "net/hns3: fix traffic management", "version": 1, "mbox": "https://patches.dpdk.org/series/17418/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94595/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/94595/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DB37EA0547;\n\tMon, 21 Jun 2021 09:39:17 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 68BB140040;\n\tMon, 21 Jun 2021 09:39:17 +0200 (CEST)", "from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255])\n by mails.dpdk.org (Postfix) with ESMTP id A9E0D4003F\n for <dev@dpdk.org>; Mon, 21 Jun 2021 09:39:15 +0200 (CEST)", "from dggeme756-chm.china.huawei.com (unknown [172.30.72.57])\n by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4G7h9T4S1lz1BQ6q\n for <dev@dpdk.org>; Mon, 21 Jun 2021 15:34:05 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n 15.1.2176.2; Mon, 21 Jun 2021 15:39:13 +0800" ], "From": "\"Min Hu (Connor)\" <humin29@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>", "Date": "Mon, 21 Jun 2021 15:38:45 +0800", "Message-ID": "<1624261125-22274-1-git-send-email-humin29@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-ClientProxiedBy": "dggems703-chm.china.huawei.com (10.3.19.180) To\n dggeme756-chm.china.huawei.com (10.3.19.102)", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH] net/hns3: fix traffic management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Huisong Li <lihuisong@huawei.com>\n\nIn a multi-TC scenario, if the length of packets destined for different\nTCs is different, for example, 64B and 1500B packets destined for TC0 and\nTC1 respectively. There is a problem that the bandwidth of the TC to which\nlarge packets are sent is preempted by the TC to which small packets are\nsent on the Kunpeng 920 network engine. As a result, the TC bandwidth\naccuracy is inaccurate.\n\nTo solve this problem, this patch made the following adjustments:\n1/ During initialization, firmware reports the capability bit indicating\nwhether the TM function is supported.\n2/ The command word for configuring TC and port rate limiting is added,\ninstead of reusing the existing command word. And firmware configured\nto the correct module.\n3/ When the PF driver is loaded, firmware completes the default\ninitialization of the TC and port.\n\nFixes: c09c7847d892 (\"net/hns3: support traffic management\")\n\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.c | 5 ++-\n drivers/net/hns3/hns3_cmd.h | 4 +++\n drivers/net/hns3/hns3_dcb.c | 4 +--\n drivers/net/hns3/hns3_dcb.h | 2 --\n drivers/net/hns3/hns3_ethdev.h | 4 +++\n drivers/net/hns3/hns3_tm.c | 69 +++++++++++++++++++++++++++++-------------\n drivers/net/hns3/hns3_tm.h | 12 ++++++++\n 7 files changed, 74 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c\nindex 44a4e28..cdccbf5 100644\n--- a/drivers/net/hns3/hns3_cmd.c\n+++ b/drivers/net/hns3/hns3_cmd.c\n@@ -427,7 +427,8 @@ hns3_get_caps_name(uint32_t caps_id)\n \t\t{ HNS3_CAPS_STASH_B, \"stash\" },\n \t\t{ HNS3_CAPS_UDP_TUNNEL_CSUM_B, \"udp_tunnel_csum\" },\n \t\t{ HNS3_CAPS_RAS_IMP_B, \"ras_imp\" },\n-\t\t{ HNS3_CAPS_RXD_ADV_LAYOUT_B, \"rxd_adv_layout\" }\n+\t\t{ HNS3_CAPS_RXD_ADV_LAYOUT_B, \"rxd_adv_layout\" },\n+\t\t{ HNS3_CAPS_TM_B, \"tm_capability\" }\n \t};\n \tuint32_t i;\n \n@@ -503,6 +504,8 @@ hns3_parse_capability(struct hns3_hw *hw,\n \t\t\t\tHNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1);\n \tif (hns3_get_bit(caps, HNS3_CAPS_RAS_IMP_B))\n \t\thns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1);\n+\tif (hns3_get_bit(caps, HNS3_CAPS_TM_B))\n+\t\thns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1);\n }\n \n static uint32_t\ndiff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex eafa365..0c9b8fc 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -162,6 +162,9 @@ enum hns3_opcode_type {\n \tHNS3_OPC_TM_INTERNAL_CNT = 0x0851,\n \tHNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,\n \n+\tHNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870,\n+\tHNS3_OPC_TM_TC_LIMIT_RATE = 0x0871,\n+\n \t/* Mailbox cmd */\n \tHNS3_OPC_MBX_VF_TO_PF = 0x2001,\n \n@@ -319,6 +322,7 @@ enum HNS3_CAPS_BITS {\n \tHNS3_CAPS_UDP_TUNNEL_CSUM_B,\n \tHNS3_CAPS_RAS_IMP_B,\n \tHNS3_CAPS_RXD_ADV_LAYOUT_B = 15,\n+\tHNS3_CAPS_TM_B = 17,\n };\n \n enum HNS3_API_CAP_BITS {\ndiff --git a/drivers/net/hns3/hns3_dcb.c b/drivers/net/hns3/hns3_dcb.c\nindex 90c0d04..f15c899 100644\n--- a/drivers/net/hns3/hns3_dcb.c\n+++ b/drivers/net/hns3/hns3_dcb.c\n@@ -415,7 +415,7 @@ hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,\n \treturn hns3_cmd_send(hw, &desc, 1);\n }\n \n-int\n+static int\n hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate)\n {\n \tstruct hns3_shaper_parameter shaper_parameter;\n@@ -551,7 +551,7 @@ hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,\n \treturn hns3_cmd_send(hw, &desc, 1);\n }\n \n-int\n+static int\n hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate)\n {\n \tstruct hns3_shaper_parameter shaper_parameter;\ndiff --git a/drivers/net/hns3/hns3_dcb.h b/drivers/net/hns3/hns3_dcb.h\nindex f378bd4..e06ec17 100644\n--- a/drivers/net/hns3/hns3_dcb.h\n+++ b/drivers/net/hns3/hns3_dcb.h\n@@ -209,8 +209,6 @@ int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,\n \n int hns3_update_queue_map_configure(struct hns3_adapter *hns);\n int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed);\n-int hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate);\n-int hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate);\n uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no);\n \n #endif /* _HNS3_DCB_H_ */\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex 575bacd..0b11a8d 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -868,6 +868,7 @@ enum {\n \tHNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,\n \tHNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,\n \tHNS3_DEV_SUPPORT_RAS_IMP_B,\n+\tHNS3_DEV_SUPPORT_TM_B,\n };\n \n #define hns3_dev_dcb_supported(hw) \\\n@@ -904,6 +905,9 @@ enum {\n #define hns3_dev_tx_push_supported(hw) \\\n \t\thns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)\n \n+#define hns3_dev_tm_supported(hw) \\\n+\thns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TM_B)\n+\n #define HNS3_DEV_PRIVATE_TO_HW(adapter) \\\n \t(&((struct hns3_adapter *)adapter)->hw)\n #define HNS3_DEV_PRIVATE_TO_PF(adapter) \\\ndiff --git a/drivers/net/hns3/hns3_tm.c b/drivers/net/hns3/hns3_tm.c\nindex aae4970..7fd9818 100644\n--- a/drivers/net/hns3/hns3_tm.c\n+++ b/drivers/net/hns3/hns3_tm.c\n@@ -28,8 +28,12 @@ void\n hns3_tm_conf_init(struct rte_eth_dev *dev)\n {\n \tstruct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t max_tx_queues = hns3_tm_max_tx_queues_get(dev);\n \n+\tif (!hns3_dev_tm_supported(hw))\n+\t\treturn;\n+\n \tpf->tm_conf.nb_leaf_nodes_max = max_tx_queues;\n \tpf->tm_conf.nb_nodes_max = 1 + HNS3_MAX_TC_NUM + max_tx_queues;\n \tpf->tm_conf.nb_shaper_profile_max = 1 + HNS3_MAX_TC_NUM;\n@@ -50,9 +54,13 @@ void\n hns3_tm_conf_uninit(struct rte_eth_dev *dev)\n {\n \tstruct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct hns3_tm_shaper_profile *shaper_profile;\n \tstruct hns3_tm_node *tm_node;\n \n+\tif (!hns3_dev_tm_supported(hw))\n+\t\treturn;\n+\n \tif (pf->tm_conf.nb_queue_node > 0) {\n \t\twhile ((tm_node = TAILQ_FIRST(&pf->tm_conf.queue_list))) {\n \t\t\tTAILQ_REMOVE(&pf->tm_conf.queue_list, tm_node, node);\n@@ -912,40 +920,39 @@ static int\n hns3_tm_config_port_rate(struct hns3_hw *hw,\n \t\t\t struct hns3_tm_shaper_profile *shaper_profile)\n {\n+\tstruct hns3_port_limit_rate_cmd *cfg;\n+\tstruct hns3_cmd_desc desc;\n \tuint32_t firmware_rate;\n \tuint64_t rate;\n+\tint ret;\n \n \tif (shaper_profile) {\n \t\trate = shaper_profile->profile.peak.rate;\n \t\tfirmware_rate = hns3_tm_rate_convert_tm2firmware(rate);\n \t} else {\n-\t\tfirmware_rate = hw->dcb_info.pg_info[0].bw_limit;\n+\t\tfirmware_rate = hw->max_tm_rate;\n \t}\n \n-\t/*\n-\t * The TM shaper topology after device inited:\n-\t * pri0 shaper --->|\n-\t * pri1 shaper --->|\n-\t * ... |----> pg0 shaper ----> port shaper\n-\t * ... |\n-\t * priX shaper --->|\n-\t *\n-\t * Because port shaper rate maybe changed by firmware, to avoid\n-\t * concurrent configure, driver use pg0 shaper to achieve the rate limit\n-\t * of port.\n-\t *\n-\t * The finally port rate = MIN(pg0 shaper rate, port shaper rate)\n-\t */\n-\treturn hns3_pg_shaper_rate_cfg(hw, 0, firmware_rate);\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PORT_LIMIT_RATE, false);\n+\tcfg = (struct hns3_port_limit_rate_cmd *)desc.data;\n+\tcfg->speed = rte_cpu_to_le_32(firmware_rate);\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret)\n+\t\thns3_err(hw, \"failed to config port rate, ret = %d\", ret);\n+\n+\treturn ret;\n }\n \n static int\n-hns3_tm_config_tc_rate(struct hns3_hw *hw,\n-\t\t uint8_t tc_no,\n+hns3_tm_config_tc_rate(struct hns3_hw *hw, uint8_t tc_no,\n \t\t struct hns3_tm_shaper_profile *shaper_profile)\n {\n+\tstruct hns3_tc_limit_rate_cmd *cfg;\n+\tstruct hns3_cmd_desc desc;\n \tuint32_t firmware_rate;\n \tuint64_t rate;\n+\tint ret;\n \n \tif (shaper_profile) {\n \t\trate = shaper_profile->profile.peak.rate;\n@@ -954,7 +961,17 @@ hns3_tm_config_tc_rate(struct hns3_hw *hw,\n \t\tfirmware_rate = hw->dcb_info.tc_info[tc_no].bw_limit;\n \t}\n \n-\treturn hns3_pri_shaper_rate_cfg(hw, tc_no, firmware_rate);\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_TC_LIMIT_RATE, false);\n+\tcfg = (struct hns3_tc_limit_rate_cmd *)desc.data;\n+\tcfg->speed = rte_cpu_to_le_32(firmware_rate);\n+\tcfg->tc_id = tc_no;\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret)\n+\t\thns3_err(hw, \"failed to config tc (%u) rate, ret = %d\",\n+\t\t\t tc_no, ret);\n+\n+\treturn ret;\n }\n \n static bool\n@@ -1227,12 +1244,16 @@ static const struct rte_tm_ops hns3_tm_ops = {\n };\n \n int\n-hns3_tm_ops_get(struct rte_eth_dev *dev __rte_unused,\n-\t\tvoid *arg)\n+hns3_tm_ops_get(struct rte_eth_dev *dev, void *arg)\n {\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n \tif (arg == NULL)\n \t\treturn -EINVAL;\n \n+\tif (!hns3_dev_tm_supported(hw))\n+\t\treturn -EOPNOTSUPP;\n+\n \t*(const void **)arg = &hns3_tm_ops;\n \n \treturn 0;\n@@ -1243,6 +1264,9 @@ hns3_tm_dev_start_proc(struct hns3_hw *hw)\n {\n \tstruct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);\n \n+\tif (!hns3_dev_tm_supported(hw))\n+\t\treturn;\n+\n \tif (pf->tm_conf.root && !pf->tm_conf.committed)\n \t\thns3_warn(hw,\n \t\t \"please call hierarchy_commit() before starting the port.\");\n@@ -1289,6 +1313,9 @@ hns3_tm_conf_update(struct hns3_hw *hw)\n \tstruct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);\n \tstruct rte_tm_error error;\n \n+\tif (!hns3_dev_tm_supported(hw))\n+\t\treturn 0;\n+\n \tif (pf->tm_conf.root == NULL || !pf->tm_conf.committed)\n \t\treturn 0;\n \ndiff --git a/drivers/net/hns3/hns3_tm.h b/drivers/net/hns3/hns3_tm.h\nindex 1f1f8c9..83e9cc8 100644\n--- a/drivers/net/hns3/hns3_tm.h\n+++ b/drivers/net/hns3/hns3_tm.h\n@@ -9,6 +9,18 @@\n #include <rte_tailq.h>\n #include <rte_tm_driver.h>\n \n+struct hns3_port_limit_rate_cmd {\n+\tuint32_t speed; /* Unit Mbps */\n+\tuint32_t rsvd[5];\n+};\n+\n+struct hns3_tc_limit_rate_cmd {\n+\tuint32_t speed; /* Unit Mbps */\n+\tuint8_t tc_id;\n+\tuint8_t rsvd[3];\n+\tuint32_t rsvd1[4];\n+};\n+\n enum hns3_tm_node_type {\n \tHNS3_TM_NODE_TYPE_PORT,\n \tHNS3_TM_NODE_TYPE_TC,\n", "prefixes": [] }