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GET /api/patches/94569/?format=api
{ "id": 94569, "url": "https://patches.dpdk.org/api/patches/94569/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-13-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210620202906.10974-13-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210620202906.10974-13-pbhagavatula@marvell.com", "date": "2021-06-20T20:29:06", "name": "[v3,13/13] event/cnxk: add Tx event vector fastpath", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a2f671502d67edd6f12578d630f2411e92b0c422", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-13-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17410, "url": "https://patches.dpdk.org/api/series/17410/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17410", "date": "2021-06-20T20:28:54", "name": "[v3,01/13] net/cnxk: add multi seg Rx vector routine", "version": 3, "mbox": "https://patches.dpdk.org/series/17410/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94569/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94569/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8157BA0547;\n\tSun, 20 Jun 2021 22:30:52 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B0B0F4115D;\n\tSun, 20 Jun 2021 22:30:01 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 19EC941195\n for <dev@dpdk.org>; Sun, 20 Jun 2021 22:29:58 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15KKQOMc010167 for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:58 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 399dxrmgt9-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:58 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 20 Jun 2021 13:29:56 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 20 Jun 2021 13:29:56 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id C15EC3F7066;\n Sun, 20 Jun 2021 13:29:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=zzWUYGqrLLMJvOlEEZIl6Dp+9dtMU4QnSHl64tWRfn4=;\n b=ARttLT+01XsJ/PjxCBeBliiYMlMe+Y9w2UYM+MHA41q4Kr/Wvd8aR7i8vvVqo4fYrci3\n RP28GizOllpzA25wq+O3jVYfAgZGlcc6wC4KXzEtV0cY28UtfH5thRZNzlIHmPkFcHTq\n d7Ts2whKtUxFVx2WzFJrJqN9O7OUrRabfCGatsnhdCBMO1Z7SOOPDpyDxyG+vltW1kTM\n /G1+8Kn3fPuk9vFXD8mvo8W+oolrisvvNepaBLBpnvRqScfrb7f1Alpl442fod1J6+f/\n 5aPMP+LS6+tJzdp76D8Jzgr4sVq6xUxYsiu1lY55LMT6by+3Og5nZ+SKe4/l8KT/Cw41 Sg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 21 Jun 2021 01:59:06 +0530", "Message-ID": "<20210620202906.10974-13-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210620202906.10974-1-pbhagavatula@marvell.com>", "References": "<20210619110154.10301-1-pbhagavatula@marvell.com>\n <20210620202906.10974-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "g3Tta6mCW2Ne7Lfc0ZiA-vGwKoV9C7OC", "X-Proofpoint-GUID": "g3Tta6mCW2Ne7Lfc0ZiA-vGwKoV9C7OC", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-20_14:2021-06-20,\n 2021-06-20 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 13/13] event/cnxk: add Tx event vector fastpath", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd Tx event vector fastpath, integrate event vector Tx routine\ninto Tx burst.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 1 +\n doc/guides/rel_notes/release_21_08.rst | 2 +-\n drivers/common/cnxk/roc_sso.h | 23 ++++++\n drivers/event/cnxk/cn10k_eventdev.c | 3 +-\n drivers/event/cnxk/cn10k_worker.h | 104 +++++++++++++++++++++++--\n drivers/event/cnxk/cn9k_worker.h | 4 +-\n drivers/event/cnxk/cnxk_worker.h | 22 ------\n drivers/net/cnxk/cn10k_tx.c | 2 +-\n drivers/net/cnxk/cn10k_tx.h | 52 +++++++++----\n drivers/net/cnxk/cn10k_tx_mseg.c | 3 +-\n drivers/net/cnxk/cn10k_tx_vec.c | 2 +-\n drivers/net/cnxk/cn10k_tx_vec_mseg.c | 2 +-\n 12 files changed, 167 insertions(+), 53 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 0297cd3d5f..53560d3830 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -47,6 +47,7 @@ Features of the OCTEON cnxk SSO PMD are:\n - Full Rx/Tx offload support defined through ethdev queue configuration.\n - HW managed event vectorization on CN10K for packets enqueued from ethdev to\n eventdev configurable per each Rx queue in Rx adapter.\n+- Event vector transmission via Tx adapter.\n \n Prerequisites and Compilation procedure\n ---------------------------------------\ndiff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst\nindex 11ccc9bcb5..9e49cb27d7 100644\n--- a/doc/guides/rel_notes/release_21_08.rst\n+++ b/doc/guides/rel_notes/release_21_08.rst\n@@ -64,7 +64,7 @@ New Features\n \n * Added Rx/Tx adapter support for event/cnxk when the ethernet device requested\n is net/cnxk.\n- * Add support for event vectorization for Rx adapter.\n+ * Add support for event vectorization for Rx/Tx adapter.\n \n \n Removed Items\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex a6030e7d8a..316c6ccd59 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -44,6 +44,29 @@ struct roc_sso {\n \tuint8_t reserved[ROC_SSO_MEM_SZ] __plt_cache_aligned;\n } __plt_cache_aligned;\n \n+static __rte_always_inline void\n+roc_sso_hws_head_wait(uintptr_t tag_op)\n+{\n+#ifdef RTE_ARCH_ARM64\n+\tuint64_t tag;\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"\t\tldr %[tag], [%[tag_op]]\t\\n\"\n+\t\t \"\t\ttbnz %[tag], 35, done%=\t\t\\n\"\n+\t\t \"\t\tsevl\t\t\t\t\\n\"\n+\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t \"\t\tldr %[tag], [%[tag_op]]\t\\n\"\n+\t\t \"\t\ttbz %[tag], 35, rty%=\t\t\\n\"\n+\t\t \"done%=:\t\t\t\t\t\\n\"\n+\t\t : [tag] \"=&r\"(tag)\n+\t\t : [tag_op] \"r\"(tag_op));\n+#else\n+\t/* Wait for the SWTAG/SWTAG_FULL operation */\n+\twhile (!(plt_read64(tag_op) & BIT_ULL(35)))\n+\t\t;\n+#endif\n+}\n+\n /* SSO device initialization */\n int __roc_api roc_sso_dev_init(struct roc_sso *roc_sso);\n int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso);\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex e85fa4785d..6f37c5bd23 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -782,7 +782,8 @@ cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,\n \tif (ret)\n \t\t*caps = 0;\n \telse\n-\t\t*caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;\n+\t\t*caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |\n+\t\t\tRTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;\n \n \treturn 0;\n }\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 7a48a6b17d..9cc0992063 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -308,29 +308,120 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n NIX_RX_FASTPATH_MODES\n #undef R\n \n-static __rte_always_inline const struct cn10k_eth_txq *\n+static __rte_always_inline struct cn10k_eth_txq *\n cn10k_sso_hws_xtract_meta(struct rte_mbuf *m,\n \t\t\t const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])\n {\n-\treturn (const struct cn10k_eth_txq *)\n+\treturn (struct cn10k_eth_txq *)\n \t\ttxq_data[m->port][rte_event_eth_tx_adapter_txq_get(m)];\n }\n \n+static __rte_always_inline void\n+cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,\n+\t\t\tuint64_t *cmd, uint16_t lmt_id, uintptr_t lmt_addr,\n+\t\t\tuint8_t sched_type, uintptr_t base,\n+\t\t\tconst uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n+\t\t\tconst uint32_t flags)\n+{\n+\tuint16_t port[4], queue[4];\n+\tstruct cn10k_eth_txq *txq;\n+\tuint16_t i, j;\n+\tuintptr_t pa;\n+\n+\tfor (i = 0; i < nb_mbufs; i += 4) {\n+\t\tport[0] = mbufs[i]->port;\n+\t\tport[1] = mbufs[i + 1]->port;\n+\t\tport[2] = mbufs[i + 2]->port;\n+\t\tport[3] = mbufs[i + 3]->port;\n+\n+\t\tqueue[0] = rte_event_eth_tx_adapter_txq_get(mbufs[i]);\n+\t\tqueue[1] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 1]);\n+\t\tqueue[2] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 2]);\n+\t\tqueue[3] = rte_event_eth_tx_adapter_txq_get(mbufs[i + 3]);\n+\n+\t\tif (((port[0] ^ port[1]) & (port[2] ^ port[3])) ||\n+\t\t ((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {\n+\n+\t\t\tfor (j = 0; j < 4; j++) {\n+\t\t\t\tstruct rte_mbuf *m = mbufs[i + j];\n+\n+\t\t\t\ttxq = (struct cn10k_eth_txq *)\n+\t\t\t\t\ttxq_data[port[j]][queue[j]];\n+\t\t\t\tcn10k_nix_tx_skeleton(txq, cmd, flags);\n+\t\t\t\t/* Perform header writes before barrier\n+\t\t\t\t * for TSO\n+\t\t\t\t */\n+\t\t\t\tif (flags & NIX_TX_OFFLOAD_TSO_F)\n+\t\t\t\t\tcn10k_nix_xmit_prepare_tso(m, flags);\n+\n+\t\t\t\tcn10k_nix_xmit_prepare(m, cmd, lmt_addr, flags,\n+\t\t\t\t\t\t txq->lso_tun_fmt);\n+\t\t\t\tif (flags & NIX_TX_MULTI_SEG_F) {\n+\t\t\t\t\tconst uint16_t segdw =\n+\t\t\t\t\t\tcn10k_nix_prepare_mseg(\n+\t\t\t\t\t\t\tm, (uint64_t *)lmt_addr,\n+\t\t\t\t\t\t\tflags);\n+\t\t\t\t\tpa = txq->io_addr | ((segdw - 1) << 4);\n+\t\t\t\t} else {\n+\t\t\t\t\tpa = txq->io_addr |\n+\t\t\t\t\t (cn10k_nix_tx_ext_subs(flags) + 1)\n+\t\t\t\t\t\t << 4;\n+\t\t\t\t}\n+\t\t\t\tif (!sched_type)\n+\t\t\t\t\troc_sso_hws_head_wait(base +\n+\t\t\t\t\t\t\t SSOW_LF_GWS_TAG);\n+\n+\t\t\t\troc_lmt_submit_steorl(lmt_id, pa);\n+\t\t\t}\n+\t\t} else {\n+\t\t\ttxq = (struct cn10k_eth_txq *)\n+\t\t\t\ttxq_data[port[0]][queue[0]];\n+\t\t\tcn10k_nix_xmit_pkts_vector(txq, &mbufs[i], 4, cmd, base\n+\t\t\t\t\t+ SSOW_LF_GWS_TAG,\n+\t\t\t\t\t\t flags | NIX_TX_VWQE_F);\n+\t\t}\n+\t}\n+}\n+\n static __rte_always_inline uint16_t\n cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\t uint64_t *cmd,\n \t\t const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n \t\t const uint32_t flags)\n {\n-\tconst struct cn10k_eth_txq *txq;\n-\tstruct rte_mbuf *m = ev->mbuf;\n-\tuint16_t ref_cnt = m->refcnt;\n+\tstruct cn10k_eth_txq *txq;\n+\tstruct rte_mbuf *m;\n \tuintptr_t lmt_addr;\n+\tuint16_t ref_cnt;\n \tuint16_t lmt_id;\n \tuintptr_t pa;\n \n \tlmt_addr = ws->lmt_base;\n \tROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);\n+\n+\tif (ev->event_type & RTE_EVENT_TYPE_VECTOR) {\n+\t\tstruct rte_mbuf **mbufs = ev->vec->mbufs;\n+\t\tuint64_t meta = *(uint64_t *)ev->vec;\n+\n+\t\tif (meta & BIT(31)) {\n+\t\t\ttxq = (struct cn10k_eth_txq *)\n+\t\t\t\ttxq_data[meta >> 32][meta >> 48];\n+\n+\t\t\tcn10k_nix_xmit_pkts_vector(\n+\t\t\t\ttxq, mbufs, meta & 0xFFFF, cmd,\n+\t\t\t\tws->tx_base + SSOW_LF_GWS_TAG,\n+\t\t\t\tflags | NIX_TX_VWQE_F);\n+\t\t} else {\n+\t\t\tcn10k_sso_vwqe_split_tx(\n+\t\t\t\tmbufs, meta & 0xFFFF, cmd, lmt_id, lmt_addr,\n+\t\t\t\tev->sched_type, ws->tx_base, txq_data, flags);\n+\t\t}\n+\t\trte_mempool_put(rte_mempool_from_obj(ev->vec), ev->vec);\n+\t\treturn (meta & 0xFFFF);\n+\t}\n+\n+\tm = ev->mbuf;\n+\tref_cnt = m->refcnt;\n \ttxq = cn10k_sso_hws_xtract_meta(m, txq_data);\n \tcn10k_nix_tx_skeleton(txq, cmd, flags);\n \t/* Perform header writes before barrier for TSO */\n@@ -346,7 +437,7 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \t\tpa = txq->io_addr | (cn10k_nix_tx_ext_subs(flags) + 1) << 4;\n \t}\n \tif (!ev->sched_type)\n-\t\tcnxk_sso_hws_head_wait(ws->tx_base + SSOW_LF_GWS_TAG);\n+\t\troc_sso_hws_head_wait(ws->tx_base + SSOW_LF_GWS_TAG);\n \n \troc_lmt_submit_steorl(lmt_id, pa);\n \n@@ -357,7 +448,6 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,\n \n \tcnxk_sso_hws_swtag_flush(ws->tx_base + SSOW_LF_GWS_TAG,\n \t\t\t\t ws->tx_base + SSOW_LF_GWS_OP_SWTAG_FLUSH);\n-\n \treturn 1;\n }\n \ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex 5aa053c586..ef1e83741a 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -458,7 +458,7 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n \t\tconst uint16_t segdw = cn9k_nix_prepare_mseg(m, cmd, flags);\n \t\tif (!CNXK_TT_FROM_EVENT(ev->event)) {\n \t\t\tcn9k_nix_xmit_mseg_prep_lmt(cmd, txq->lmt_addr, segdw);\n-\t\t\tcnxk_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n+\t\t\troc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n \t\t\tif (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)\n \t\t\t\tcn9k_nix_xmit_mseg_one(cmd, txq->lmt_addr,\n \t\t\t\t\t\t txq->io_addr, segdw);\n@@ -469,7 +469,7 @@ cn9k_sso_hws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n \t} else {\n \t\tif (!CNXK_TT_FROM_EVENT(ev->event)) {\n \t\t\tcn9k_nix_xmit_prep_lmt(cmd, txq->lmt_addr, flags);\n-\t\t\tcnxk_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n+\t\t\troc_sso_hws_head_wait(base + SSOW_LF_GWS_TAG);\n \t\t\tif (cn9k_nix_xmit_submit_lmt(txq->io_addr) == 0)\n \t\t\t\tcn9k_nix_xmit_one(cmd, txq->lmt_addr,\n \t\t\t\t\t\t txq->io_addr, flags);\ndiff --git a/drivers/event/cnxk/cnxk_worker.h b/drivers/event/cnxk/cnxk_worker.h\nindex 4eb46ae162..945132b748 100644\n--- a/drivers/event/cnxk/cnxk_worker.h\n+++ b/drivers/event/cnxk/cnxk_worker.h\n@@ -75,27 +75,5 @@ cnxk_sso_hws_swtag_wait(uintptr_t tag_op)\n #endif\n }\n \n-static __rte_always_inline void\n-cnxk_sso_hws_head_wait(uintptr_t tag_op)\n-{\n-#ifdef RTE_ARCH_ARM64\n-\tuint64_t swtp;\n-\n-\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n-\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n-\t\t \"\t\ttbz %[swtb], 35, done%=\t\t\\n\"\n-\t\t \"\t\tsevl\t\t\t\t\\n\"\n-\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n-\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n-\t\t \"\t\ttbnz %[swtb], 35, rty%=\t\t\\n\"\n-\t\t \"done%=:\t\t\t\t\t\\n\"\n-\t\t : [swtb] \"=&r\"(swtp)\n-\t\t : [swtp_loc] \"r\"(tag_op));\n-#else\n-\t/* Wait for the SWTAG/SWTAG_FULL operation */\n-\twhile (plt_read64(tag_op) & BIT_ULL(35))\n-\t\t;\n-#endif\n-}\n \n #endif\ndiff --git a/drivers/net/cnxk/cn10k_tx.c b/drivers/net/cnxk/cn10k_tx.c\nindex 1f30bab59a..0e1276c60b 100644\n--- a/drivers/net/cnxk/cn10k_tx.c\n+++ b/drivers/net/cnxk/cn10k_tx.c\n@@ -16,7 +16,7 @@\n \t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn10k_nix_xmit_pkts(tx_queue, tx_pkts, pkts, cmd, \\\n-\t\t\t\t\t flags);\t\t\t \\\n+\t\t\t\t\t 0, flags);\t\t\t \\\n \t}\n \n NIX_TX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex 532b53b319..d2a24120ef 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -18,6 +18,7 @@\n * Defining it from backwards to denote its been\n * not used as offload flags to pick function\n */\n+#define NIX_TX_VWQE_F\t BIT(14)\n #define NIX_TX_MULTI_SEG_F BIT(15)\n \n #define NIX_TX_NEED_SEND_HDR_W1 \\\n@@ -519,7 +520,7 @@ cn10k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n \n static __rte_always_inline uint16_t\n cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n-\t\t uint64_t *cmd, const uint16_t flags)\n+\t\t uint64_t *cmd, uintptr_t base, const uint16_t flags)\n {\n \tstruct cn10k_eth_txq *txq = tx_queue;\n \tconst rte_iova_t io_addr = txq->io_addr;\n@@ -528,14 +529,15 @@ cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \tuint64_t lso_tun_fmt;\n \tuint64_t data;\n \n-\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\tif (!(flags & NIX_TX_VWQE_F)) {\n+\t\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\t\t/* Reduce the cached count */\n+\t\ttxq->fc_cache_pkts -= pkts;\n+\t}\n \n \t/* Get cmd skeleton */\n \tcn10k_nix_tx_skeleton(txq, cmd, flags);\n \n-\t/* Reduce the cached count */\n-\ttxq->fc_cache_pkts -= pkts;\n-\n \tif (flags & NIX_TX_OFFLOAD_TSO_F)\n \t\tlso_tun_fmt = txq->lso_tun_fmt;\n \n@@ -558,6 +560,9 @@ cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \t\tlmt_addr += (1ULL << ROC_LMT_LINE_SIZE_LOG2);\n \t}\n \n+\tif (flags & NIX_TX_VWQE_F)\n+\t\troc_sso_hws_head_wait(base);\n+\n \t/* Trigger LMTST */\n \tif (burst > 16) {\n \t\tdata = cn10k_nix_tx_steor_data(flags);\n@@ -604,7 +609,8 @@ cn10k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \n static __rte_always_inline uint16_t\n cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n+\t\t\t uint16_t pkts, uint64_t *cmd, uintptr_t base,\n+\t\t\t const uint16_t flags)\n {\n \tstruct cn10k_eth_txq *txq = tx_queue;\n \tuintptr_t pa0, pa1, lmt_addr = txq->lmt_base;\n@@ -652,6 +658,9 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tshft += 3;\n \t}\n \n+\tif (flags & NIX_TX_VWQE_F)\n+\t\troc_sso_hws_head_wait(base);\n+\n \tdata0 = (uint64_t)data128;\n \tdata1 = (uint64_t)(data128 >> 64);\n \t/* Make data0 similar to data1 */\n@@ -984,7 +993,8 @@ cn10k_nix_prep_lmt_mseg_vector(struct rte_mbuf **mbufs, uint64x2_t *cmd0,\n \n static __rte_always_inline uint16_t\n cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n+\t\t\t uint16_t pkts, uint64_t *cmd, uintptr_t base,\n+\t\t\t const uint16_t flags)\n {\n \tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n \tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n@@ -1013,13 +1023,17 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tuint64_t data[2];\n \t} wd;\n \n-\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n-\n-\tscalar = pkts & (NIX_DESCS_PER_LOOP - 1);\n-\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\tif (!(flags & NIX_TX_VWQE_F)) {\n+\t\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\t\tscalar = pkts & (NIX_DESCS_PER_LOOP - 1);\n+\t\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\t\t/* Reduce the cached count */\n+\t\ttxq->fc_cache_pkts -= pkts;\n+\t} else {\n+\t\tscalar = pkts & (NIX_DESCS_PER_LOOP - 1);\n+\t\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\t}\n \n-\t/* Reduce the cached count */\n-\ttxq->fc_cache_pkts -= pkts;\n \t/* Perform header writes before barrier for TSO */\n \tif (flags & NIX_TX_OFFLOAD_TSO_F) {\n \t\tfor (i = 0; i < pkts; i++)\n@@ -1972,6 +1986,9 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (flags & NIX_TX_MULTI_SEG_F)\n \t\twd.data[0] >>= 16;\n \n+\tif (flags & NIX_TX_VWQE_F)\n+\t\troc_sso_hws_head_wait(base);\n+\n \t/* Trigger LMTST */\n \tif (lnum > 16) {\n \t\tif (!(flags & NIX_TX_MULTI_SEG_F))\n@@ -2028,10 +2045,11 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tif (unlikely(scalar)) {\n \t\tif (flags & NIX_TX_MULTI_SEG_F)\n \t\t\tpkts += cn10k_nix_xmit_pkts_mseg(tx_queue, tx_pkts,\n-\t\t\t\t\t\t\t scalar, cmd, flags);\n+\t\t\t\t\t\t\t scalar, cmd, base,\n+\t\t\t\t\t\t\t flags);\n \t\telse\n \t\t\tpkts += cn10k_nix_xmit_pkts(tx_queue, tx_pkts, scalar,\n-\t\t\t\t\t\t cmd, flags);\n+\t\t\t\t\t\t cmd, base, flags);\n \t}\n \n \treturn pkts;\n@@ -2040,13 +2058,15 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n #else\n static __rte_always_inline uint16_t\n cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n+\t\t\t uint16_t pkts, uint64_t *cmd, uintptr_t base,\n+\t\t\t const uint16_t flags)\n {\n \tRTE_SET_USED(tx_queue);\n \tRTE_SET_USED(tx_pkts);\n \tRTE_SET_USED(pkts);\n \tRTE_SET_USED(cmd);\n \tRTE_SET_USED(flags);\n+\tRTE_SET_USED(base);\n \treturn 0;\n }\n #endif\ndiff --git a/drivers/net/cnxk/cn10k_tx_mseg.c b/drivers/net/cnxk/cn10k_tx_mseg.c\nindex 33f6754722..4ea4c8a4e5 100644\n--- a/drivers/net/cnxk/cn10k_tx_mseg.c\n+++ b/drivers/net/cnxk/cn10k_tx_mseg.c\n@@ -18,7 +18,8 @@\n \t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn10k_nix_xmit_pkts_mseg(tx_queue, tx_pkts, pkts, cmd, \\\n-\t\t\t\t\t\t(flags) | NIX_TX_MULTI_SEG_F); \\\n+\t\t\t\t\t\t0, (flags)\t\t \\\n+\t\t\t\t\t\t\t| NIX_TX_MULTI_SEG_F); \\\n \t}\n \n NIX_TX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_tx_vec.c b/drivers/net/cnxk/cn10k_tx_vec.c\nindex 34e3737501..a0350496ab 100644\n--- a/drivers/net/cnxk/cn10k_tx_vec.c\n+++ b/drivers/net/cnxk/cn10k_tx_vec.c\n@@ -18,7 +18,7 @@\n \t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t \\\n \t\t\treturn 0; \\\n \t\treturn cn10k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd,\\\n-\t\t\t\t\t\t (flags)); \\\n+\t\t\t\t\t\t 0, (flags)); \\\n \t}\n \n NIX_TX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_tx_vec_mseg.c b/drivers/net/cnxk/cn10k_tx_vec_mseg.c\nindex 1fad81dbad..7f98f79b97 100644\n--- a/drivers/net/cnxk/cn10k_tx_vec_mseg.c\n+++ b/drivers/net/cnxk/cn10k_tx_vec_mseg.c\n@@ -16,7 +16,7 @@\n \t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F)) \\\n \t\t\treturn 0; \\\n \t\treturn cn10k_nix_xmit_pkts_vector( \\\n-\t\t\ttx_queue, tx_pkts, pkts, cmd, \\\n+\t\t\ttx_queue, tx_pkts, pkts, cmd, 0, \\\n \t\t\t(flags) | NIX_TX_MULTI_SEG_F); \\\n \t}\n \n", "prefixes": [ "v3", "13/13" ] }