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GET /api/patches/94558/?format=api
{ "id": 94558, "url": "https://patches.dpdk.org/api/patches/94558/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-1-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210620202906.10974-1-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210620202906.10974-1-pbhagavatula@marvell.com", "date": "2021-06-20T20:28:54", "name": "[v3,01/13] net/cnxk: add multi seg Rx vector routine", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6c26cb5b74d21d0b6c3886fd2a5baefb3d4415f0", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210620202906.10974-1-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17410, "url": "https://patches.dpdk.org/api/series/17410/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17410", "date": "2021-06-20T20:28:54", "name": "[v3,01/13] net/cnxk: add multi seg Rx vector routine", "version": 3, "mbox": "https://patches.dpdk.org/series/17410/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94558/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94558/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DF1EEA0547;\n\tSun, 20 Jun 2021 22:29:20 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5F78B40141;\n\tSun, 20 Jun 2021 22:29:20 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 8AAD44003F\n for <dev@dpdk.org>; Sun, 20 Jun 2021 22:29:18 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15KKSRF7009821 for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:17 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 399g3qm1bf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 20 Jun 2021 13:29:16 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 20 Jun 2021 13:29:14 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 20 Jun 2021 13:29:14 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 119B33F7066;\n Sun, 20 Jun 2021 13:29:11 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=PPzHbhgWf+mr2qoWksCtEd3vImIDVZgNzZQmqMAhTA4=;\n b=ghwIkFWbDvxw9570AHsq1nmM9QikNLvxBNH3M2I/+RnDEHo68EHsA+DnY7+OkHySRGFl\n hGwFHSvtaWmXYvWb0WHX+Ceiu+3YX3N8AoJ12thApElO62q9H4Fe7/xeiBAHaE9G0dSd\n ux2WbgSQd5m6r4ao3BIm2EOPPEMJxL3N2+YbjCOJ6VMgGTTqAlhm/huGEREOkveekrQw\n lLJufYrSNkdfdBQpRLBxzkYLOKE+nR8pmBEW7DTSPYGK7ez3neJ18u4dqlhvQ1bSuv8c\n 4+7DI0DOPvLzN1/RFmtv4/atCrfJGHFC0qm1Gz1kNMqyHTZ3n/+6ZkMazcQrhb22LnmU DA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Mon, 21 Jun 2021 01:58:54 +0530", "Message-ID": "<20210620202906.10974-1-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210619110154.10301-1-pbhagavatula@marvell.com>", "References": "<20210619110154.10301-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "69E8Y58n2DtKvi5rl6U_w0fK5DC_UhBA", "X-Proofpoint-ORIG-GUID": "69E8Y58n2DtKvi5rl6U_w0fK5DC_UhBA", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-20_11:2021-06-20,\n 2021-06-20 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 01/13] net/cnxk: add multi seg Rx vector\n routine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd multi-segment Rx vector routine, form the primary mbufs using\nvector path switch to scalar path when extracting segments.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n Depends-on: http://patches.dpdk.org/project/dpdk/list/?series=17394\n\n v3 Changes:\n - Spell check.\n\n drivers/net/cnxk/cn10k_rx.c | 31 +++++++++++------\n drivers/net/cnxk/cn10k_rx.h | 51 +++++++++++++++++++++-------\n drivers/net/cnxk/cn10k_rx_vec_mseg.c | 17 ++++++++++\n drivers/net/cnxk/cn9k_rx.c | 31 +++++++++++------\n drivers/net/cnxk/cn9k_rx.h | 51 +++++++++++++++++++++-------\n drivers/net/cnxk/cn9k_rx_vec_mseg.c | 18 ++++++++++\n drivers/net/cnxk/meson.build | 2 ++\n 7 files changed, 157 insertions(+), 44 deletions(-)\n create mode 100644 drivers/net/cnxk/cn10k_rx_vec_mseg.c\n create mode 100644 drivers/net/cnxk/cn9k_rx_vec_mseg.c\n\n--\n2.17.1", "diff": "diff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c\nindex 5c956c06b4..3a9fd71309 100644\n--- a/drivers/net/cnxk/cn10k_rx.c\n+++ b/drivers/net/cnxk/cn10k_rx.c\n@@ -29,6 +29,8 @@ pick_rx_func(struct rte_eth_dev *eth_dev,\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];\n+\n+\trte_atomic_thread_fence(__ATOMIC_RELEASE);\n }\n\n void\n@@ -60,20 +62,29 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n #undef R\n \t};\n\n-\t/* For PTP enabled, scalar rx function should be chosen as most of the\n-\t * PTP apps are implemented to rx burst 1 pkt.\n-\t */\n-\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n-\telse\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name,\n\n-\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n\n \t/* Copy multi seg version with no offload for tear down sequence */\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n \t\tdev->rx_pkt_burst_no_offload =\n \t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0];\n-\trte_mb();\n+\n+\t/* For PTP enabled, scalar rx function should be chosen as most of the\n+\t * PTP apps are implemented to rx burst 1 pkt.\n+\t */\n+\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {\n+\t\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n+\t\t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n+\t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst);\n+\t}\n+\n+\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n+\t\treturn pick_rx_func(eth_dev, nix_eth_rx_vec_burst_mseg);\n+\treturn pick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n }\ndiff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex 1cc37cbaa0..5926ff7f46 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -119,8 +119,15 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n\n \tsg = *(const uint64_t *)(rx + 1);\n \tnb_segs = (sg >> 48) & 0x3;\n-\tmbuf->nb_segs = nb_segs;\n+\n+\tif (nb_segs == 1) {\n+\t\tmbuf->next = NULL;\n+\t\treturn;\n+\t}\n+\n+\tmbuf->pkt_len = rx->pkt_lenm1 + 1;\n \tmbuf->data_len = sg & 0xFFFF;\n+\tmbuf->nb_segs = nb_segs;\n \tsg = sg >> 16;\n\n \teol = ((const rte_iova_t *)(rx + 1) + ((rx->desc_sizem1 + 1) << 1));\n@@ -195,15 +202,14 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t\tol_flags = nix_update_match_id(rx->match_id, ol_flags, mbuf);\n\n \tmbuf->ol_flags = ol_flags;\n-\t*(uint64_t *)(&mbuf->rearm_data) = val;\n \tmbuf->pkt_len = len;\n+\tmbuf->data_len = len;\n+\t*(uint64_t *)(&mbuf->rearm_data) = val;\n\n-\tif (flag & NIX_RX_MULTI_SEG_F) {\n+\tif (flag & NIX_RX_MULTI_SEG_F)\n \t\tnix_cqe_xtract_mseg(rx, mbuf, val);\n-\t} else {\n-\t\tmbuf->data_len = len;\n+\telse\n \t\tmbuf->next = NULL;\n-\t}\n }\n\n static inline uint16_t\n@@ -481,16 +487,34 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n \t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n\n-\t\t/* Update that no more segments */\n-\t\tmbuf0->next = NULL;\n-\t\tmbuf1->next = NULL;\n-\t\tmbuf2->next = NULL;\n-\t\tmbuf3->next = NULL;\n-\n \t\t/* Store the mbufs to rx_pkts */\n \t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n \t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n\n+\t\tif (flags & NIX_RX_MULTI_SEG_F) {\n+\t\t\t/* Multi segment is enable build mseg list for\n+\t\t\t * individual mbufs in scalar mode.\n+\t\t\t */\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(0) + 8), mbuf0,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(1) + 8), mbuf1,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(2) + 8), mbuf2,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(3) + 8), mbuf3,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t} else {\n+\t\t\t/* Update that no more segments */\n+\t\t\tmbuf0->next = NULL;\n+\t\t\tmbuf1->next = NULL;\n+\t\t\tmbuf2->next = NULL;\n+\t\t\tmbuf3->next = NULL;\n+\t\t}\n+\n \t\t/* Prefetch mbufs */\n \t\troc_prefetch_store_keep(mbuf0);\n \t\troc_prefetch_store_keep(mbuf1);\n@@ -645,6 +669,9 @@ R(vlan_ts_mark_cksum_ptype_rss,\t1, 1, 1, 1, 1, 1,\t\t\t \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n \t\t\t\t\t\t\t\t\t \\\n \tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_mseg_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts);\n\n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn10k_rx_vec_mseg.c b/drivers/net/cnxk/cn10k_rx_vec_mseg.c\nnew file mode 100644\nindex 0000000000..04d1e46c82\n--- /dev/null\n+++ b/drivers/net/cnxk/cn10k_rx_vec_mseg.c\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn10k_ethdev.h\"\n+#include \"cn10k_rx.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_mseg_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n+\t{ \\\n+\t\treturn cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n+\t\t\t\t\t (flags) | NIX_RX_MULTI_SEG_F); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/net/cnxk/cn9k_rx.c b/drivers/net/cnxk/cn9k_rx.c\nindex 0acedd0a1f..d293d4eac3 100644\n--- a/drivers/net/cnxk/cn9k_rx.c\n+++ b/drivers/net/cnxk/cn9k_rx.c\n@@ -29,6 +29,8 @@ pick_rx_func(struct rte_eth_dev *eth_dev,\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]\n \t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];\n+\n+\trte_atomic_thread_fence(__ATOMIC_RELEASE);\n }\n\n void\n@@ -60,20 +62,29 @@ cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n #undef R\n \t};\n\n-\t/* For PTP enabled, scalar rx function should be chosen as most of the\n-\t * PTP apps are implemented to rx burst 1 pkt.\n-\t */\n-\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n-\telse\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_mseg_##name,\n\n-\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n\n \t/* Copy multi seg version with no offload for tear down sequence */\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n \t\tdev->rx_pkt_burst_no_offload =\n \t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0];\n-\trte_mb();\n+\n+\t/* For PTP enabled, scalar rx function should be chosen as most of the\n+\t * PTP apps are implemented to rx burst 1 pkt.\n+\t */\n+\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) {\n+\t\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n+\t\t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n+\t\treturn pick_rx_func(eth_dev, nix_eth_rx_burst);\n+\t}\n+\n+\tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n+\t\treturn pick_rx_func(eth_dev, nix_eth_rx_vec_burst_mseg);\n+\treturn pick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n }\ndiff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h\nindex 10ef5c6905..5ae9e8195c 100644\n--- a/drivers/net/cnxk/cn9k_rx.h\n+++ b/drivers/net/cnxk/cn9k_rx.h\n@@ -120,8 +120,15 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,\n\n \tsg = *(const uint64_t *)(rx + 1);\n \tnb_segs = (sg >> 48) & 0x3;\n-\tmbuf->nb_segs = nb_segs;\n+\n+\tif (nb_segs == 1) {\n+\t\tmbuf->next = NULL;\n+\t\treturn;\n+\t}\n+\n+\tmbuf->pkt_len = rx->pkt_lenm1 + 1;\n \tmbuf->data_len = sg & 0xFFFF;\n+\tmbuf->nb_segs = nb_segs;\n \tsg = sg >> 16;\n\n \teol = ((const rte_iova_t *)(rx + 1) +\n@@ -198,15 +205,14 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n \t\t\tnix_update_match_id(rx->cn9k.match_id, ol_flags, mbuf);\n\n \tmbuf->ol_flags = ol_flags;\n-\t*(uint64_t *)(&mbuf->rearm_data) = val;\n \tmbuf->pkt_len = len;\n+\tmbuf->data_len = len;\n+\t*(uint64_t *)(&mbuf->rearm_data) = val;\n\n-\tif (flag & NIX_RX_MULTI_SEG_F) {\n+\tif (flag & NIX_RX_MULTI_SEG_F)\n \t\tnix_cqe_xtract_mseg(rx, mbuf, val);\n-\t} else {\n-\t\tmbuf->data_len = len;\n+\telse\n \t\tmbuf->next = NULL;\n-\t}\n }\n\n static inline uint16_t\n@@ -484,16 +490,34 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n \t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n\n-\t\t/* Update that no more segments */\n-\t\tmbuf0->next = NULL;\n-\t\tmbuf1->next = NULL;\n-\t\tmbuf2->next = NULL;\n-\t\tmbuf3->next = NULL;\n-\n \t\t/* Store the mbufs to rx_pkts */\n \t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n \t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n\n+\t\tif (flags & NIX_RX_MULTI_SEG_F) {\n+\t\t\t/* Multi segment is enable build mseg list for\n+\t\t\t * individual mbufs in scalar mode.\n+\t\t\t */\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(0) + 8), mbuf0,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(1) + 8), mbuf1,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(2) + 8), mbuf2,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t\tnix_cqe_xtract_mseg((union nix_rx_parse_u *)\n+\t\t\t\t\t (cq0 + CQE_SZ(3) + 8), mbuf3,\n+\t\t\t\t\t mbuf_initializer);\n+\t\t} else {\n+\t\t\t/* Update that no more segments */\n+\t\t\tmbuf0->next = NULL;\n+\t\t\tmbuf1->next = NULL;\n+\t\t\tmbuf2->next = NULL;\n+\t\t\tmbuf3->next = NULL;\n+\t\t}\n+\n \t\t/* Prefetch mbufs */\n \t\troc_prefetch_store_keep(mbuf0);\n \t\troc_prefetch_store_keep(mbuf1);\n@@ -647,6 +671,9 @@ R(vlan_ts_mark_cksum_ptype_rss,\t1, 1, 1, 1, 1, 1,\t\t\t \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n \t\t\t\t\t\t\t\t\t \\\n \tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_vec_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_vec_mseg_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts);\n\n NIX_RX_FASTPATH_MODES\ndiff --git a/drivers/net/cnxk/cn9k_rx_vec_mseg.c b/drivers/net/cnxk/cn9k_rx_vec_mseg.c\nnew file mode 100644\nindex 0000000000..e46d8a4749\n--- /dev/null\n+++ b/drivers/net/cnxk/cn9k_rx_vec_mseg.c\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_ethdev.h\"\n+#include \"cn9k_rx.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_vec_mseg_##name( \\\n+\t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n+\t{ \\\n+\t\treturn cn9k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \\\n+\t\t\t\t\t\t (flags) | \\\n+\t\t\t\t\t\t\t NIX_RX_MULTI_SEG_F); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 2071d0dcb2..aa8c7253fb 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -23,6 +23,7 @@ sources += files('cn9k_ethdev.c',\n \t\t 'cn9k_rx.c',\n \t\t 'cn9k_rx_mseg.c',\n \t\t 'cn9k_rx_vec.c',\n+\t\t 'cn9k_rx_vec_mseg.c',\n \t\t 'cn9k_tx.c',\n \t\t 'cn9k_tx_mseg.c',\n \t\t 'cn9k_tx_vec.c')\n@@ -32,6 +33,7 @@ sources += files('cn10k_ethdev.c',\n \t\t 'cn10k_rx.c',\n \t\t 'cn10k_rx_mseg.c',\n \t\t 'cn10k_rx_vec.c',\n+\t\t 'cn10k_rx_vec_mseg.c',\n \t\t 'cn10k_tx.c',\n \t\t 'cn10k_tx_mseg.c',\n \t\t 'cn10k_tx_vec.c')\n", "prefixes": [ "v3", "01/13" ] }