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GET /api/patches/94551/?format=api
{ "id": 94551, "url": "https://patches.dpdk.org/api/patches/94551/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210619110154.10301-11-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210619110154.10301-11-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210619110154.10301-11-pbhagavatula@marvell.com", "date": "2021-06-19T11:01:51", "name": "[v2,11/13] event/cnxk: add Rx adapter vector support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5f394817eeae66643a407484f4780586708b097d", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210619110154.10301-11-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 17405, "url": "https://patches.dpdk.org/api/series/17405/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17405", "date": "2021-06-19T11:01:41", "name": "[v2,01/13] net/cnxk: add multi seg Rx vector routine", "version": 2, "mbox": "https://patches.dpdk.org/series/17405/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94551/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94551/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A5E9AA0A0C;\n\tSat, 19 Jun 2021 13:03:39 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB66E41149;\n\tSat, 19 Jun 2021 13:02:49 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0C64F41102\n for <dev@dpdk.org>; Sat, 19 Jun 2021 13:02:47 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 15JAu1tU007709 for <dev@dpdk.org>; Sat, 19 Jun 2021 04:02:47 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 398tu0v62h-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 19 Jun 2021 04:02:47 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sat, 19 Jun 2021 04:02:45 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sat, 19 Jun 2021 04:02:45 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id BB87B5B6965;\n Sat, 19 Jun 2021 04:02:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=6NYHv829x8bUGeOgtLhXkTV8VzYB8Z7D7wn3ntpTNF8=;\n b=WbfdpF3hLnBbRe003+s7nvjCP9JO8om0K/GxBbKFpqKlaS79xwIf+rHZGADga1DMtm3a\n hUe2+cOmgqGFcOTivsoZjbERt1TbspGMlv4CSpaZij5yfe0z6c0xb22rOZgGQyewnAzT\n CgAVw4hgSNa3fHcrwkAiOOfPrclvfZ6Z9C+88yQBpQy27m8eIerGKjcVIHyQFeDhiT7/\n xtZN4DYZE8eUjbNe6ZzFqvX4P4E8gfiD6Vi+zS47ez9WE5TdjVEJR7yz6v8y6gvF9moO\n KNtyca10v0n2vyFKankn/X+xTLDgesgvHb5pz1rWCKmkPTf1HNWUvuWMhp+iyRL0n8a0 /A==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori\n <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sat, 19 Jun 2021 16:31:51 +0530", "Message-ID": "<20210619110154.10301-11-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210619110154.10301-1-pbhagavatula@marvell.com>", "References": "<20210524122303.1116-1-pbhagavatula@marvell.com>\n <20210619110154.10301-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "zyoL8Tpw3qHUa8XaioYTOIVP5AAxwHV_", "X-Proofpoint-ORIG-GUID": "zyoL8Tpw3qHUa8XaioYTOIVP5AAxwHV_", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-06-19_09:2021-06-18,\n 2021-06-19 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 11/13] event/cnxk: add Rx adapter vector\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event vector support for cnxk event Rx adapter, add control path\nAPIs to get vector limits and ability to configure event vectorization\non a given Rx queue.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 2 +\n drivers/event/cnxk/cn10k_eventdev.c | 106 ++++++++++++++++++++++-\n drivers/event/cnxk/cnxk_eventdev.h | 2 +\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 25 ++++++\n drivers/net/cnxk/cnxk_ethdev.h | 2 +-\n 5 files changed, 135 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 6fdccc2ab4..0297cd3d5f 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -45,6 +45,8 @@ Features of the OCTEON cnxk SSO PMD are:\n - Lockfree Tx from event eth Tx adapter using ``DEV_TX_OFFLOAD_MT_LOCKFREE``\n capability while maintaining receive packet order.\n - Full Rx/Tx offload support defined through ethdev queue configuration.\n+- HW managed event vectorization on CN10K for packets enqueued from ethdev to\n+ eventdev configurable per each Rx queue in Rx adapter.\n \n Prerequisites and Compilation procedure\n ---------------------------------------\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex e462f770c5..e85fa4785d 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -610,7 +610,8 @@ cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,\n \telse\n \t\t*caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |\n \t\t\tRTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |\n-\t\t\tRTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID;\n+\t\t\tRTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |\n+\t\t\tRTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;\n \n \treturn 0;\n }\n@@ -671,6 +672,105 @@ cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n \treturn cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);\n }\n \n+static int\n+cn10k_sso_rx_adapter_vector_limits(\n+\tconst struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,\n+\tstruct rte_event_eth_rx_adapter_vector_limits *limits)\n+{\n+\tstruct cnxk_eth_dev *cnxk_eth_dev;\n+\tint ret;\n+\n+\tRTE_SET_USED(dev);\n+\tret = strncmp(eth_dev->device->driver->name, \"net_cn10k\", 8);\n+\tif (ret)\n+\t\treturn -ENOTSUP;\n+\n+\tcnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);\n+\tlimits->log2_sz = true;\n+\tlimits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;\n+\tlimits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;\n+\tlimits->min_timeout_ns =\n+\t\t(roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;\n+\tlimits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_sso_rx_adapter_vwqe_enable(struct cnxk_eth_dev *cnxk_eth_dev,\n+\t\t\t\tuint16_t port_id, uint16_t rq_id, uint16_t sz,\n+\t\t\t\tuint64_t tmo_ns, struct rte_mempool *vmp)\n+{\n+\tstruct roc_nix_rq *rq;\n+\n+\trq = &cnxk_eth_dev->rqs[rq_id];\n+\n+\tif (!rq->sso_ena)\n+\t\treturn -EINVAL;\n+\tif (rq->flow_tag_width == 0)\n+\t\treturn -EINVAL;\n+\n+\trq->vwqe_ena = 1;\n+\trq->vwqe_first_skip = 0;\n+\trq->vwqe_aura_handle = roc_npa_aura_handle_to_aura(vmp->pool_id);\n+\trq->vwqe_max_sz_exp = rte_log2_u32(sz);\n+\trq->vwqe_wait_tmo =\n+\t\ttmo_ns /\n+\t\t((roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100);\n+\trq->tag_mask = (port_id & 0xF) << 20;\n+\trq->tag_mask |=\n+\t\t(((port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV_VECTOR << 4))\n+\t\t<< 24;\n+\n+\treturn roc_nix_rq_modify(&cnxk_eth_dev->nix, rq, 0);\n+}\n+\n+static int\n+cn10k_sso_rx_adapter_vector_config(\n+\tconst struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,\n+\tint32_t rx_queue_id,\n+\tconst struct rte_event_eth_rx_adapter_event_vector_config *config)\n+{\n+\tstruct cnxk_eth_dev *cnxk_eth_dev;\n+\tstruct cnxk_sso_evdev *dev;\n+\tint i, rc;\n+\n+\trc = strncmp(eth_dev->device->driver->name, \"net_cn10k\", 8);\n+\tif (rc)\n+\t\treturn -EINVAL;\n+\n+\tdev = cnxk_sso_pmd_priv(event_dev);\n+\tcnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);\n+\tif (rx_queue_id < 0) {\n+\t\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\t\tcnxk_sso_updt_xae_cnt(dev, config->vector_mp,\n+\t\t\t\t\t RTE_EVENT_TYPE_ETHDEV_VECTOR);\n+\t\t\trc = cnxk_sso_xae_reconfigure(\n+\t\t\t\t(struct rte_eventdev *)(uintptr_t)event_dev);\n+\t\t\trc = cnxk_sso_rx_adapter_vwqe_enable(\n+\t\t\t\tcnxk_eth_dev, eth_dev->data->port_id, i,\n+\t\t\t\tconfig->vector_sz, config->vector_timeout_ns,\n+\t\t\t\tconfig->vector_mp);\n+\t\t\tif (rc)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\n+\t\tcnxk_sso_updt_xae_cnt(dev, config->vector_mp,\n+\t\t\t\t RTE_EVENT_TYPE_ETHDEV_VECTOR);\n+\t\trc = cnxk_sso_xae_reconfigure(\n+\t\t\t(struct rte_eventdev *)(uintptr_t)event_dev);\n+\t\trc = cnxk_sso_rx_adapter_vwqe_enable(\n+\t\t\tcnxk_eth_dev, eth_dev->data->port_id, rx_queue_id,\n+\t\t\tconfig->vector_sz, config->vector_timeout_ns,\n+\t\t\tconfig->vector_mp);\n+\t\tif (rc)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,\n \t\t\t const struct rte_eth_dev *eth_dev, uint32_t *caps)\n@@ -739,6 +839,10 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = {\n \t.eth_rx_adapter_start = cnxk_sso_rx_adapter_start,\n \t.eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,\n \n+\t.eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,\n+\t.eth_rx_adapter_event_vector_config =\n+\t\tcn10k_sso_rx_adapter_vector_config,\n+\n \t.eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,\n \t.eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,\n \t.eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 458fdc8d92..3783e0c95b 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -96,6 +96,8 @@ struct cnxk_sso_evdev {\n \tuint16_t tim_adptr_ring_cnt;\n \tuint16_t *timer_adptr_rings;\n \tuint64_t *timer_adptr_sz;\n+\tuint16_t vec_pool_cnt;\n+\tuint64_t *vec_pools;\n \t/* Dev args */\n \tuint32_t xae_cnt;\n \tuint8_t qos_queue_cnt;\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex 548d7b81ce..c4c4f5a7f4 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -40,6 +40,31 @@ cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data,\n \t\tdev->adptr_xae_cnt += rxq->qconf.mp->size;\n \t\tbreak;\n \t}\n+\tcase RTE_EVENT_TYPE_ETHDEV_VECTOR: {\n+\t\tstruct rte_mempool *mp = data;\n+\t\tuint64_t *old_ptr;\n+\n+\t\tfor (i = 0; i < dev->vec_pool_cnt; i++) {\n+\t\t\tif ((uint64_t)mp == dev->vec_pools[i])\n+\t\t\t\treturn;\n+\t\t}\n+\n+\t\tdev->vec_pool_cnt++;\n+\t\told_ptr = dev->vec_pools;\n+\t\tdev->vec_pools =\n+\t\t\trte_realloc(dev->vec_pools,\n+\t\t\t\t sizeof(uint64_t) * dev->vec_pool_cnt, 0);\n+\t\tif (dev->vec_pools == NULL) {\n+\t\t\tdev->adptr_xae_cnt += mp->size;\n+\t\t\tdev->vec_pools = old_ptr;\n+\t\t\tdev->vec_pool_cnt--;\n+\t\t\treturn;\n+\t\t}\n+\t\tdev->vec_pools[dev->vec_pool_cnt - 1] = (uint64_t)mp;\n+\n+\t\tdev->adptr_xae_cnt += mp->size;\n+\t\tbreak;\n+\t}\n \tcase RTE_EVENT_TYPE_TIMER: {\n \t\tstruct cnxk_tim_ring *timr = data;\n \t\tuint16_t *old_ring_ptr;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 4eead03905..2528b3cdaa 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -238,7 +238,7 @@ struct cnxk_eth_txq_sp {\n } __plt_cache_aligned;\n \n static inline struct cnxk_eth_dev *\n-cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n+cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev)\n {\n \treturn eth_dev->data->dev_private;\n }\n", "prefixes": [ "v2", "11/13" ] }