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GET /api/patches/94329/?format=api
{ "id": 94329, "url": "https://patches.dpdk.org/api/patches/94329/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210617110005.4132926-5-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210617110005.4132926-5-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210617110005.4132926-5-jiawenwu@trustnetic.com", "date": "2021-06-17T10:59:50", "name": "[v6,04/19] net/ngbe: define registers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "ad851f3e331c14776bc36d30613b01ae2492713e", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 3961, "url": "https://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210617110005.4132926-5-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 17372, "url": "https://patches.dpdk.org/api/series/17372/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17372", "date": "2021-06-17T10:59:46", "name": "net: ngbe PMD", "version": 6, "mbox": "https://patches.dpdk.org/series/17372/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94329/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/94329/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B010BA0C4D;\n\tThu, 17 Jun 2021 12:58:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A30D9410FA;\n\tThu, 17 Jun 2021 12:58:19 +0200 (CEST)", "from smtpbg511.qq.com (smtpbg511.qq.com [203.205.250.109])\n by mails.dpdk.org (Postfix) with ESMTP id A8DFD410EB\n for <dev@dpdk.org>; Thu, 17 Jun 2021 12:58:15 +0200 (CEST)", "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Thu, 17 Jun 2021 18:58:10 +0800 (CST)" ], "X-QQ-mid": "bizesmtp46t1623927490tzqx37fc", "X-QQ-SSF": "01400000000000D0E000B00A0000000", "X-QQ-FEAT": "xmzaef4TE3f/ThGiewy/0lbpHbnA80l+qPGArs6R0xXrO89mqm8FCfa4DjUh+\n 88TpC6s6hwXLBPvEtyeDP5LusgHWv1XbEHgczWqKWRCU4kqydENW1+HmTiM9QBfze1U77lZ\n FiiIznDD086BuYk0bc+yWOpR1Cu1m9tRvxZ4Y5aWJSC4HIXZiqXuW5U7i8n0vLjl/P2Ve/u\n EMCrIU2Kvvof04XnYrRn5X8OD5tqJ4DYB7OmRzyCTr4MxRUHu1Dg6Hiq3W6eEt2ceNf3LEw\n xHPzHH47SpAyueEjTHyGC3OcA2FhGun1WGFqltPrmgDUPYetBv/G+DIR8d5FaGSMymJfe7M\n MIPZEOUvoqQ3uCjlOw=", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Thu, 17 Jun 2021 18:59:50 +0800", "Message-Id": "<20210617110005.4132926-5-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210617110005.4132926-1-jiawenwu@trustnetic.com>", "References": "<20210617110005.4132926-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v6 04/19] net/ngbe: define registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Define all registers that will be used.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/ngbe/base/ngbe_regs.h | 1490 +++++++++++++++++++++++++++++\n 1 file changed, 1490 insertions(+)\n create mode 100644 drivers/net/ngbe/base/ngbe_regs.h", "diff": "diff --git a/drivers/net/ngbe/base/ngbe_regs.h b/drivers/net/ngbe/base/ngbe_regs.h\nnew file mode 100644\nindex 0000000000..737bd796a1\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_regs.h\n@@ -0,0 +1,1490 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2020 Beijing WangXun Technology Co., Ltd.\n+ * Copyright(c) 2010-2017 Intel Corporation\n+ */\n+\n+#ifndef _NGBE_REGS_H_\n+#define _NGBE_REGS_H_\n+\n+#define NGBE_PVMBX_QSIZE (16) /* 16*4B */\n+#define NGBE_PVMBX_BSIZE (NGBE_PVMBX_QSIZE * 4)\n+\n+#define NGBE_REMOVED(a) (0)\n+\n+#define NGBE_REG_DUMMY 0xFFFFFF\n+\n+#define MS8(shift, mask) (((u8)(mask)) << (shift))\n+#define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift))\n+#define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask))\n+\n+#define MS16(shift, mask) (((u16)(mask)) << (shift))\n+#define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift))\n+#define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask))\n+\n+#define MS32(shift, mask) (((u32)(mask)) << (shift))\n+#define LS32(val, shift, mask) (((u32)(val) & (u32)(mask)) << (shift))\n+#define RS32(reg, shift, mask) (((u32)(reg) >> (shift)) & (u32)(mask))\n+\n+#define MS64(shift, mask) (((u64)(mask)) << (shift))\n+#define LS64(val, shift, mask) (((u64)(val) & (u64)(mask)) << (shift))\n+#define RS64(reg, shift, mask) (((u64)(reg) >> (shift)) & (u64)(mask))\n+\n+#define MS(shift, mask) MS32(shift, mask)\n+#define LS(val, shift, mask) LS32(val, shift, mask)\n+#define RS(reg, shift, mask) RS32(reg, shift, mask)\n+\n+#define ROUND_UP(x, y) (((x) + (y) - 1) / (y) * (y))\n+#define ROUND_DOWN(x, y) ((x) / (y) * (y))\n+#define ROUND_OVER(x, maxbits, unitbits) \\\n+\t((x) >= 1 << (maxbits) ? 0 : (x) >> (unitbits))\n+\n+/* autoc bits definition */\n+#define NGBE_AUTOC NGBE_REG_DUMMY\n+#define NGBE_AUTOC_FLU MS64(0, 0x1)\n+#define NGBE_AUTOC_10G_PMA_PMD_MASK MS64(7, 0x3) /* parallel */\n+#define NGBE_AUTOC_10G_XAUI LS64(0, 7, 0x3)\n+#define NGBE_AUTOC_10G_KX4 LS64(1, 7, 0x3)\n+#define NGBE_AUTOC_10G_CX4 LS64(2, 7, 0x3)\n+#define NGBE_AUTOC_10G_KR LS64(3, 7, 0x3) /* fixme */\n+#define NGBE_AUTOC_1G_PMA_PMD_MASK MS64(9, 0x7)\n+#define NGBE_AUTOC_1G_BX LS64(0, 9, 0x7)\n+#define NGBE_AUTOC_1G_KX LS64(1, 9, 0x7)\n+#define NGBE_AUTOC_1G_SFI LS64(0, 9, 0x7)\n+#define NGBE_AUTOC_1G_KX_BX LS64(1, 9, 0x7)\n+#define NGBE_AUTOC_AN_RESTART MS64(12, 0x1)\n+#define NGBE_AUTOC_LMS_MASK MS64(13, 0x7)\n+#define NGBE_AUTOC_LMS_10G LS64(3, 13, 0x7)\n+#define NGBE_AUTOC_LMS_KX4_KX_KR LS64(4, 13, 0x7)\n+#define NGBE_AUTOC_LMS_SGMII_1G_100M LS64(5, 13, 0x7)\n+#define NGBE_AUTOC_LMS_KX4_KX_KR_1G_AN LS64(6, 13, 0x7)\n+#define NGBE_AUTOC_LMS_KX4_KX_KR_SGMII LS64(7, 13, 0x7)\n+#define NGBE_AUTOC_LMS_1G_LINK_NO_AN LS64(0, 13, 0x7)\n+#define NGBE_AUTOC_LMS_10G_LINK_NO_AN LS64(1, 13, 0x7)\n+#define NGBE_AUTOC_LMS_1G_AN LS64(2, 13, 0x7)\n+#define NGBE_AUTOC_LMS_KX4_AN LS64(4, 13, 0x7)\n+#define NGBE_AUTOC_LMS_KX4_AN_1G_AN LS64(6, 13, 0x7)\n+#define NGBE_AUTOC_LMS_ATTACH_TYPE LS64(7, 13, 0x7)\n+#define NGBE_AUTOC_LMS_AN MS64(15, 0x7)\n+\n+#define NGBE_AUTOC_KR_SUPP MS64(16, 0x1)\n+#define NGBE_AUTOC_FECR MS64(17, 0x1)\n+#define NGBE_AUTOC_FECA MS64(18, 0x1)\n+#define NGBE_AUTOC_AN_RX_ALIGN MS64(18, 0x1F) /* fixme */\n+#define NGBE_AUTOC_AN_RX_DRIFT MS64(23, 0x3)\n+#define NGBE_AUTOC_AN_RX_LOOSE MS64(24, 0x3)\n+#define NGBE_AUTOC_PD_TMR MS64(25, 0x3)\n+#define NGBE_AUTOC_RF MS64(27, 0x1)\n+#define NGBE_AUTOC_ASM_PAUSE MS64(29, 0x1)\n+#define NGBE_AUTOC_SYM_PAUSE MS64(28, 0x1)\n+#define NGBE_AUTOC_PAUSE MS64(28, 0x3)\n+#define NGBE_AUTOC_KX_SUPP MS64(30, 0x1)\n+#define NGBE_AUTOC_KX4_SUPP MS64(31, 0x1)\n+\n+#define NGBE_AUTOC_10GS_PMA_PMD_MASK MS64(48, 0x3) /* serial */\n+#define NGBE_AUTOC_10GS_KR LS64(0, 48, 0x3)\n+#define NGBE_AUTOC_10GS_XFI LS64(1, 48, 0x3)\n+#define NGBE_AUTOC_10GS_SFI LS64(2, 48, 0x3)\n+#define NGBE_AUTOC_LINK_DIA_MASK MS64(60, 0x7)\n+#define NGBE_AUTOC_LINK_DIA_D3_MASK LS64(5, 60, 0x7)\n+\n+#define NGBE_AUTOC_SPEED_MASK MS64(32, 0xFFFF)\n+#define NGBD_AUTOC_SPEED(r) RS64(r, 32, 0xFFFF)\n+#define NGBE_AUTOC_SPEED(v) LS64(v, 32, 0xFFFF)\n+#define NGBE_LINK_SPEED_UNKNOWN 0\n+#define NGBE_LINK_SPEED_10M_FULL 0x0002\n+#define NGBE_LINK_SPEED_100M_FULL 0x0008\n+#define NGBE_LINK_SPEED_1GB_FULL 0x0020\n+#define NGBE_LINK_SPEED_2_5GB_FULL 0x0400\n+#define NGBE_LINK_SPEED_5GB_FULL 0x0800\n+#define NGBE_LINK_SPEED_10GB_FULL 0x0080\n+#define NGBE_LINK_SPEED_40GB_FULL 0x0100\n+#define NGBE_AUTOC_AUTONEG MS64(63, 0x1)\n+\n+\n+\n+/* Hardware Datapath:\n+ * RX: / Queue <- Filter \\\n+ * Host | TC <=> SEC <=> MAC <=> PHY\n+ * TX: \\ Queue -> Filter /\n+ *\n+ * Packet Filter:\n+ * RX: RSS < FDIR < Filter < Encrypt\n+ *\n+ * Macro Argument Naming:\n+ * rp = ring pair [0,127]\n+ * tc = traffic class [0,7]\n+ * up = user priority [0,7]\n+ * pi = pool index [0,63]\n+ * r = register\n+ * v = value\n+ * s = shift\n+ * m = mask\n+ * i,j,k = array index\n+ * H,L = high/low bits\n+ * HI,LO = high/low state\n+ */\n+\n+#define NGBE_ETHPHYIF NGBE_REG_DUMMY\n+#define NGBE_ETHPHYIF_MDIO_ACT MS(1, 0x1)\n+#define NGBE_ETHPHYIF_MDIO_MODE MS(2, 0x1)\n+#define NGBE_ETHPHYIF_MDIO_BASE(r) RS(r, 3, 0x1F)\n+#define NGBE_ETHPHYIF_MDIO_SHARED MS(13, 0x1)\n+#define NGBE_ETHPHYIF_SPEED_10M MS(17, 0x1)\n+#define NGBE_ETHPHYIF_SPEED_100M MS(18, 0x1)\n+#define NGBE_ETHPHYIF_SPEED_1G MS(19, 0x1)\n+#define NGBE_ETHPHYIF_SPEED_2_5G MS(20, 0x1)\n+#define NGBE_ETHPHYIF_SPEED_10G MS(21, 0x1)\n+#define NGBE_ETHPHYIF_SGMII_ENABLE MS(25, 0x1)\n+#define NGBE_ETHPHYIF_INT_PHY_MODE MS(24, 0x1)\n+#define NGBE_ETHPHYIF_IO_XPCS MS(30, 0x1)\n+#define NGBE_ETHPHYIF_IO_EPHY MS(31, 0x1)\n+\n+/******************************************************************************\n+ * Chip Registers\n+ ******************************************************************************/\n+/**\n+ * Chip Status\n+ **/\n+#define NGBE_PWR\t\t0x010000\n+#define NGBE_PWR_LAN(r)\tRS(r, 28, 0xC)\n+#define NGBE_PWR_LAN_0\t(1)\n+#define NGBE_PWR_LAN_1\t(2)\n+#define NGBE_PWR_LAN_2\t(3)\n+#define NGBE_PWR_LAN_3\t(4)\n+#define NGBE_CTL\t\t0x010004\n+#define NGBE_LOCKPF\t\t0x010008\n+#define NGBE_RST\t\t0x01000C\n+#define NGBE_RST_SW\t\tMS(0, 0x1)\n+#define NGBE_RST_LAN(i)\tMS(((i) + 1), 0x1)\n+#define NGBE_RST_FW\t\tMS(5, 0x1)\n+#define NGBE_RST_ETH(i)\tMS(((i) + 29), 0x1)\n+#define NGBE_RST_GLB\t\tMS(31, 0x1)\n+#define NGBE_RST_DEFAULT\t(NGBE_RST_SW | \\\n+\t\t\t\tNGBE_RST_LAN(0) | \\\n+\t\t\t\tNGBE_RST_LAN(1) | \\\n+\t\t\t\tNGBE_RST_LAN(2) | \\\n+\t\t\t\tNGBE_RST_LAN(3))\n+#define NGBE_PROB\t\t\t0x010010\n+#define NGBE_IODRV\t\t\t0x010024\n+#define NGBE_STAT\t\t\t0x010028\n+#define NGBE_STAT_MNGINIT\t\tMS(0, 0x1)\n+#define NGBE_STAT_MNGVETO\t\tMS(8, 0x1)\n+#define NGBE_STAT_ECCLAN0\t\tMS(16, 0x1)\n+#define NGBE_STAT_ECCLAN1\t\tMS(17, 0x1)\n+#define NGBE_STAT_ECCLAN2\t\tMS(18, 0x1)\n+#define NGBE_STAT_ECCLAN3\t\tMS(19, 0x1)\n+#define NGBE_STAT_ECCMNG\t\tMS(20, 0x1)\n+#define NGBE_STAT_ECCPCORE\t\tMS(21, 0X1)\n+#define NGBE_STAT_ECCPCIW\t\tMS(22, 0x1)\n+#define NGBE_STAT_ECCPCIEPHY\t\tMS(23, 0x1)\n+#define NGBE_STAT_ECCFMGR\t\tMS(24, 0x1)\n+#define NGBE_STAT_GPHY_IN_RST(i)\tMS(((i) + 9), 0x1)\n+#define NGBE_RSTSTAT\t\t\t0x010030\n+#define NGBE_RSTSTAT_PROG\t\tMS(20, 0x1)\n+#define NGBE_RSTSTAT_PREP\t\tMS(19, 0x1)\n+#define NGBE_RSTSTAT_TYPE_MASK\tMS(16, 0x7)\n+#define NGBE_RSTSTAT_TYPE(r)\t\tRS(r, 16, 0x7)\n+#define NGBE_RSTSTAT_TYPE_PE\t\tLS(0, 16, 0x7)\n+#define NGBE_RSTSTAT_TYPE_PWR\t\tLS(1, 16, 0x7)\n+#define NGBE_RSTSTAT_TYPE_HOT\t\tLS(2, 16, 0x7)\n+#define NGBE_RSTSTAT_TYPE_SW\t\tLS(3, 16, 0x7)\n+#define NGBE_RSTSTAT_TYPE_FW\t\tLS(4, 16, 0x7)\n+#define NGBE_RSTSTAT_TMRINIT_MASK\tMS(8, 0xFF)\n+#define NGBE_RSTSTAT_TMRINIT(v)\tLS(v, 8, 0xFF)\n+#define NGBE_RSTSTAT_TMRCNT_MASK\tMS(0, 0xFF)\n+#define NGBE_RSTSTAT_TMRCNT(v)\tLS(v, 0, 0xFF)\n+#define NGBE_PWRTMR\t\t\t0x010034\n+\n+/**\n+ * SPI(Flash)\n+ **/\n+#define NGBE_SPICMD 0x010104\n+#define NGBE_SPICMD_ADDR(v) LS(v, 0, 0xFFFFFF)\n+#define NGBE_SPICMD_CLK(v) LS(v, 25, 0x7)\n+#define NGBE_SPICMD_CMD(v) LS(v, 28, 0x7)\n+#define NGBE_SPIDAT 0x010108\n+#define NGBE_SPIDAT_BYPASS MS(31, 0x1)\n+#define NGBE_SPIDAT_STATUS(v) LS(v, 16, 0xFF)\n+#define NGBE_SPIDAT_OPDONE MS(0, 0x1)\n+#define NGBE_SPISTAT 0x01010C\n+#define NGBE_SPISTAT_OPDONE MS(0, 0x1)\n+#define NGBE_SPISTAT_BPFLASH MS(31, 0x1)\n+#define NGBE_SPIUSRCMD 0x010110\n+#define NGBE_SPICFG0 0x010114\n+#define NGBE_SPICFG1 0x010118\n+\n+/* FMGR Registers */\n+#define NGBE_ILDRSTAT 0x010120\n+#define NGBE_ILDRSTAT_PCIRST MS(0, 0x1)\n+#define NGBE_ILDRSTAT_PWRRST MS(1, 0x1)\n+#define NGBE_ILDRSTAT_SWRST MS(11, 0x1)\n+#define NGBE_ILDRSTAT_SWRST_LAN0 MS(13, 0x1)\n+#define NGBE_ILDRSTAT_SWRST_LAN1 MS(14, 0x1)\n+#define NGBE_ILDRSTAT_SWRST_LAN2 MS(15, 0x1)\n+#define NGBE_ILDRSTAT_SWRST_LAN3 MS(16, 0x1)\n+\n+#define NGBE_SRAM 0x010124\n+#define NGBE_SRAM_SZ(v) LS(v, 28, 0x7)\n+#define NGBE_SRAMCTLECC 0x010130\n+#define NGBE_SRAMINJECC 0x010134\n+#define NGBE_SRAMECC 0x010138\n+\n+/* Sensors for PVT(Process Voltage Temperature) */\n+#define NGBE_TSCTRL\t\t\t0x010300\n+#define NGBE_TSCTRL_EVALMD\t\tMS(31, 0x1)\n+#define NGBE_TSEN\t\t\t0x010304\n+#define NGBE_TSEN_ENA\t\t\tMS(0, 0x1)\n+#define NGBE_TSSTAT\t\t\t0x010308\n+#define NGBE_TSSTAT_VLD\t\tMS(16, 0x1)\n+#define NGBE_TSSTAT_DATA(r)\t\tRS(r, 0, 0x3FF)\n+#define NGBE_TSATHRE\t\t\t0x01030C\n+#define NGBE_TSDTHRE\t\t\t0x010310\n+#define NGBE_TSINTR\t\t\t0x010314\n+#define NGBE_TSINTR_AEN\t\tMS(0, 0x1)\n+#define NGBE_TSINTR_DEN\t\tMS(1, 0x1)\n+#define NGBE_TSALM\t\t\t0x010318\n+#define NGBE_TSALM_LO\t\t\tMS(0, 0x1)\n+#define NGBE_TSALM_HI\t\t\tMS(1, 0x1)\n+\n+#define NGBE_EFUSE_WDATA0 0x010320\n+#define NGBE_EFUSE_WDATA1 0x010324\n+#define NGBE_EFUSE_RDATA0 0x010328\n+#define NGBE_EFUSE_RDATA1 0x01032C\n+#define NGBE_EFUSE_STATUS 0x010330\n+\n+/******************************************************************************\n+ * Port Registers\n+ ******************************************************************************/\n+/* Internal PHY reg_offset [0,31] */\n+#define NGBE_PHY_CONFIG(reg_offset)\t(0x014000 + (reg_offset) * 4)\n+\n+/* Port Control */\n+#define NGBE_PORTCTL 0x014400\n+#define NGBE_PORTCTL_VLANEXT MS(0, 0x1)\n+#define NGBE_PORTCTL_ETAG MS(1, 0x1)\n+#define NGBE_PORTCTL_QINQ MS(2, 0x1)\n+#define NGBE_PORTCTL_DRVLOAD MS(3, 0x1)\n+#define NGBE_PORTCTL_NUMVT_MASK MS(12, 0x1)\n+#define NGBE_PORTCTL_NUMVT_8 LS(1, 12, 0x1)\n+#define NGBE_PORTCTL_RSTDONE MS(14, 0x1)\n+#define NGBE_PORTCTL_TEREDODIA MS(27, 0x1)\n+#define NGBE_PORTCTL_GENEVEDIA MS(28, 0x1)\n+#define NGBE_PORTCTL_VXLANGPEDIA MS(30, 0x1)\n+#define NGBE_PORTCTL_VXLANDIA MS(31, 0x1)\n+\n+/* Port Status */\n+#define NGBE_PORTSTAT 0x014404\n+#define NGBE_PORTSTAT_BW_MASK MS(1, 0x7)\n+#define NGBE_PORTSTAT_BW_1G MS(1, 0x1)\n+#define NGBE_PORTSTAT_BW_100M MS(2, 0x1)\n+#define NGBE_PORTSTAT_BW_10M MS(3, 0x1)\n+#define NGBE_PORTSTAT_ID(r) RS(r, 8, 0x3)\n+\n+#define NGBE_EXTAG 0x014408\n+#define NGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF)\n+#define NGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF)\n+#define NGBE_EXTAG_VLAN_MASK MS(16, 0xFFFF)\n+#define NGBE_EXTAG_VLAN(v) LS(v, 16, 0xFFFF)\n+\n+#define NGBE_TCPTIME 0x014420\n+\n+#define NGBE_LEDCTL 0x014424\n+#define NGBE_LEDCTL_SEL(s) MS((s), 0x1)\n+#define NGBE_LEDCTL_OD(s) MS(((s) + 16), 0x1)\n+\t/* s=1G(1),100M(2),10M(3) */\n+#define NGBE_LEDCTL_100M (NGBE_LEDCTL_SEL(2) | NGBE_LEDCTL_OD(2))\n+\n+#define NGBE_TAGTPID(i) (0x014430 + (i) * 4) /*0-3*/\n+#define NGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF)\n+#define NGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF)\n+#define NGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF)\n+#define NGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF)\n+\n+#define NGBE_LAN_SPEED\t\t\t0x014440\n+#define NGBE_LAN_SPEED_MASK\t\tMS(0, 0x3)\n+\n+/* GPIO Registers */\n+#define NGBE_GPIODATA\t\t\t0x014800\n+#define NGBE_GPIOBIT_0 MS(0, 0x1) /* O:tx fault */\n+#define NGBE_GPIOBIT_1 MS(1, 0x1) /* O:tx disabled */\n+#define NGBE_GPIOBIT_2 MS(2, 0x1) /* I:sfp module absent */\n+#define NGBE_GPIOBIT_3 MS(3, 0x1) /* I:rx signal lost */\n+#define NGBE_GPIOBIT_4 MS(4, 0x1) /* O:rate select, 1G(0) 10G(1) */\n+#define NGBE_GPIOBIT_5 MS(5, 0x1) /* O:rate select, 1G(0) 10G(1) */\n+#define NGBE_GPIOBIT_6 MS(6, 0x1) /* I:ext phy interrupt */\n+#define NGBE_GPIOBIT_7 MS(7, 0x1) /* I:fan speed alarm */\n+#define NGBE_GPIODIR\t\t\t0x014804\n+#define NGBE_GPIODIR_DDR(v)\t\tLS(v, 0, 0x3)\n+#define NGBE_GPIOCTL\t\t\t0x014808\n+#define NGBE_GPIOINTEN\t\t\t0x014830\n+#define NGBE_GPIOINTEN_INT(v)\t\tLS(v, 0, 0x3)\n+#define NGBE_GPIOINTMASK\t\t0x014834\n+#define NGBE_GPIOINTTYPE\t\t0x014838\n+#define NGBE_GPIOINTTYPE_LEVEL(v)\tLS(v, 0, 0x3)\n+#define NGBE_GPIOINTPOL\t\t\t0x01483C\n+#define NGBE_GPIOINTPOL_ACT(v)\tLS(v, 0, 0x3)\n+#define NGBE_GPIOINTSTAT\t\t0x014840\n+#define NGBE_GPIOINTDB\t\t\t0x014848\n+#define NGBE_GPIOEOI\t\t\t0x01484C\n+#define NGBE_GPIODAT\t\t\t0x014850\n+\n+/* TPH */\n+#define NGBE_TPHCFG 0x014F00\n+\n+/******************************************************************************\n+ * Transmit DMA Registers\n+ ******************************************************************************/\n+/* TDMA Control */\n+#define NGBE_DMATXCTRL\t\t\t0x018000\n+#define NGBE_DMATXCTRL_ENA\t\tMS(0, 0x1)\n+#define NGBE_DMATXCTRL_TPID_MASK\tMS(16, 0xFFFF)\n+#define NGBE_DMATXCTRL_TPID(v)\tLS(v, 16, 0xFFFF)\n+#define NGBE_POOLTXENA(i)\t\t(0x018004 + (i) * 4) /*0*/\n+#define NGBE_PRBTXDMACTL\t\t0x018010\n+#define NGBE_ECCTXDMACTL\t\t0x018014\n+#define NGBE_ECCTXDMAINJ\t\t0x018018\n+#define NGBE_ECCTXDMA\t\t\t0x01801C\n+#define NGBE_PBTXDMATH\t\t\t0x018020\n+#define NGBE_QPTXLLI\t\t\t0x018040\n+#define NGBE_POOLTXLBET\t\t\t0x018050\n+#define NGBE_POOLTXASET\t\t\t0x018058\n+#define NGBE_POOLTXASMAC\t\t0x018060\n+#define NGBE_POOLTXASVLAN\t\t0x018070\n+#define NGBE_POOLTXDSA\t\t\t0x0180A0\n+#define NGBE_POOLTAG(pl)\t\t(0x018100 + (pl) * 4) /*0-7*/\n+#define NGBE_POOLTAG_VTAG(v)\t\tLS(v, 0, 0xFFFF)\n+#define NGBE_POOLTAG_VTAG_MASK\tMS(0, 0xFFFF)\n+#define TXGBD_POOLTAG_VTAG_UP(r)\tRS(r, 13, 0x7)\n+#define NGBE_POOLTAG_TPIDSEL(v)\tLS(v, 24, 0x7)\n+#define NGBE_POOLTAG_ETAG_MASK\tMS(27, 0x3)\n+#define NGBE_POOLTAG_ETAG\t\tLS(2, 27, 0x3)\n+#define NGBE_POOLTAG_ACT_MASK\t\tMS(30, 0x3)\n+#define NGBE_POOLTAG_ACT_ALWAYS\tLS(1, 30, 0x3)\n+#define NGBE_POOLTAG_ACT_NEVER\tLS(2, 30, 0x3)\n+\n+/* Queue Arbiter(QoS) */\n+#define NGBE_QARBTXCTL\t\t\t0x018200\n+#define NGBE_QARBTXCTL_DA\t\tMS(6, 0x1)\n+#define NGBE_QARBTXRATE\t\t\t0x018404\n+#define NGBE_QARBTXRATE_MIN(v)\tLS(v, 0, 0x3FFF)\n+#define NGBE_QARBTXRATE_MAX(v)\tLS(v, 16, 0x3FFF)\n+\n+/* ETAG */\n+#define NGBE_POOLETAG(pl) (0x018700 + (pl) * 4)\n+\n+/******************************************************************************\n+ * Receive DMA Registers\n+ ******************************************************************************/\n+/* Receive Control */\n+#define NGBE_ARBRXCTL\t\t\t0x012000\n+#define NGBE_ARBRXCTL_DIA\t\tMS(6, 0x1)\n+#define NGBE_POOLRXENA(i)\t\t(0x012004 + (i) * 4) /*0*/\n+#define NGBE_PRBRDMA\t\t\t0x012010\n+#define NGBE_ECCRXDMACTL\t\t0x012014\n+#define NGBE_ECCRXDMAINJ\t\t0x012018\n+#define NGBE_ECCRXDMA\t\t\t0x01201C\n+#define NGBE_POOLRXDNA\t\t\t0x0120A0\n+#define NGBE_QPRXDROP\t\t\t0x012080\n+#define NGBE_QPRXSTRPVLAN\t\t0x012090\n+\n+/******************************************************************************\n+ * Packet Buffer\n+ ******************************************************************************/\n+/* Flow Control */\n+#define NGBE_FCXOFFTM\t\t\t0x019200\n+#define NGBE_FCWTRLO\t\t\t0x019220\n+#define NGBE_FCWTRLO_TH(v)\t\tLS(v, 10, 0x1FF) /*KB*/\n+#define NGBE_FCWTRLO_XON\t\tMS(31, 0x1)\n+#define NGBE_FCWTRHI\t\t\t0x019260\n+#define NGBE_FCWTRHI_TH(v)\t\tLS(v, 10, 0x1FF) /*KB*/\n+#define NGBE_FCWTRHI_XOFF\t\tMS(31, 0x1)\n+#define NGBE_RXFCRFSH\t\t\t0x0192A0\n+#define NGBE_RXFCFSH_TIME(v)\t\tLS(v, 0, 0xFFFF)\n+#define NGBE_FCSTAT\t\t\t0x01CE00\n+#define NGBE_FCSTAT_DLNK\t\tMS(0, 0x1)\n+#define NGBE_FCSTAT_ULNK\t\tMS(8, 0x1)\n+\n+#define NGBE_RXFCCFG 0x011090\n+#define NGBE_RXFCCFG_FC MS(0, 0x1)\n+#define NGBE_TXFCCFG 0x0192A4\n+#define NGBE_TXFCCFG_FC MS(3, 0x1)\n+\n+/* Data Buffer */\n+#define NGBE_PBRXCTL 0x019000\n+#define NGBE_PBRXCTL_ST MS(0, 0x1)\n+#define NGBE_PBRXCTL_ENA MS(31, 0x1)\n+#define NGBE_PBRXSTAT 0x019004\n+#define NGBE_PBRXSIZE 0x019020\n+#define NGBE_PBRXSIZE_KB(v) LS(v, 10, 0x3F)\n+\n+#define NGBE_PBRXOFTMR 0x019094\n+#define NGBE_PBRXDBGCMD 0x019090\n+#define NGBE_PBRXDBGDAT 0x0190A0\n+\n+#define NGBE_PBTXSIZE 0x01CC00\n+\n+/* LLI */\n+#define NGBE_PBRXLLI 0x19080\n+#define NGBE_PBRXLLI_SZLT(v) LS(v, 0, 0xFFF)\n+#define NGBE_PBRXLLI_UPLT(v) LS(v, 16, 0x7)\n+#define NGBE_PBRXLLI_UPEA MS(19, 0x1)\n+\n+/* Port Arbiter(QoS) */\n+#define NGBE_PARBTXCTL 0x01CD00\n+#define NGBE_PARBTXCTL_DA MS(6, 0x1)\n+\n+/******************************************************************************\n+ * Packet Filter (L2-7)\n+ ******************************************************************************/\n+/**\n+ * Receive Scaling\n+ **/\n+#define NGBE_POOLRSS(pl)\t\t(0x019300 + (pl) * 4) /*0-7*/\n+#define NGBE_POOLRSS_L4HDR\t\tMS(1, 0x1)\n+#define NGBE_POOLRSS_L3HDR\t\tMS(2, 0x1)\n+#define NGBE_POOLRSS_L2HDR\t\tMS(3, 0x1)\n+#define NGBE_POOLRSS_L2TUN\t\tMS(4, 0x1)\n+#define NGBE_POOLRSS_TUNHDR\t\tMS(5, 0x1)\n+#define NGBE_RSSTBL(i)\t\t\t(0x019400 + (i) * 4) /*32*/\n+#define NGBE_RSSKEY(i)\t\t\t(0x019480 + (i) * 4) /*10*/\n+#define NGBE_RACTL\t\t\t0x0194F4\n+#define NGBE_RACTL_RSSENA\t\tMS(2, 0x1)\n+#define NGBE_RACTL_RSSMASK\t\tMS(16, 0xFFFF)\n+#define NGBE_RACTL_RSSIPV4TCP\t\tMS(16, 0x1)\n+#define NGBE_RACTL_RSSIPV4\t\tMS(17, 0x1)\n+#define NGBE_RACTL_RSSIPV6\t\tMS(20, 0x1)\n+#define NGBE_RACTL_RSSIPV6TCP\t\tMS(21, 0x1)\n+#define NGBE_RACTL_RSSIPV4UDP\t\tMS(22, 0x1)\n+#define NGBE_RACTL_RSSIPV6UDP\t\tMS(23, 0x1)\n+\n+/**\n+ * Flow Director\n+ **/\n+#define PERFECT_BUCKET_64KB_HASH_MASK\t0x07FF\t/* 11 bits */\n+#define PERFECT_BUCKET_128KB_HASH_MASK\t0x0FFF\t/* 12 bits */\n+#define PERFECT_BUCKET_256KB_HASH_MASK\t0x1FFF\t/* 13 bits */\n+#define SIG_BUCKET_64KB_HASH_MASK\t0x1FFF\t/* 13 bits */\n+#define SIG_BUCKET_128KB_HASH_MASK\t0x3FFF\t/* 14 bits */\n+#define SIG_BUCKET_256KB_HASH_MASK\t0x7FFF\t/* 15 bits */\n+\n+/**\n+ * 5-tuple Filter\n+ **/\n+#define NGBE_5TFPORT(i)\t\t\t(0x019A00 + (i) * 4) /*0-7*/\n+#define NGBE_5TFPORT_SRC(v)\t\tLS(v, 0, 0xFFFF)\n+#define NGBE_5TFPORT_DST(v)\t\tLS(v, 16, 0xFFFF)\n+#define NGBE_5TFCTL0(i)\t\t\t(0x019C00 + (i) * 4) /*0-7*/\n+#define NGBE_5TFCTL0_PROTO(v)\t\tLS(v, 0, 0x3)\n+enum ngbe_5tuple_protocol {\n+\tNGBE_5TF_PROT_TCP = 0,\n+\tNGBE_5TF_PROT_UDP,\n+\tNGBE_5TF_PROT_SCTP,\n+\tNGBE_5TF_PROT_NONE,\n+};\n+#define NGBE_5TFCTL0_PRI(v)\t\tLS(v, 2, 0x7)\n+#define NGBE_5TFCTL0_POOL(v)\t\tLS(v, 8, 0x7)\n+#define NGBE_5TFCTL0_MASK\t\tMS(27, 0xF)\n+#define NGBE_5TFCTL0_MSPORT\t\tMS(27, 0x1)\n+#define NGBE_5TFCTL0_MDPORT\t\tMS(28, 0x1)\n+#define NGBE_5TFCTL0_MPROTO\t\tMS(29, 0x1)\n+#define NGBE_5TFCTL0_MPOOL\t\tMS(30, 0x1)\n+#define NGBE_5TFCTL0_ENA\t\tMS(31, 0x1)\n+#define NGBE_5TFCTL1(i)\t\t\t(0x019E00 + (i) * 4) /*0-7*/\n+#define NGBE_5TFCTL1_CHKSZ\t\tMS(12, 0x1)\n+#define NGBE_5TFCTL1_LLI\t\tMS(20, 0x1)\n+#define NGBE_5TFCTL1_QP(v)\t\tLS(v, 21, 0x7)\n+\n+/**\n+ * Storm Control\n+ **/\n+#define NGBE_STRMCTL 0x015004\n+#define NGBE_STRMCTL_MCPNSH MS(0, 0x1)\n+#define NGBE_STRMCTL_MCDROP MS(1, 0x1)\n+#define NGBE_STRMCTL_BCPNSH MS(2, 0x1)\n+#define NGBE_STRMCTL_BCDROP MS(3, 0x1)\n+#define NGBE_STRMCTL_DFTPOOL MS(4, 0x1)\n+#define NGBE_STRMCTL_ITVL(v) LS(v, 8, 0x3FF)\n+#define NGBE_STRMTH 0x015008\n+#define NGBE_STRMTH_MC(v) LS(v, 0, 0xFFFF)\n+#define NGBE_STRMTH_BC(v) LS(v, 16, 0xFFFF)\n+\n+/******************************************************************************\n+ * Ether Flow\n+ ******************************************************************************/\n+#define NGBE_PSRCTL\t\t 0x015000\n+#define NGBE_PSRCTL_TPE\t MS(4, 0x1)\n+#define NGBE_PSRCTL_ADHF12_MASK MS(5, 0x3)\n+#define NGBE_PSRCTL_ADHF12(v) LS(v, 5, 0x3)\n+#define NGBE_PSRCTL_UCHFENA\t MS(7, 0x1)\n+#define NGBE_PSRCTL_MCHFENA\t MS(7, 0x1)\n+#define NGBE_PSRCTL_MCP\t MS(8, 0x1)\n+#define NGBE_PSRCTL_UCP\t MS(9, 0x1)\n+#define NGBE_PSRCTL_BCA\t MS(10, 0x1)\n+#define NGBE_PSRCTL_L4CSUM\t MS(12, 0x1)\n+#define NGBE_PSRCTL_PCSD\t MS(13, 0x1)\n+#define NGBE_PSRCTL_LBENA\t MS(18, 0x1)\n+#define NGBE_FRMSZ\t\t 0x015020\n+#define NGBE_FRMSZ_MAX_MASK\t MS(0, 0xFFFF)\n+#define NGBE_FRMSZ_MAX(v)\t LS(v, 0, 0xFFFF)\n+#define NGBE_VLANCTL\t\t 0x015088\n+#define NGBE_VLANCTL_TPID_MASK MS(0, 0xFFFF)\n+#define NGBE_VLANCTL_TPID(v)\t LS(v, 0, 0xFFFF)\n+#define NGBE_VLANCTL_CFI\t MS(28, 0x1)\n+#define NGBE_VLANCTL_CFIENA\t MS(29, 0x1)\n+#define NGBE_VLANCTL_VFE\t MS(30, 0x1)\n+#define NGBE_POOLCTL\t\t 0x0151B0\n+#define NGBE_POOLCTL_DEFDSA\t MS(29, 0x1)\n+#define NGBE_POOLCTL_RPLEN\t MS(30, 0x1)\n+#define NGBE_POOLCTL_MODE_MASK MS(16, 0x3)\n+#define NGBE_PSRPOOL_MODE_MAC LS(0, 16, 0x3)\n+#define NGBE_PSRPOOL_MODE_ETAG LS(1, 16, 0x3)\n+#define NGBE_POOLCTL_DEFPL(v) LS(v, 7, 0x7)\n+#define NGBE_POOLCTL_DEFPL_MASK MS(7, 0x7)\n+\n+#define NGBE_ETFLT(i) (0x015128 + (i) * 4) /*0-7*/\n+#define NGBE_ETFLT_ETID(v) LS(v, 0, 0xFFFF)\n+#define NGBE_ETFLT_ETID_MASK MS(0, 0xFFFF)\n+#define NGBE_ETFLT_POOL(v) LS(v, 20, 0x7)\n+#define NGBE_ETFLT_POOLENA MS(26, 0x1)\n+#define NGBE_ETFLT_TXAS MS(29, 0x1)\n+#define NGBE_ETFLT_1588 MS(30, 0x1)\n+#define NGBE_ETFLT_ENA MS(31, 0x1)\n+#define NGBE_ETCLS(i) (0x019100 + (i) * 4) /*0-7*/\n+#define NGBE_ETCLS_QPID(v) LS(v, 16, 0x7)\n+#define NGBD_ETCLS_QPID(r) RS(r, 16, 0x7)\n+#define NGBE_ETCLS_LLI MS(29, 0x1)\n+#define NGBE_ETCLS_QENA MS(31, 0x1)\n+#define NGBE_SYNCLS 0x019130\n+#define NGBE_SYNCLS_ENA MS(0, 0x1)\n+#define NGBE_SYNCLS_QPID(v) LS(v, 1, 0x7)\n+#define NGBD_SYNCLS_QPID(r) RS(r, 1, 0x7)\n+#define NGBE_SYNCLS_QPID_MASK MS(1, 0x7)\n+#define NGBE_SYNCLS_HIPRIO MS(31, 0x1)\n+\n+/* MAC & VLAN & NVE */\n+#define NGBE_PSRVLANIDX 0x016230 /*0-31*/\n+#define NGBE_PSRVLAN 0x016220\n+#define NGBE_PSRVLAN_VID(v) LS(v, 0, 0xFFF)\n+#define NGBE_PSRVLAN_EA MS(31, 0x1)\n+#define NGBE_PSRVLANPLM(i) (0x016224 + (i) * 4) /*0-1*/\n+\n+/**\n+ * Mirror Rules\n+ **/\n+#define NGBE_MIRRCTL(i)\t (0x015B00 + (i) * 4)\n+#define NGBE_MIRRCTL_POOL\t MS(0, 0x1)\n+#define NGBE_MIRRCTL_UPLINK\t MS(1, 0x1)\n+#define NGBE_MIRRCTL_DNLINK\t MS(2, 0x1)\n+#define NGBE_MIRRCTL_VLAN\t MS(3, 0x1)\n+#define NGBE_MIRRCTL_DESTP(v)\t LS(v, 8, 0x7)\n+#define NGBE_MIRRVLANL(i)\t (0x015B10 + (i) * 8)\n+#define NGBE_MIRRPOOLL(i)\t (0x015B30 + (i) * 8)\n+\n+/**\n+ * Time Stamp\n+ **/\n+#define NGBE_TSRXCTL\t\t0x015188\n+#define NGBE_TSRXCTL_VLD\tMS(0, 0x1)\n+#define NGBE_TSRXCTL_TYPE(v)\tLS(v, 1, 0x7)\n+#define NGBE_TSRXCTL_TYPE_V2L2\t(0)\n+#define NGBE_TSRXCTL_TYPE_V1L4\t(1)\n+#define NGBE_TSRXCTL_TYPE_V2L24\t(2)\n+#define NGBE_TSRXCTL_TYPE_V2EVENT\t(5)\n+#define NGBE_TSRXCTL_ENA\tMS(4, 0x1)\n+#define NGBE_TSRXSTMPL\t\t0x0151E8\n+#define NGBE_TSRXSTMPH\t\t0x0151A4\n+#define NGBE_TSTXCTL\t\t0x011F00\n+#define NGBE_TSTXCTL_VLD\tMS(0, 0x1)\n+#define NGBE_TSTXCTL_ENA\tMS(4, 0x1)\n+#define NGBE_TSTXSTMPL\t\t0x011F04\n+#define NGBE_TSTXSTMPH\t\t0x011F08\n+#define NGBE_TSTIMEL\t\t0x011F0C\n+#define NGBE_TSTIMEH\t\t0x011F10\n+#define NGBE_TSTIMEINC\t\t0x011F14\n+#define NGBE_TSTIMEINC_IV(v)\tLS(v, 0, 0x7FFFFFF)\n+\n+/**\n+ * Wake on Lan\n+ **/\n+#define NGBE_WOLCTL 0x015B80\n+#define NGBE_WOLIPCTL 0x015B84\n+#define NGBE_WOLIP4(i) (0x015BC0 + (i) * 4) /* 0-3 */\n+#define NGBE_WOLIP6(i) (0x015BE0 + (i) * 4) /* 0-3 */\n+\n+#define NGBE_WOLFLEXCTL 0x015CFC\n+#define NGBE_WOLFLEXI 0x015B8C\n+#define NGBE_WOLFLEXDAT(i) (0x015C00 + (i) * 16) /* 0-15 */\n+#define NGBE_WOLFLEXMSK(i) (0x015C08 + (i) * 16) /* 0-15 */\n+\n+/******************************************************************************\n+ * Security Registers\n+ ******************************************************************************/\n+#define NGBE_SECRXCTL\t\t\t0x017000\n+#define NGBE_SECRXCTL_ODSA\t\tMS(0, 0x1)\n+#define NGBE_SECRXCTL_XDSA\t\tMS(1, 0x1)\n+#define NGBE_SECRXCTL_CRCSTRIP\tMS(2, 0x1)\n+#define NGBE_SECRXCTL_SAVEBAD\t\tMS(6, 0x1)\n+#define NGBE_SECRXSTAT\t\t\t0x017004\n+#define NGBE_SECRXSTAT_RDY\t\tMS(0, 0x1)\n+#define NGBE_SECRXSTAT_ECC\t\tMS(1, 0x1)\n+\n+#define NGBE_SECTXCTL\t\t\t0x01D000\n+#define NGBE_SECTXCTL_ODSA\t\tMS(0, 0x1)\n+#define NGBE_SECTXCTL_XDSA\t\tMS(1, 0x1)\n+#define NGBE_SECTXCTL_STFWD\t\tMS(2, 0x1)\n+#define NGBE_SECTXCTL_MSKIV\t\tMS(3, 0x1)\n+#define NGBE_SECTXSTAT\t\t\t0x01D004\n+#define NGBE_SECTXSTAT_RDY\t\tMS(0, 0x1)\n+#define NGBE_SECTXSTAT_ECC\t\tMS(1, 0x1)\n+#define NGBE_SECTXBUFAF\t\t\t0x01D008\n+#define NGBE_SECTXBUFAE\t\t\t0x01D00C\n+#define NGBE_SECTXIFG\t\t\t0x01D020\n+#define NGBE_SECTXIFG_MIN(v)\t\tLS(v, 0, 0xF)\n+#define NGBE_SECTXIFG_MIN_MASK\tMS(0, 0xF)\n+\n+/**\n+ * LinkSec\n+ **/\n+#define NGBE_LSECRXCAP\t 0x017200\n+#define NGBE_LSECRXCTL 0x017204\n+\t/* disabled(0),check(1),strict(2),drop(3) */\n+#define NGBE_LSECRXCTL_MODE_MASK MS(2, 0x3)\n+#define NGBE_LSECRXCTL_MODE_STRICT LS(2, 2, 0x3)\n+#define NGBE_LSECRXCTL_POSTHDR MS(6, 0x1)\n+#define NGBE_LSECRXCTL_REPLAY MS(7, 0x1)\n+#define NGBE_LSECRXSCIL 0x017208\n+#define NGBE_LSECRXSCIH 0x01720C\n+#define NGBE_LSECRXSA(i) (0x017210 + (i) * 4) /* 0-1 */\n+#define NGBE_LSECRXPN(i) (0x017218 + (i) * 4) /* 0-1 */\n+#define NGBE_LSECRXKEY(n, i)\t (0x017220 + 0x10 * (n) + 4 * (i)) /*0-3*/\n+#define NGBE_LSECTXCAP 0x01D200\n+#define NGBE_LSECTXCTL 0x01D204\n+\t/* disabled(0), auth(1), auth+encrypt(2) */\n+#define NGBE_LSECTXCTL_MODE_MASK MS(0, 0x3)\n+#define NGBE_LSECTXCTL_MODE_AUTH LS(1, 0, 0x3)\n+#define NGBE_LSECTXCTL_MODE_AENC LS(2, 0, 0x3)\n+#define NGBE_LSECTXCTL_PNTRH_MASK MS(8, 0xFFFFFF)\n+#define NGBE_LSECTXCTL_PNTRH(v) LS(v, 8, 0xFFFFFF)\n+#define NGBE_LSECTXSCIL 0x01D208\n+#define NGBE_LSECTXSCIH 0x01D20C\n+#define NGBE_LSECTXSA 0x01D210\n+#define NGBE_LSECTXPN0 0x01D214\n+#define NGBE_LSECTXPN1 0x01D218\n+#define NGBE_LSECTXKEY0(i) (0x01D21C + (i) * 4) /* 0-3 */\n+#define NGBE_LSECTXKEY1(i) (0x01D22C + (i) * 4) /* 0-3 */\n+\n+#define NGBE_LSECRX_UTPKT 0x017240\n+#define NGBE_LSECRX_DECOCT 0x017244\n+#define NGBE_LSECRX_VLDOCT 0x017248\n+#define NGBE_LSECRX_BTPKT 0x01724C\n+#define NGBE_LSECRX_NOSCIPKT 0x017250\n+#define NGBE_LSECRX_UNSCIPKT 0x017254\n+#define NGBE_LSECRX_UNCHKPKT 0x017258\n+#define NGBE_LSECRX_DLYPKT 0x01725C\n+#define NGBE_LSECRX_LATEPKT 0x017260\n+#define NGBE_LSECRX_OKPKT(i) (0x017264 + (i) * 4) /* 0-1 */\n+#define NGBE_LSECRX_BADPKT(i) (0x01726C + (i) * 4) /* 0-1 */\n+#define NGBE_LSECRX_INVPKT(i) (0x017274 + (i) * 4) /* 0-1 */\n+#define NGBE_LSECRX_BADSAPKT(i) (0x01727C + (i) * 8) /* 0-3 */\n+#define NGBE_LSECRX_INVSAPKT(i) (0x017280 + (i) * 8) /* 0-3 */\n+#define NGBE_LSECTX_UTPKT 0x01D23C\n+#define NGBE_LSECTX_ENCPKT 0x01D240\n+#define NGBE_LSECTX_PROTPKT 0x01D244\n+#define NGBE_LSECTX_ENCOCT 0x01D248\n+#define NGBE_LSECTX_PROTOCT 0x01D24C\n+\n+/******************************************************************************\n+ * MAC Registers\n+ ******************************************************************************/\n+#define NGBE_MACRXCFG 0x011004\n+#define NGBE_MACRXCFG_ENA MS(0, 0x1)\n+#define NGBE_MACRXCFG_JUMBO MS(8, 0x1)\n+#define NGBE_MACRXCFG_LB MS(10, 0x1)\n+#define NGBE_MACCNTCTL 0x011800\n+#define NGBE_MACCNTCTL_RC MS(2, 0x1)\n+\n+#define NGBE_MACRXFLT 0x011008\n+#define NGBE_MACRXFLT_PROMISC MS(0, 0x1)\n+#define NGBE_MACRXFLT_CTL_MASK MS(6, 0x3)\n+#define NGBE_MACRXFLT_CTL_DROP LS(0, 6, 0x3)\n+#define NGBE_MACRXFLT_CTL_NOPS LS(1, 6, 0x3)\n+#define NGBE_MACRXFLT_CTL_NOFT LS(2, 6, 0x3)\n+#define NGBE_MACRXFLT_CTL_PASS LS(3, 6, 0x3)\n+#define NGBE_MACRXFLT_RXALL MS(31, 0x1)\n+\n+/******************************************************************************\n+ * Statistic Registers\n+ ******************************************************************************/\n+/* Ring Counter */\n+#define NGBE_QPRXPKT(rp) (0x001014 + 0x40 * (rp))\n+#define NGBE_QPRXOCTL(rp) (0x001018 + 0x40 * (rp))\n+#define NGBE_QPRXOCTH(rp) (0x00101C + 0x40 * (rp))\n+#define NGBE_QPRXMPKT(rp) (0x001020 + 0x40 * (rp))\n+#define NGBE_QPRXBPKT(rp) (0x001024 + 0x40 * (rp))\n+#define NGBE_QPTXPKT(rp) (0x003014 + 0x40 * (rp))\n+#define NGBE_QPTXOCTL(rp) (0x003018 + 0x40 * (rp))\n+#define NGBE_QPTXOCTH(rp) (0x00301C + 0x40 * (rp))\n+#define NGBE_QPTXMPKT(rp) (0x003020 + 0x40 * (rp))\n+#define NGBE_QPTXBPKT(rp) (0x003024 + 0x40 * (rp))\n+\n+/* TDMA Counter */\n+#define NGBE_DMATXDROP\t\t\t0x018300\n+#define NGBE_DMATXSECDROP\t\t0x018304\n+#define NGBE_DMATXPKT\t\t\t0x018308\n+#define NGBE_DMATXOCTL\t\t\t0x01830C\n+#define NGBE_DMATXOCTH\t\t\t0x018310\n+#define NGBE_DMATXMNG\t\t\t0x018314\n+\n+/* RDMA Counter */\n+#define NGBE_DMARXDROP\t\t\t0x012500\n+#define NGBE_DMARXPKT\t\t\t0x012504\n+#define NGBE_DMARXOCTL\t\t\t0x012508\n+#define NGBE_DMARXOCTH\t\t\t0x01250C\n+#define NGBE_DMARXMNG\t\t\t0x012510\n+\n+/* Packet Buffer Counter */\n+#define NGBE_PBRXMISS\t\t\t0x019040\n+#define NGBE_PBRXPKT\t\t\t0x019060\n+#define NGBE_PBRXREP\t\t\t0x019064\n+#define NGBE_PBRXDROP\t\t\t0x019068\n+#define NGBE_PBLBSTAT\t\t\t0x01906C\n+#define NGBE_PBLBSTAT_FREE(r)\t\tRS(r, 0, 0x3FF)\n+#define NGBE_PBLBSTAT_FULL\t\tMS(11, 0x1)\n+#define NGBE_PBRXWRPTR\t\t\t0x019180\n+#define NGBE_PBRXWRPTR_HEAD(r)\tRS(r, 0, 0xFFFF)\n+#define NGBE_PBRXWRPTR_TAIL(r)\tRS(r, 16, 0xFFFF)\n+#define NGBE_PBRXRDPTR\t\t\t0x0191A0\n+#define NGBE_PBRXRDPTR_HEAD(r)\tRS(r, 0, 0xFFFF)\n+#define NGBE_PBRXRDPTR_TAIL(r)\tRS(r, 16, 0xFFFF)\n+#define NGBE_PBRXDATA\t\t\t0x0191C0\n+#define NGBE_PBRXDATA_RDPTR(r)\tRS(r, 0, 0xFFFF)\n+#define NGBE_PBRXDATA_WRPTR(r)\tRS(r, 16, 0xFFFF)\n+#define NGBE_PBRX_USDSP\t\t\t0x0191E0\n+#define NGBE_RXPBPFCDMACL\t\t0x019210\n+#define NGBE_RXPBPFCDMACH\t\t0x019214\n+#define NGBE_PBTXLNKXOFF\t\t0x019218\n+#define NGBE_PBTXLNKXON\t\t\t0x01921C\n+\n+#define NGBE_PBTXSTAT\t\t\t0x01C004\n+#define NGBE_PBTXSTAT_EMPT(tc, r)\t((1 << (tc) & (r)) >> (tc))\n+\n+#define NGBE_PBRXLNKXOFF\t\t0x011988\n+#define NGBE_PBRXLNKXON\t\t\t0x011E0C\n+\n+#define NGBE_PBLPBK\t\t\t0x01CF08\n+\n+/* Ether Flow Counter */\n+#define NGBE_LANPKTDROP\t\t\t0x0151C0\n+#define NGBE_MNGPKTDROP\t\t\t0x0151C4\n+\n+#define NGBE_PSRLANPKTCNT\t\t0x0151B8\n+#define NGBE_PSRMNGPKTCNT\t\t0x0151BC\n+\n+/* MAC Counter */\n+#define NGBE_MACRXERRCRCL 0x011928\n+#define NGBE_MACRXERRCRCH 0x01192C\n+#define NGBE_MACRXERRLENL 0x011978\n+#define NGBE_MACRXERRLENH 0x01197C\n+#define NGBE_MACRX1TO64L 0x001940\n+#define NGBE_MACRX1TO64H 0x001944\n+#define NGBE_MACRX65TO127L 0x001948\n+#define NGBE_MACRX65TO127H 0x00194C\n+#define NGBE_MACRX128TO255L 0x001950\n+#define NGBE_MACRX128TO255H 0x001954\n+#define NGBE_MACRX256TO511L 0x001958\n+#define NGBE_MACRX256TO511H 0x00195C\n+#define NGBE_MACRX512TO1023L 0x001960\n+#define NGBE_MACRX512TO1023H 0x001964\n+#define NGBE_MACRX1024TOMAXL 0x001968\n+#define NGBE_MACRX1024TOMAXH 0x00196C\n+#define NGBE_MACTX1TO64L 0x001834\n+#define NGBE_MACTX1TO64H 0x001838\n+#define NGBE_MACTX65TO127L 0x00183C\n+#define NGBE_MACTX65TO127H 0x001840\n+#define NGBE_MACTX128TO255L 0x001844\n+#define NGBE_MACTX128TO255H 0x001848\n+#define NGBE_MACTX256TO511L 0x00184C\n+#define NGBE_MACTX256TO511H 0x001850\n+#define NGBE_MACTX512TO1023L 0x001854\n+#define NGBE_MACTX512TO1023H 0x001858\n+#define NGBE_MACTX1024TOMAXL 0x00185C\n+#define NGBE_MACTX1024TOMAXH 0x001860\n+\n+#define NGBE_MACRXUNDERSIZE 0x011938\n+#define NGBE_MACRXOVERSIZE 0x01193C\n+#define NGBE_MACRXJABBER 0x011934\n+\n+#define NGBE_MACRXPKTL 0x011900\n+#define NGBE_MACRXPKTH 0x011904\n+#define NGBE_MACTXPKTL 0x01181C\n+#define NGBE_MACTXPKTH 0x011820\n+#define NGBE_MACRXGBOCTL 0x011908\n+#define NGBE_MACRXGBOCTH 0x01190C\n+#define NGBE_MACTXGBOCTL 0x011814\n+#define NGBE_MACTXGBOCTH 0x011818\n+\n+#define NGBE_MACRXOCTL 0x011918\n+#define NGBE_MACRXOCTH 0x01191C\n+#define NGBE_MACRXMPKTL 0x011920\n+#define NGBE_MACRXMPKTH 0x011924\n+#define NGBE_MACTXOCTL 0x011824\n+#define NGBE_MACTXOCTH 0x011828\n+#define NGBE_MACTXMPKTL 0x01182C\n+#define NGBE_MACTXMPKTH 0x011830\n+\n+/* Management Counter */\n+#define NGBE_MNGOUT\t\t0x01CF00\n+#define NGBE_MNGIN\t\t0x01CF04\n+#define NGBE_MNGDROP\t\t0x01CF0C\n+\n+/* MAC SEC Counter */\n+#define NGBE_LSECRXUNTAG\t0x017240\n+#define NGBE_LSECRXDECOCT\t0x017244\n+#define NGBE_LSECRXVLDOCT\t0x017248\n+#define NGBE_LSECRXBADTAG\t0x01724C\n+#define NGBE_LSECRXNOSCI\t0x017250\n+#define NGBE_LSECRXUKSCI\t0x017254\n+#define NGBE_LSECRXUNCHK\t0x017258\n+#define NGBE_LSECRXDLY\t\t0x01725C\n+#define NGBE_LSECRXLATE\t\t0x017260\n+#define NGBE_LSECRXGOOD\t\t0x017264\n+#define NGBE_LSECRXBAD\t\t0x01726C\n+#define NGBE_LSECRXUK\t\t0x017274\n+#define NGBE_LSECRXBADSA\t0x01727C\n+#define NGBE_LSECRXUKSA\t\t0x017280\n+#define NGBE_LSECTXUNTAG\t0x01D23C\n+#define NGBE_LSECTXENC\t\t0x01D240\n+#define NGBE_LSECTXPTT\t\t0x01D244\n+#define NGBE_LSECTXENCOCT\t0x01D248\n+#define NGBE_LSECTXPTTOCT\t0x01D24C\n+\n+/* Management Counter */\n+#define NGBE_MNGOS2BMC 0x01E094\n+#define NGBE_MNGBMC2OS 0x01E090\n+\n+/******************************************************************************\n+ * PF(Physical Function) Registers\n+ ******************************************************************************/\n+/* Interrupt */\n+#define NGBE_ICRMISC\t\t0x000100\n+#define NGBE_ICRMISC_MASK\tMS(8, 0xFFFFFF)\n+#define NGBE_ICRMISC_RST\tMS(10, 0x1) /* device reset event */\n+#define NGBE_ICRMISC_TS\tMS(11, 0x1) /* time sync */\n+#define NGBE_ICRMISC_STALL\tMS(12, 0x1) /* trans or recv path is stalled */\n+#define NGBE_ICRMISC_LNKSEC\tMS(13, 0x1) /* Tx LinkSec require key exchange*/\n+#define NGBE_ICRMISC_ERRBUF\tMS(14, 0x1) /* Packet Buffer Overrun */\n+#define NGBE_ICRMISC_ERRMAC\tMS(17, 0x1) /* err reported by MAC */\n+#define NGBE_ICRMISC_PHY\tMS(18, 0x1) /* interrupt reported by eth phy */\n+#define NGBE_ICRMISC_ERRIG\tMS(20, 0x1) /* integrity error */\n+#define NGBE_ICRMISC_SPI\tMS(21, 0x1) /* SPI interface */\n+#define NGBE_ICRMISC_VFMBX\tMS(23, 0x1) /* VF-PF message box */\n+#define NGBE_ICRMISC_GPIO\tMS(26, 0x1) /* GPIO interrupt */\n+#define NGBE_ICRMISC_ERRPCI\tMS(27, 0x1) /* pcie request error */\n+#define NGBE_ICRMISC_HEAT\tMS(28, 0x1) /* overheat detection */\n+#define NGBE_ICRMISC_PROBE\tMS(29, 0x1) /* probe match */\n+#define NGBE_ICRMISC_MNGMBX\tMS(30, 0x1) /* mng mailbox */\n+#define NGBE_ICRMISC_TIMER\tMS(31, 0x1) /* tcp timer */\n+#define NGBE_ICRMISC_DEFAULT\t( \\\n+\t\t\tNGBE_ICRMISC_RST | \\\n+\t\t\tNGBE_ICRMISC_ERRMAC | \\\n+\t\t\tNGBE_ICRMISC_PHY | \\\n+\t\t\tNGBE_ICRMISC_ERRIG | \\\n+\t\t\tNGBE_ICRMISC_GPIO | \\\n+\t\t\tNGBE_ICRMISC_VFMBX | \\\n+\t\t\tNGBE_ICRMISC_MNGMBX | \\\n+\t\t\tNGBE_ICRMISC_STALL | \\\n+\t\t\tNGBE_ICRMISC_TIMER)\n+#define NGBE_ICSMISC\t\t\t0x000104\n+#define NGBE_IENMISC\t\t\t0x000108\n+#define NGBE_IVARMISC\t\t\t0x0004FC\n+#define NGBE_IVARMISC_VEC(v)\t\tLS(v, 0, 0x7)\n+#define NGBE_IVARMISC_VLD\t\tMS(7, 0x1)\n+#define NGBE_ICR(i)\t\t\t(0x000120 + (i) * 4) /*0*/\n+#define NGBE_ICR_MASK\t\t\tMS(0, 0x1FF)\n+#define NGBE_ICS(i)\t\t\t(0x000130 + (i) * 4) /*0*/\n+#define NGBE_ICS_MASK\t\t\tNGBE_ICR_MASK\n+#define NGBE_IMS(i)\t\t\t(0x000140 + (i) * 4) /*0*/\n+#define NGBE_IMS_MASK\t\t\tNGBE_ICR_MASK\n+#define NGBE_IMC(i)\t\t\t(0x000150 + (i) * 4) /*0*/\n+#define NGBE_IMC_MASK\t\t\tNGBE_ICR_MASK\n+#define NGBE_IVAR(i)\t\t\t(0x000500 + (i) * 4) /*0-3*/\n+#define NGBE_IVAR_VEC(v)\t\tLS(v, 0, 0x7)\n+#define NGBE_IVAR_VLD\t\t\tMS(7, 0x1)\n+#define NGBE_TCPTMR\t\t\t0x000170\n+#define NGBE_ITRSEL\t\t\t0x000180\n+\n+/* P2V Mailbox */\n+#define NGBE_MBMEM(i)\t\t(0x005000 + 0x40 * (i)) /*0-7*/\n+#define NGBE_MBCTL(i)\t\t(0x000600 + 4 * (i)) /*0-7*/\n+#define NGBE_MBCTL_STS\tMS(0, 0x1) /* Initiate message send to VF */\n+#define NGBE_MBCTL_ACK\tMS(1, 0x1) /* Ack message recv'd from VF */\n+#define NGBE_MBCTL_VFU\tMS(2, 0x1) /* VF owns the mailbox buffer */\n+#define NGBE_MBCTL_PFU\tMS(3, 0x1) /* PF owns the mailbox buffer */\n+#define NGBE_MBCTL_RVFU\tMS(4, 0x1) /* Reset VFU - used when VF stuck */\n+#define NGBE_MBVFICR\t\t\t0x000480\n+#define NGBE_MBVFICR_INDEX(vf)\t((vf) >> 4)\n+#define NGBE_MBVFICR_VFREQ_MASK\t(0x0000FFFF) /* bits for VF messages */\n+#define NGBE_MBVFICR_VFREQ_VF1\t(0x00000001) /* bit for VF 1 message */\n+#define NGBE_MBVFICR_VFACK_MASK\t(0xFFFF0000) /* bits for VF acks */\n+#define NGBE_MBVFICR_VFACK_VF1\t(0x00010000) /* bit for VF 1 ack */\n+#define NGBE_FLRVFP\t\t\t0x000490\n+#define NGBE_FLRVFE\t\t\t0x0004A0\n+#define NGBE_FLRVFEC\t\t\t0x0004A8\n+\n+/******************************************************************************\n+ * VF(Virtual Function) Registers\n+ ******************************************************************************/\n+#define NGBE_VFPBWRAP\t\t\t0x000000\n+#define NGBE_VFPBWRAP_WRAP\t\tMS(0, 0x7)\n+#define NGBE_VFPBWRAP_EMPT\t\tMS(3, 0x1)\n+#define NGBE_VFSTATUS\t\t\t0x000004\n+#define NGBE_VFSTATUS_UP\t\tMS(0, 0x1)\n+#define NGBE_VFSTATUS_BW_MASK\t\tMS(1, 0x7)\n+#define NGBE_VFSTATUS_BW_1G\t\tLS(0x1, 1, 0x7)\n+#define NGBE_VFSTATUS_BW_100M\tLS(0x2, 1, 0x7)\n+#define NGBE_VFSTATUS_BW_10M\tLS(0x4, 1, 0x7)\n+#define NGBE_VFSTATUS_BUSY\t\tMS(4, 0x1)\n+#define NGBE_VFSTATUS_LANID\t\tMS(8, 0x3)\n+#define NGBE_VFRST\t\t\t0x000008\n+#define NGBE_VFRST_SET\t\tMS(0, 0x1)\n+#define NGBE_VFMSIXECC\t\t\t0x00000C\n+#define NGBE_VFPLCFG\t\t\t0x000078\n+#define NGBE_VFPLCFG_RSV\t\tMS(0, 0x1)\n+#define NGBE_VFPLCFG_PSR(v)\t\tLS(v, 1, 0x1F)\n+#define NGBE_VFPLCFG_PSRL4HDR\t(0x1)\n+#define NGBE_VFPLCFG_PSRL3HDR\t(0x2)\n+#define NGBE_VFPLCFG_PSRL2HDR\t(0x4)\n+#define NGBE_VFPLCFG_PSRTUNHDR\t(0x8)\n+#define NGBE_VFPLCFG_PSRTUNMAC\t(0x10)\n+#define NGBE_VFICR\t\t\t0x000100\n+#define NGBE_VFICR_MASK\t\tLS(3, 0, 0x3)\n+#define NGBE_VFICR_MBX\t\tMS(1, 0x1)\n+#define NGBE_VFICR_DONE1\t\tMS(0, 0x1)\n+#define NGBE_VFICS\t\t\t0x000104\n+#define NGBE_VFICS_MASK\t\tNGBE_VFICR_MASK\n+#define NGBE_VFIMS\t\t\t0x000108\n+#define NGBE_VFIMS_MASK\t\tNGBE_VFICR_MASK\n+#define NGBE_VFIMC\t\t\t0x00010C\n+#define NGBE_VFIMC_MASK\t\tNGBE_VFICR_MASK\n+#define NGBE_VFGPIE\t\t\t0x000118\n+#define NGBE_VFIVAR(i)\t\t\t(0x000240 + 4 * (i)) /*0-1*/\n+#define NGBE_VFIVARMISC\t\t\t0x000260\n+#define NGBE_VFIVAR_ALLOC(v)\t\tLS(v, 0, 0x1)\n+#define NGBE_VFIVAR_VLD\t\tMS(7, 0x1)\n+\n+#define NGBE_VFMBCTL\t\t\t0x000600\n+#define NGBE_VFMBCTL_REQ MS(0, 0x1) /* Request for PF Ready bit */\n+#define NGBE_VFMBCTL_ACK MS(1, 0x1) /* Ack PF message received */\n+#define NGBE_VFMBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */\n+#define NGBE_VFMBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */\n+#define NGBE_VFMBCTL_PFSTS MS(4, 0x1) /* PF wrote a message in the MB */\n+#define NGBE_VFMBCTL_PFACK MS(5, 0x1) /* PF ack the previous VF msg */\n+#define NGBE_VFMBCTL_RSTI MS(6, 0x1) /* PF has reset indication */\n+#define NGBE_VFMBCTL_RSTD MS(7, 0x1) /* PF has indicated reset done */\n+#define NGBE_VFMBCTL_R2C_BITS\t\t(NGBE_VFMBCTL_RSTD | \\\n+\t\t\t\t\tNGBE_VFMBCTL_PFSTS | \\\n+\t\t\t\t\tNGBE_VFMBCTL_PFACK)\n+#define NGBE_VFMBX\t\t\t0x000C00 /*0-15*/\n+#define NGBE_VFTPHCTL(i)\t\t0x000D00\n+\n+/******************************************************************************\n+ * PF&VF TxRx Interface\n+ ******************************************************************************/\n+#define RNGLEN(v) ROUND_OVER(v, 13, 7)\n+#define HDRLEN(v) ROUND_OVER(v, 10, 6)\n+#define PKTLEN(v) ROUND_OVER(v, 14, 10)\n+#define INTTHR(v) ROUND_OVER(v, 4, 0)\n+\n+#define\tNGBE_RING_DESC_ALIGN\t128\n+#define\tNGBE_RING_DESC_MIN\t128\n+#define\tNGBE_RING_DESC_MAX\t8192\n+#define NGBE_RXD_ALIGN\t\tNGBE_RING_DESC_ALIGN\n+#define NGBE_TXD_ALIGN\t\tNGBE_RING_DESC_ALIGN\n+\n+/* receive ring */\n+#define NGBE_RXBAL(rp) (0x001000 + 0x40 * (rp))\n+#define NGBE_RXBAH(rp) (0x001004 + 0x40 * (rp))\n+#define NGBE_RXRP(rp) (0x00100C + 0x40 * (rp))\n+#define NGBE_RXWP(rp) (0x001008 + 0x40 * (rp))\n+#define NGBE_RXCFG(rp) (0x001010 + 0x40 * (rp))\n+#define NGBE_RXCFG_ENA MS(0, 0x1)\n+#define NGBE_RXCFG_RNGLEN(v) LS(RNGLEN(v), 1, 0x3F)\n+#define NGBE_RXCFG_PKTLEN(v) LS(PKTLEN(v), 8, 0xF)\n+#define NGBE_RXCFG_PKTLEN_MASK MS(8, 0xF)\n+#define NGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF)\n+#define NGBE_RXCFG_HDRLEN_MASK MS(12, 0xF)\n+#define NGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7)\n+#define NGBE_RXCFG_ETAG MS(22, 0x1)\n+#define NGBE_RXCFG_SPLIT MS(26, 0x1)\n+#define NGBE_RXCFG_CNTAG MS(28, 0x1)\n+#define NGBE_RXCFG_DROP MS(30, 0x1)\n+#define NGBE_RXCFG_VLAN MS(31, 0x1)\n+\n+/* transmit ring */\n+#define NGBE_TXBAL(rp) (0x003000 + 0x40 * (rp)) /*0-7*/\n+#define NGBE_TXBAH(rp) (0x003004 + 0x40 * (rp))\n+#define NGBE_TXWP(rp) (0x003008 + 0x40 * (rp))\n+#define NGBE_TXRP(rp) (0x00300C + 0x40 * (rp))\n+#define NGBE_TXCFG(rp) (0x003010 + 0x40 * (rp))\n+#define NGBE_TXCFG_ENA MS(0, 0x1)\n+#define NGBE_TXCFG_BUFLEN_MASK MS(1, 0x3F)\n+#define NGBE_TXCFG_BUFLEN(v) LS(RNGLEN(v), 1, 0x3F)\n+#define NGBE_TXCFG_HTHRESH_MASK MS(8, 0xF)\n+#define NGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF)\n+#define NGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F)\n+#define NGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F)\n+#define NGBE_TXCFG_FLUSH MS(26, 0x1)\n+\n+/* interrupt registers */\n+#define NGBE_BMEPEND\t\t\t0x000168\n+#define NGBE_BMEPEND_ST\t\tMS(0, 0x1)\n+#define NGBE_ITRI\t\t\t0x000180\n+#define NGBE_ITR(i)\t\t\t(0x000200 + 4 * (i))\n+#define NGBE_ITR_IVAL_MASK\t\tMS(2, 0x1FFF) /* 1ns/10G, 10ns/REST */\n+#define NGBE_ITR_IVAL(v)\t\tLS(v, 2, 0x1FFF) /*1ns/10G, 10ns/REST*/\n+#define NGBE_ITR_IVAL_1G(us)\tNGBE_ITR_IVAL((us) / 2)\n+#define NGBE_ITR_IVAL_10G(us)\tNGBE_ITR_IVAL((us) / 20)\n+#define NGBE_ITR_LLIEA\t\tMS(15, 0x1)\n+#define NGBE_ITR_LLICREDIT(v)\t\tLS(v, 16, 0x1F)\n+#define NGBE_ITR_CNT(v)\t\tLS(v, 21, 0x3FF)\n+#define NGBE_ITR_WRDSA\t\tMS(31, 0x1)\n+#define NGBE_GPIE\t\t\t0x000118\n+#define NGBE_GPIE_MSIX\t\tMS(0, 0x1)\n+#define NGBE_GPIE_LLIEA\t\tMS(1, 0x1)\n+#define NGBE_GPIE_LLIVAL(v)\t\tLS(v, 3, 0x1F)\n+#define NGBE_GPIE_LLIVAL_H(v)\t\tLS(v, 16, 0x7FF)\n+\n+/******************************************************************************\n+ * Debug Registers\n+ ******************************************************************************/\n+/**\n+ * Probe\n+ **/\n+#define NGBE_PRBCTL 0x010200\n+#define NGBE_PRBSTA 0x010204\n+#define NGBE_PRBDAT 0x010220\n+#define NGBE_PRBCNT 0x010228\n+\n+#define NGBE_PRBPCI 0x01F010\n+#define NGBE_PRBPSR 0x015010\n+#define NGBE_PRBRDB 0x019010\n+#define NGBE_PRBTDB 0x01C010\n+#define NGBE_PRBRSEC 0x017010\n+#define NGBE_PRBTSEC 0x01D010\n+#define NGBE_PRBMNG 0x01E010\n+#define NGBE_PRBRMAC 0x011014\n+#define NGBE_PRBTMAC 0x011010\n+#define NGBE_PRBREMAC 0x011E04\n+#define NGBE_PRBTEMAC 0x011E00\n+\n+/**\n+ * ECC\n+ **/\n+#define NGBE_ECCRXPBCTL 0x019014\n+#define NGBE_ECCRXPBINJ 0x019018\n+#define NGBE_ECCRXPB 0x01901C\n+#define NGBE_ECCTXPBCTL 0x01C014\n+#define NGBE_ECCTXPBINJ 0x01C018\n+#define NGBE_ECCTXPB 0x01C01C\n+\n+#define NGBE_ECCRXETHCTL 0x015014\n+#define NGBE_ECCRXETHINJ 0x015018\n+#define NGBE_ECCRXETH 0x01401C\n+\n+#define NGBE_ECCRXSECCTL 0x017014\n+#define NGBE_ECCRXSECINJ 0x017018\n+#define NGBE_ECCRXSEC 0x01701C\n+#define NGBE_ECCTXSECCTL 0x01D014\n+#define NGBE_ECCTXSECINJ 0x01D018\n+#define NGBE_ECCTXSEC 0x01D01C\n+\n+#define NGBE_P2VMBX_SIZE (16) /* 16*4B */\n+#define NGBE_P2MMBX_SIZE (64) /* 64*4B */\n+\n+/**************** Global Registers ****************************/\n+#define NGBE_POOLETHCTL(pl) (0x015600 + (pl) * 4)\n+#define NGBE_POOLETHCTL_LBDIA MS(0, 0x1)\n+#define NGBE_POOLETHCTL_LLBDIA MS(1, 0x1)\n+#define NGBE_POOLETHCTL_LLB MS(2, 0x1)\n+#define NGBE_POOLETHCTL_UCP MS(4, 0x1)\n+#define NGBE_POOLETHCTL_ETP MS(5, 0x1)\n+#define NGBE_POOLETHCTL_VLA MS(6, 0x1)\n+#define NGBE_POOLETHCTL_VLP MS(7, 0x1)\n+#define NGBE_POOLETHCTL_UTA MS(8, 0x1)\n+#define NGBE_POOLETHCTL_MCHA MS(9, 0x1)\n+#define NGBE_POOLETHCTL_UCHA MS(10, 0x1)\n+#define NGBE_POOLETHCTL_BCA MS(11, 0x1)\n+#define NGBE_POOLETHCTL_MCP MS(12, 0x1)\n+#define NGBE_POOLDROPSWBK(i) (0x0151C8 + (i) * 4) /*0-1*/\n+\n+/**************************** Receive DMA registers **************************/\n+\n+#define NGBE_RPUP2TC 0x019008\n+#define NGBE_RPUP2TC_UP_SHIFT 3\n+#define NGBE_RPUP2TC_UP_MASK 0x7\n+\n+/* mac switcher */\n+#define NGBE_ETHADDRL 0x016200\n+#define NGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF)\n+#define NGBE_ETHADDRL_AD1(v) LS(v, 8, 0xFF)\n+#define NGBE_ETHADDRL_AD2(v) LS(v, 16, 0xFF)\n+#define NGBE_ETHADDRL_AD3(v) LS(v, 24, 0xFF)\n+#define NGBE_ETHADDRL_ETAG(r) RS(r, 0, 0x3FFF)\n+#define NGBE_ETHADDRH 0x016204\n+#define NGBE_ETHADDRH_AD4(v) LS(v, 0, 0xFF)\n+#define NGBE_ETHADDRH_AD5(v) LS(v, 8, 0xFF)\n+#define NGBE_ETHADDRH_AD_MASK MS(0, 0xFFFF)\n+#define NGBE_ETHADDRH_ETAG MS(30, 0x1)\n+#define NGBE_ETHADDRH_VLD MS(31, 0x1)\n+#define NGBE_ETHADDRASS 0x016208\n+#define NGBE_ETHADDRIDX 0x016210\n+\n+/* Outmost Barrier Filters */\n+#define NGBE_MCADDRTBL(i) (0x015200 + (i) * 4) /*0-127*/\n+#define NGBE_UCADDRTBL(i) (0x015400 + (i) * 4) /*0-127*/\n+#define NGBE_VLANTBL(i) (0x016000 + (i) * 4) /*0-127*/\n+\n+#define NGBE_MNGFLEXSEL 0x1582C\n+#define NGBE_MNGFLEXDWL(i) (0x15A00 + ((i) * 16))\n+#define NGBE_MNGFLEXDWH(i) (0x15A04 + ((i) * 16))\n+#define NGBE_MNGFLEXMSK(i) (0x15A08 + ((i) * 16))\n+\n+#define NGBE_LANFLEXSEL 0x15B8C\n+#define NGBE_LANFLEXDWL(i) (0x15C00 + ((i) * 16))\n+#define NGBE_LANFLEXDWH(i) (0x15C04 + ((i) * 16))\n+#define NGBE_LANFLEXMSK(i) (0x15C08 + ((i) * 16))\n+#define NGBE_LANFLEXCTL 0x15CFC\n+\n+/* ipsec */\n+#define NGBE_IPSRXIDX 0x017100\n+#define NGBE_IPSRXIDX_ENA MS(0, 0x1)\n+#define NGBE_IPSRXIDX_TB_MASK MS(1, 0x3)\n+#define NGBE_IPSRXIDX_TB_IP LS(1, 1, 0x3)\n+#define NGBE_IPSRXIDX_TB_SPI LS(2, 1, 0x3)\n+#define NGBE_IPSRXIDX_TB_KEY LS(3, 1, 0x3)\n+#define NGBE_IPSRXIDX_TBIDX(v) LS(v, 3, 0xF)\n+#define NGBE_IPSRXIDX_READ MS(30, 0x1)\n+#define NGBE_IPSRXIDX_WRITE MS(31, 0x1)\n+#define NGBE_IPSRXADDR(i) (0x017104 + (i) * 4)\n+\n+#define NGBE_IPSRXSPI 0x017114\n+#define NGBE_IPSRXADDRIDX 0x017118\n+#define NGBE_IPSRXKEY(i) (0x01711C + (i) * 4)\n+#define NGBE_IPSRXSALT 0x01712C\n+#define NGBE_IPSRXMODE 0x017130\n+#define NGBE_IPSRXMODE_IPV6 0x00000010\n+#define NGBE_IPSRXMODE_DEC 0x00000008\n+#define NGBE_IPSRXMODE_ESP 0x00000004\n+#define NGBE_IPSRXMODE_AH 0x00000002\n+#define NGBE_IPSRXMODE_VLD 0x00000001\n+#define NGBE_IPSTXIDX 0x01D100\n+#define NGBE_IPSTXIDX_ENA MS(0, 0x1)\n+#define NGBE_IPSTXIDX_SAIDX(v) LS(v, 3, 0x3FF)\n+#define NGBE_IPSTXIDX_READ MS(30, 0x1)\n+#define NGBE_IPSTXIDX_WRITE MS(31, 0x1)\n+#define NGBE_IPSTXSALT 0x01D104\n+#define NGBE_IPSTXKEY(i) (0x01D108 + (i) * 4)\n+\n+#define NGBE_MACTXCFG 0x011000\n+#define NGBE_MACTXCFG_TE MS(0, 0x1)\n+#define NGBE_MACTXCFG_SPEED_MASK MS(29, 0x3)\n+#define NGBE_MACTXCFG_SPEED(v) LS(v, 29, 0x3)\n+#define NGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3)\n+#define NGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3)\n+\n+#define NGBE_ISBADDRL 0x000160\n+#define NGBE_ISBADDRH 0x000164\n+\n+#define NGBE_ARBPOOLIDX 0x01820C\n+#define NGBE_ARBTXRATE 0x018404\n+#define NGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF)\n+#define NGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF)\n+\n+/* qos */\n+#define NGBE_ARBTXCTL 0x018200\n+#define NGBE_ARBTXCTL_RRM MS(1, 0x1)\n+#define NGBE_ARBTXCTL_WSP MS(2, 0x1)\n+#define NGBE_ARBTXCTL_DIA MS(6, 0x1)\n+#define NGBE_ARBTXMMW 0x018208\n+\n+/* Management */\n+#define NGBE_MNGFWSYNC 0x01E000\n+#define NGBE_MNGFWSYNC_REQ MS(0, 0x1)\n+#define NGBE_MNGSWSYNC 0x01E004\n+#define NGBE_MNGSWSYNC_REQ MS(0, 0x1)\n+#define NGBE_SWSEM 0x01002C\n+#define NGBE_SWSEM_PF MS(0, 0x1)\n+#define NGBE_MNGSEM 0x01E008\n+#define NGBE_MNGSEM_SW(v) LS(v, 0, 0xFFFF)\n+#define NGBE_MNGSEM_SWPHY MS(0, 0x1)\n+#define NGBE_MNGSEM_SWMBX MS(2, 0x1)\n+#define NGBE_MNGSEM_SWFLASH MS(3, 0x1)\n+#define NGBE_MNGSEM_FW(v) LS(v, 16, 0xFFFF)\n+#define NGBE_MNGSEM_FWPHY MS(16, 0x1)\n+#define NGBE_MNGSEM_FWMBX MS(18, 0x1)\n+#define NGBE_MNGSEM_FWFLASH MS(19, 0x1)\n+#define NGBE_MNGMBXCTL 0x01E044\n+#define NGBE_MNGMBXCTL_SWRDY MS(0, 0x1)\n+#define NGBE_MNGMBXCTL_SWACK MS(1, 0x1)\n+#define NGBE_MNGMBXCTL_FWRDY MS(2, 0x1)\n+#define NGBE_MNGMBXCTL_FWACK MS(3, 0x1)\n+#define NGBE_MNGMBX 0x01E100\n+\n+/**\n+ * MDIO(PHY)\n+ **/\n+#define NGBE_MDIOSCA 0x011200\n+#define NGBE_MDIOSCA_REG(v) LS(v, 0, 0xFFFF)\n+#define NGBE_MDIOSCA_PORT(v) LS(v, 16, 0x1F)\n+#define NGBE_MDIOSCA_DEV(v) LS(v, 21, 0x1F)\n+#define NGBE_MDIOSCD 0x011204\n+#define NGBE_MDIOSCD_DAT_R(r) RS(r, 0, 0xFFFF)\n+#define NGBE_MDIOSCD_DAT(v) LS(v, 0, 0xFFFF)\n+#define NGBE_MDIOSCD_CMD_PREAD LS(2, 16, 0x3)\n+#define NGBE_MDIOSCD_CMD_WRITE LS(1, 16, 0x3)\n+#define NGBE_MDIOSCD_CMD_READ LS(3, 16, 0x3)\n+#define NGBE_MDIOSCD_SADDR MS(18, 0x1)\n+#define NGBE_MDIOSCD_CLOCK(v) LS(v, 19, 0x7)\n+#define NGBE_MDIOSCD_BUSY MS(22, 0x1)\n+\n+#define NGBE_MDIOMODE\t\t\t0x011220\n+#define NGBE_MDIOMODE_MASK\t\tMS(0, 0xF)\n+#define NGBE_MDIOMODE_PRT3CL22\tMS(3, 0x1)\n+#define NGBE_MDIOMODE_PRT2CL22\tMS(2, 0x1)\n+#define NGBE_MDIOMODE_PRT1CL22\tMS(1, 0x1)\n+#define NGBE_MDIOMODE_PRT0CL22\tMS(0, 0x1)\n+\n+#define NVM_OROM_OFFSET\t\t0x17\n+#define NVM_OROM_BLK_LOW\t0x83\n+#define NVM_OROM_BLK_HI\t\t0x84\n+#define NVM_OROM_PATCH_MASK\t0xFF\n+#define NVM_OROM_SHIFT\t\t8\n+#define NVM_VER_MASK\t\t0x00FF /* version mask */\n+#define NVM_VER_SHIFT\t\t8 /* version bit shift */\n+#define NVM_OEM_PROD_VER_PTR\t0x1B /* OEM Product version block pointer */\n+#define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */\n+#define NVM_OEM_PROD_VER_OFF_L\t0x2 /* OEM Product version offset low */\n+#define NVM_OEM_PROD_VER_OFF_H\t0x3 /* OEM Product version offset high */\n+#define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */\n+#define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */\n+#define NVM_ETK_OFF_LOW\t\t0x2D /* version low order word */\n+#define NVM_ETK_OFF_HI\t\t0x2E /* version high order word */\n+#define NVM_ETK_SHIFT\t\t16 /* high version word shift */\n+#define NVM_VER_INVALID\t\t0xFFFF\n+#define NVM_ETK_VALID\t\t0x8000\n+#define NVM_INVALID_PTR\t\t0xFFFF\n+#define NVM_VER_SIZE\t\t32 /* version string size */\n+\n+#define NGBE_REG_RSSTBL NGBE_RSSTBL(0)\n+#define NGBE_REG_RSSKEY NGBE_RSSKEY(0)\n+\n+/*\n+ * read non-rc counters\n+ */\n+#define NGBE_UPDCNT32(reg, last, cur) \\\n+do { \\\n+\tuint32_t latest = rd32(hw, reg); \\\n+\tif (hw->offset_loaded || hw->rx_loaded)\t\t\t \\\n+\t\tlast = 0;\t\t\t\t\t \\\n+\tcur += (latest - last) & UINT_MAX; \\\n+\tlast = latest; \\\n+} while (0)\n+\n+#define NGBE_UPDCNT36(regl, last, cur) \\\n+do { \\\n+\tuint64_t new_lsb = rd32(hw, regl); \\\n+\tuint64_t new_msb = rd32(hw, regl + 4); \\\n+\tuint64_t latest = ((new_msb << 32) | new_lsb); \\\n+\tif (hw->offset_loaded || hw->rx_loaded)\t\t\t \\\n+\t\tlast = 0;\t\t\t\t\t \\\n+\tcur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \\\n+\tlast = latest; \\\n+} while (0)\n+\n+/**\n+ * register operations\n+ **/\n+#define NGBE_REG_READ32(addr) rte_read32(addr)\n+#define NGBE_REG_READ32_RELAXED(addr) rte_read32_relaxed(addr)\n+#define NGBE_REG_WRITE32(addr, val) rte_write32(val, addr)\n+#define NGBE_REG_WRITE32_RELAXED(addr, val) rte_write32_relaxed(val, addr)\n+\n+#define NGBE_DEAD_READ_REG 0xdeadbeefU\n+#define NGBE_FAILED_READ_REG 0xffffffffU\n+#define NGBE_REG_ADDR(hw, reg) \\\n+\t((volatile u32 *)((char *)(hw)->hw_addr + (reg)))\n+\n+static inline u32\n+ngbe_get32(volatile u32 *addr)\n+{\n+\tu32 val = NGBE_REG_READ32(addr);\n+\treturn rte_le_to_cpu_32(val);\n+}\n+\n+static inline void\n+ngbe_set32(volatile u32 *addr, u32 val)\n+{\n+\tval = rte_cpu_to_le_32(val);\n+\tNGBE_REG_WRITE32(addr, val);\n+}\n+\n+static inline u32\n+ngbe_get32_masked(volatile u32 *addr, u32 mask)\n+{\n+\tu32 val = ngbe_get32(addr);\n+\tval &= mask;\n+\treturn val;\n+}\n+\n+static inline void\n+ngbe_set32_masked(volatile u32 *addr, u32 mask, u32 field)\n+{\n+\tu32 val = ngbe_get32(addr);\n+\tval = ((val & ~mask) | (field & mask));\n+\tngbe_set32(addr, val);\n+}\n+\n+static inline u32\n+ngbe_get32_relaxed(volatile u32 *addr)\n+{\n+\tu32 val = NGBE_REG_READ32_RELAXED(addr);\n+\treturn rte_le_to_cpu_32(val);\n+}\n+\n+static inline void\n+ngbe_set32_relaxed(volatile u32 *addr, u32 val)\n+{\n+\tval = rte_cpu_to_le_32(val);\n+\tNGBE_REG_WRITE32_RELAXED(addr, val);\n+}\n+\n+static inline u32\n+rd32(struct ngbe_hw *hw, u32 reg)\n+{\n+\tif (reg == NGBE_REG_DUMMY)\n+\t\treturn 0;\n+\treturn ngbe_get32(NGBE_REG_ADDR(hw, reg));\n+}\n+\n+static inline void\n+wr32(struct ngbe_hw *hw, u32 reg, u32 val)\n+{\n+\tif (reg == NGBE_REG_DUMMY)\n+\t\treturn;\n+\tngbe_set32(NGBE_REG_ADDR(hw, reg), val);\n+}\n+\n+static inline u32\n+rd32m(struct ngbe_hw *hw, u32 reg, u32 mask)\n+{\n+\tu32 val = rd32(hw, reg);\n+\tval &= mask;\n+\treturn val;\n+}\n+\n+static inline void\n+wr32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 field)\n+{\n+\tu32 val = rd32(hw, reg);\n+\tval = ((val & ~mask) | (field & mask));\n+\twr32(hw, reg, val);\n+}\n+\n+static inline u64\n+rd64(struct ngbe_hw *hw, u32 reg)\n+{\n+\tu64 lsb = rd32(hw, reg);\n+\tu64 msb = rd32(hw, reg + 4);\n+\treturn (lsb | msb << 32);\n+}\n+\n+static inline void\n+wr64(struct ngbe_hw *hw, u32 reg, u64 val)\n+{\n+\twr32(hw, reg, (u32)val);\n+\twr32(hw, reg + 4, (u32)(val >> 32));\n+}\n+\n+/* poll register */\n+static inline u32\n+po32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,\n+\tu32 loop, u32 slice)\n+{\n+\tbool usec = true;\n+\tu32 value = 0, all = 0;\n+\n+\tif (slice > 1000 * MAX_UDELAY_MS) {\n+\t\tusec = false;\n+\t\tslice = (slice + 500) / 1000;\n+\t}\n+\n+\tdo {\n+\t\tall |= rd32(hw, reg);\n+\t\tvalue |= mask & all;\n+\t\tif (value == expect)\n+\t\t\tbreak;\n+\n+\t\tusec ? usec_delay(slice) : msec_delay(slice);\n+\t} while (--loop > 0);\n+\n+\tif (actual)\n+\t\t*actual = all;\n+\n+\treturn loop;\n+}\n+\n+/* flush all write operations */\n+#define ngbe_flush(hw) rd32(hw, 0x00100C)\n+\n+#define rd32a(hw, reg, idx) ( \\\n+\trd32((hw), (reg) + ((idx) << 2)))\n+#define wr32a(hw, reg, idx, val) \\\n+\twr32((hw), (reg) + ((idx) << 2), (val))\n+\n+#define rd32w(hw, reg, mask, slice) do { \\\n+\trd32((hw), reg); \\\n+\tpo32m((hw), reg, mask, mask, NULL, 5, slice); \\\n+} while (0)\n+\n+#define wr32w(hw, reg, val, mask, slice) do { \\\n+\twr32((hw), reg, val); \\\n+\tpo32m((hw), reg, mask, mask, NULL, 5, slice); \\\n+} while (0)\n+\n+#define NGBE_XPCS_IDAADDR 0x13000\n+#define NGBE_XPCS_IDADATA 0x13004\n+#define NGBE_EPHY_IDAADDR 0x13008\n+#define NGBE_EPHY_IDADATA 0x1300C\n+static inline u32\n+rd32_epcs(struct ngbe_hw *hw, u32 addr)\n+{\n+\tu32 data;\n+\twr32(hw, NGBE_XPCS_IDAADDR, addr);\n+\tdata = rd32(hw, NGBE_XPCS_IDADATA);\n+\treturn data;\n+}\n+\n+static inline void\n+wr32_epcs(struct ngbe_hw *hw, u32 addr, u32 data)\n+{\n+\twr32(hw, NGBE_XPCS_IDAADDR, addr);\n+\twr32(hw, NGBE_XPCS_IDADATA, data);\n+}\n+\n+static inline u32\n+rd32_ephy(struct ngbe_hw *hw, u32 addr)\n+{\n+\tu32 data;\n+\twr32(hw, NGBE_EPHY_IDAADDR, addr);\n+\tdata = rd32(hw, NGBE_EPHY_IDADATA);\n+\treturn data;\n+}\n+\n+static inline void\n+wr32_ephy(struct ngbe_hw *hw, u32 addr, u32 data)\n+{\n+\twr32(hw, NGBE_EPHY_IDAADDR, addr);\n+\twr32(hw, NGBE_EPHY_IDADATA, data);\n+}\n+\n+#endif /* _NGBE_REGS_H_ */\n", "prefixes": [ "v6", "04/19" ] }