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GET /api/patches/94320/?format=api
{ "id": 94320, "url": "https://patches.dpdk.org/api/patches/94320/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210617101708.113951-2-ting.xu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210617101708.113951-2-ting.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210617101708.113951-2-ting.xu@intel.com", "date": "2021-06-17T10:17:04", "name": "[v2,1/5] common/iavf: support ETS-based QoS offload configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d05697676a121356cbf47dc40ca107bfaaa6e208", "submitter": { "id": 1363, "url": "https://patches.dpdk.org/api/people/1363/?format=api", "name": "Xu, Ting", "email": "ting.xu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210617101708.113951-2-ting.xu@intel.com/mbox/", "series": [ { "id": 17371, "url": "https://patches.dpdk.org/api/series/17371/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17371", "date": "2021-06-17T10:17:03", "name": "Enable ETS-based Tx QoS for VF in DCF", "version": 2, "mbox": "https://patches.dpdk.org/series/17371/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94320/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94320/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 41AAAA0C4D;\n\tThu, 17 Jun 2021 12:18:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7FCF6410DF;\n\tThu, 17 Jun 2021 12:18:38 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 3186540150\n for <dev@dpdk.org>; Thu, 17 Jun 2021 12:18:36 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Jun 2021 03:18:33 -0700", "from dpdk-xuting-main.sh.intel.com ([10.67.117.76])\n by fmsmga002.fm.intel.com with ESMTP; 17 Jun 2021 03:18:30 -0700" ], "IronPort-SDR": [ "\n kj71VdmmZOvLoBtPLNKzeuDgcV8ZJJhgBRcY9gi6/Yvx2dvd2pFny+Sx4u+ooI7sHaf/g/h+2I\n 4+ivyA2muN5A==", "\n q/7BbBSHJhoWP3UZ/JxI29KKWx2sfkdwl2VoJLOdgI+rW+qnDcm4lx86KEoZFhmO4+iZhEfJif\n 0iziHWsG/K5A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10017\"; a=\"206297207\"", "E=Sophos;i=\"5.83,280,1616482800\"; d=\"scan'208\";a=\"206297207\"", "E=Sophos;i=\"5.83,280,1616482800\"; d=\"scan'208\";a=\"488603096\"" ], "X-ExtLoop1": "1", "From": "Ting Xu <ting.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com,\n qiming.yang@intel.com", "Date": "Thu, 17 Jun 2021 18:17:04 +0800", "Message-Id": "<20210617101708.113951-2-ting.xu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210617101708.113951-1-ting.xu@intel.com>", "References": "<20210601014034.36100-1-ting.xu@intel.com>\n <20210617101708.113951-1-ting.xu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 1/5] common/iavf: support ETS-based QoS\n offload configuration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds new virtchnl opcodes and structures for QoS\nconfiguration, which includes:\n1. VIRTCHNL_VF_OFFLOAD_TC, to negotiate the capability supporting QoS\nconfiguration. If VF and PF both have this flag, then the ETS-based QoS\noffload function is supported.\n2. VIRTCHNL_OP_DCF_CONFIG_BW, DCF is supposed to configure min and max\nbandwidth for each VF per enabled TCs. To make the VSI node bandwidth\nconfiguration work, DCF also needs to configure TC node bandwidth\ndirectly.\n3. VIRTCHNL_OP_GET_QOS_CAPS, VF queries current QoS configuration, such\nas enabled TCs, arbiter type, up2tc and bandwidth of VSI node. The\nconfiguration is previously set by DCB and DCF, and now is the potential\nQoS capability of VF. VF can take it as reference to configure queue TC\nmapping.\n4. VIRTCHNL_OP_CONFIG_TC_MAP, set VF queues to TC mapping for all Tx and\nRx queues. Queues mapping to one TC should be continuous and all\nallocated queues should be mapped.\n\nSigned-off-by: Ting Xu <ting.xu@intel.com>\n---\n drivers/common/iavf/iavf_type.h | 2 +\n drivers/common/iavf/virtchnl.h | 125 ++++++++++++++++++++++++++++++++\n 2 files changed, 127 insertions(+)", "diff": "diff --git a/drivers/common/iavf/iavf_type.h b/drivers/common/iavf/iavf_type.h\nindex f3815d523b..73dfb47e70 100644\n--- a/drivers/common/iavf/iavf_type.h\n+++ b/drivers/common/iavf/iavf_type.h\n@@ -141,6 +141,8 @@ enum iavf_debug_mask {\n #define IAVF_PHY_LED_MODE_MASK\t\t\t0xFFFF\n #define IAVF_PHY_LED_MODE_ORIG\t\t\t0x80000000\n \n+#define IAVF_MAX_TRAFFIC_CLASS\t8\n+\n /* Memory types */\n enum iavf_memset_type {\n \tIAVF_NONDMA_MEM = 0,\ndiff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h\nindex 3a60faff93..a56f8b4589 100644\n--- a/drivers/common/iavf/virtchnl.h\n+++ b/drivers/common/iavf/virtchnl.h\n@@ -85,6 +85,10 @@ enum virtchnl_rx_hsplit {\n \tVIRTCHNL_RX_HSPLIT_SPLIT_SCTP = 8,\n };\n \n+enum virtchnl_bw_limit_type {\n+\tVIRTCHNL_BW_SHAPER = 0,\n+};\n+\n #define VIRTCHNL_ETH_LENGTH_OF_ADDRESS\t6\n /* END GENERIC DEFINES */\n \n@@ -130,6 +134,7 @@ enum virtchnl_ops {\n \tVIRTCHNL_OP_ADD_CLOUD_FILTER = 32,\n \tVIRTCHNL_OP_DEL_CLOUD_FILTER = 33,\n \t/* opcodes 34, 35, 36, and 37 are reserved */\n+\tVIRTCHNL_OP_DCF_CONFIG_BW = 37,\n \tVIRTCHNL_OP_DCF_VLAN_OFFLOAD = 38,\n \tVIRTCHNL_OP_DCF_CMD_DESC = 39,\n \tVIRTCHNL_OP_DCF_CMD_BUFF = 40,\n@@ -152,6 +157,8 @@ enum virtchnl_ops {\n \tVIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2 = 57,\n \tVIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2 = 58,\n \tVIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2 = 59,\n+\tVIRTCHNL_OP_GET_QOS_CAPS = 66,\n+\tVIRTCHNL_OP_CONFIG_TC_MAP = 67,\n \tVIRTCHNL_OP_ENABLE_QUEUES_V2 = 107,\n \tVIRTCHNL_OP_DISABLE_QUEUES_V2 = 108,\n \tVIRTCHNL_OP_MAP_QUEUE_VECTOR = 111,\n@@ -398,6 +405,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource);\n #define VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC\tBIT(26)\n #define VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF\t\tBIT(27)\n #define VIRTCHNL_VF_OFFLOAD_FDIR_PF\t\tBIT(28)\n+#define VIRTCHNL_VF_OFFLOAD_TC\t\tBIT(29)\n #define VIRTCHNL_VF_CAP_DCF\t\t\tBIT(30)\n \t/* BIT(31) is reserved */\n \n@@ -1285,6 +1293,13 @@ struct virtchnl_filter {\n \n VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter);\n \n+struct virtchnl_shaper_bw {\n+\tu32 committed;\n+\tu32 peak;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_shaper_bw);\n+\n /* VIRTCHNL_OP_DCF_GET_VSI_MAP\n * VF sends this message to get VSI mapping table.\n * PF responds with an indirect message containing VF's\n@@ -1357,6 +1372,32 @@ struct virtchnl_dcf_vlan_offload {\n \n VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_dcf_vlan_offload);\n \n+/* VIRTCHNL_OP_DCF_CONFIG_BW\n+ * VF send this message to set the bandwidth configuration of each\n+ * TC with a specific vf id. If vf id is 0xffff, it is used to configure\n+ * TC node bandwidth directly.\n+ */\n+struct virtchnl_dcf_bw_cfg {\n+\tu8 tc_id;\n+\tu8 pad[3];\n+\tenum virtchnl_bw_limit_type type;\n+\tunion {\n+\t\tstruct virtchnl_shaper_bw shaper;\n+\t\tu8 pad2[32];\n+\t};\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_dcf_bw_cfg);\n+\n+struct virtchnl_dcf_bw_cfg_list {\n+#define VIRTCHNL_DCF_TC_LEVEL 0xffff\n+\tu16 vf_id;\n+\tu16 num_elem;\n+\tstruct virtchnl_dcf_bw_cfg cfg[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(44, virtchnl_dcf_bw_cfg_list);\n+\n struct virtchnl_supported_rxdids {\n \t/* see enum virtchnl_rx_desc_id_bitmasks */\n \tu64 supported_rxdids;\n@@ -1767,6 +1808,62 @@ struct virtchnl_fdir_del {\n \n VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_fdir_del);\n \n+/* VIRTCHNL_OP_GET_QOS_CAPS\n+ * VF sends this message to get its QoS Caps, such as\n+ * TC number, Arbiter and Bandwidth.\n+ */\n+struct virtchnl_qos_cap_elem {\n+\tu8 tc_id;\n+\tu8 prio_of_tc;\n+#define VIRTCHNL_ABITER_STRICT 0\n+#define VIRTCHNL_ABITER_ETS 2\n+\tu8 arbiter;\n+#define VIRTCHNL_STRICT_WEIGHT 1\n+\tu8 weight;\n+\tenum virtchnl_bw_limit_type type;\n+\tunion {\n+\t\tstruct virtchnl_shaper_bw shaper;\n+\t\tu8 pad2[32];\n+\t};\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_qos_cap_elem);\n+\n+struct virtchnl_qos_cap_list {\n+\tu16 vsi_id;\n+\tu16 num_elem;\n+\tstruct virtchnl_qos_cap_elem cap[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(44, virtchnl_qos_cap_list);\n+\n+/* VIRTCHNL_OP_CONFIG_TC_MAP\n+ * VF sends message virtchnl_queue_tc_mapping to set queue to tc\n+ * mapping for all the Tx and Rx queues with a specified VSI, and\n+ * would get response about bitmap of valid user priorities\n+ * associated with queues.\n+ */\n+struct virtchnl_queue_tc_mapping {\n+\tu16 vsi_id;\n+\tu16 num_tc;\n+\tu16 num_queue_pairs;\n+\tu8 pad[2];\n+\tunion {\n+\t\tstruct {\n+\t\t\tu16 start_queue_id;\n+\t\t\tu16 queue_count;\n+\t\t} req;\n+\t\tstruct {\n+#define VIRTCHNL_USER_PRIO_TYPE_UP\t0\n+#define VIRTCHNL_USER_PRIO_TYPE_DSCP\t1\n+\t\t\tu16 prio_type;\n+\t\t\tu16 valid_prio_bitmap;\n+\t\t} resp;\n+\t} tc[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_tc_mapping);\n+\n /* VIRTCHNL_OP_QUERY_FDIR_FILTER\n * VF sends this request to PF by filling out vsi_id,\n * flow_id and reset_counter. PF will return query_info\n@@ -2117,6 +2214,19 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,\n \tcase VIRTCHNL_OP_DCF_GET_VSI_MAP:\n \tcase VIRTCHNL_OP_DCF_GET_PKG_INFO:\n \t\tbreak;\n+\tcase VIRTCHNL_OP_DCF_CONFIG_BW:\n+\t\tvalid_len = sizeof(struct virtchnl_dcf_bw_cfg_list);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_dcf_bw_cfg_list *cfg_list =\n+\t\t\t\t(struct virtchnl_dcf_bw_cfg_list *)msg;\n+\t\t\tif (cfg_list->num_elem == 0) {\n+\t\t\t\terr_msg_format = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tvalid_len += (cfg_list->num_elem - 1) *\n+\t\t\t\t\t sizeof(struct virtchnl_dcf_bw_cfg);\n+\t\t}\n+\t\tbreak;\n \tcase VIRTCHNL_OP_GET_SUPPORTED_RXDIDS:\n \t\tbreak;\n \tcase VIRTCHNL_OP_ADD_RSS_CFG:\n@@ -2132,6 +2242,21 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,\n \tcase VIRTCHNL_OP_QUERY_FDIR_FILTER:\n \t\tvalid_len = sizeof(struct virtchnl_fdir_query);\n \t\tbreak;\n+\tcase VIRTCHNL_OP_GET_QOS_CAPS:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_TC_MAP:\n+\t\tvalid_len = sizeof(struct virtchnl_queue_tc_mapping);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_queue_tc_mapping *q_tc =\n+\t\t\t\t(struct virtchnl_queue_tc_mapping *)msg;\n+\t\t\tif (q_tc->num_tc == 0) {\n+\t\t\t\terr_msg_format = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tvalid_len += (q_tc->num_tc - 1) *\n+\t\t\t\t\t sizeof(q_tc->tc[0]);\n+\t\t}\n+\t\tbreak;\n \tcase VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS:\n \t\tbreak;\n \tcase VIRTCHNL_OP_ADD_VLAN_V2:\n", "prefixes": [ "v2", "1/5" ] }