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GET /api/patches/94299/?format=api
{ "id": 94299, "url": "https://patches.dpdk.org/api/patches/94299/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210616144602.2803271-1-akozyrev@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210616144602.2803271-1-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210616144602.2803271-1-akozyrev@nvidia.com", "date": "2021-06-16T14:46:02", "name": "net/mlx5: convert meta register to big-endian", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "08aab0b757084be77aa3ff3d09e6ed8ff0fab55e", "submitter": { "id": 1873, "url": "https://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210616144602.2803271-1-akozyrev@nvidia.com/mbox/", "series": [ { "id": 17358, "url": "https://patches.dpdk.org/api/series/17358/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17358", "date": "2021-06-16T14:46:02", "name": "net/mlx5: convert meta register to big-endian", "version": 1, "mbox": "https://patches.dpdk.org/series/17358/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94299/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/94299/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(39860400002)(136003)(346002)(376002)(36840700001)(46966006)(82740400003)(478600001)(426003)(36906005)(54906003)(336012)(6916009)(70586007)(8676002)(316002)(16526019)(2906002)(186003)(70206006)(55016002)(26005)(8936002)(356005)(2616005)(7636003)(36860700001)(5660300002)(6666004)(1076003)(36756003)(82310400003)(107886003)(83380400001)(6286002)(86362001)(47076005)(7696005)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Jun 2021 14:46:17.1973 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4d52d186-292d-4121-80eb-08d930d57f79", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT039.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR12MB2737", "Subject": "[dpdk-dev] [PATCH] net/mlx5: convert meta register to big-endian", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Metadata is stored in the CPU order (little-endian format on x86),\nwhile all the packet header fields are stored in the network order.\nThat leads to the wrong results whenever we try to use the metadata\nvalue in the modify_field actions: bytes are swapped as a result.\n\nConvert the metadata into the big-endian format before storing it\nin the Mellanox NIC to achieve consistent behaviour.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 40 +++++-------------------\n drivers/net/mlx5/mlx5_rx.c | 5 +--\n drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 22 +++++++++----\n drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 30 +++++++++++-------\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 18 ++++++++---\n 5 files changed, 59 insertions(+), 56 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex dafd37ab93..b36ffde559 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1239,8 +1239,8 @@ flow_dv_convert_action_set_meta\n \t\t\t const struct rte_flow_action_set_meta *conf,\n \t\t\t struct rte_flow_error *error)\n {\n-\tuint32_t data = conf->data;\n-\tuint32_t mask = conf->mask;\n+\tuint32_t mask = rte_cpu_to_be_32(conf->mask);\n+\tuint32_t data = rte_cpu_to_be_32(conf->data) & mask;\n \tstruct rte_flow_item item = {\n \t\t.spec = &data,\n \t\t.mask = &mask,\n@@ -1253,25 +1253,14 @@ flow_dv_convert_action_set_meta\n \tif (reg < 0)\n \t\treturn reg;\n \tMLX5_ASSERT(reg != REG_NON);\n-\t/*\n-\t * In datapath code there is no endianness\n-\t * coversions for perfromance reasons, all\n-\t * pattern conversions are done in rte_flow.\n-\t */\n \tif (reg == REG_C_0) {\n \t\tstruct mlx5_priv *priv = dev->data->dev_private;\n \t\tuint32_t msk_c0 = priv->sh->dv_regc0_mask;\n-\t\tuint32_t shl_c0;\n+\t\tuint32_t shl_c0 = rte_bsf32(msk_c0);\n \n-\t\tMLX5_ASSERT(msk_c0);\n-#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n-\t\tshl_c0 = rte_bsf32(msk_c0);\n-#else\n-\t\tshl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);\n-#endif\n-\t\tmask <<= shl_c0;\n-\t\tdata <<= shl_c0;\n-\t\tMLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));\n+\t\tdata = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);\n+\t\tmask = rte_cpu_to_be_32(mask) & msk_c0;\n+\t\tmask = rte_cpu_to_be_32(mask << shl_c0);\n \t}\n \treg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};\n \t/* The routine expects parameters in memory as big-endian ones. */\n@@ -9226,27 +9215,14 @@ flow_dv_translate_item_meta(struct rte_eth_dev *dev,\n \t\tif (reg < 0)\n \t\t\treturn;\n \t\tMLX5_ASSERT(reg != REG_NON);\n-\t\t/*\n-\t\t * In datapath code there is no endianness\n-\t\t * coversions for perfromance reasons, all\n-\t\t * pattern conversions are done in rte_flow.\n-\t\t */\n-\t\tvalue = rte_cpu_to_be_32(value);\n-\t\tmask = rte_cpu_to_be_32(mask);\n \t\tif (reg == REG_C_0) {\n \t\t\tstruct mlx5_priv *priv = dev->data->dev_private;\n \t\t\tuint32_t msk_c0 = priv->sh->dv_regc0_mask;\n \t\t\tuint32_t shl_c0 = rte_bsf32(msk_c0);\n-#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n-\t\t\tuint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);\n \n-\t\t\tvalue >>= shr_c0;\n-\t\t\tmask >>= shr_c0;\n-#endif\n-\t\t\tvalue <<= shl_c0;\n+\t\t\tmask &= msk_c0;\n \t\t\tmask <<= shl_c0;\n-\t\t\tMLX5_ASSERT(msk_c0);\n-\t\t\tMLX5_ASSERT(!(~msk_c0 & mask));\n+\t\t\tvalue <<= shl_c0;\n \t\t}\n \t\tflow_dv_match_meta_reg(matcher, key, reg, value, mask);\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 6cd71a44eb..777a1d6e45 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -740,8 +740,9 @@ rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,\n \t\t}\n \t}\n \tif (rxq->dynf_meta) {\n-\t\tuint32_t meta = cqe->flow_table_metadata &\n-\t\t\t\trxq->flow_meta_port_mask;\n+\t\tuint32_t meta = rte_be_to_cpu_32(cqe->flow_table_metadata >>\n+\t\t\t__builtin_popcount(rxq->flow_meta_port_mask)) &\n+\t\t\trxq->flow_meta_port_mask;\n \n \t\tif (meta) {\n \t\t\tpkt->ol_flags |= rxq->flow_meta_mask;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\nindex 2d1154b624..648c59e2c2 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n@@ -1221,23 +1221,33 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\tif (rxq->dynf_meta) {\n \t\t\tuint64_t flag = rxq->flow_meta_mask;\n \t\t\tint32_t offs = rxq->flow_meta_offset;\n-\t\t\tuint32_t metadata, mask;\n+\t\t\tuint32_t mask = rxq->flow_meta_port_mask;\n+\t\t\tuint32_t shift =\n+\t\t\t\t__builtin_popcount(rxq->flow_meta_port_mask);\n+\t\t\tuint32_t metadata;\n \n-\t\t\tmask = rxq->flow_meta_port_mask;\n \t\t\t/* This code is subject for futher optimization. */\n-\t\t\tmetadata = cq[pos].flow_table_metadata & mask;\n+\t\t\tmetadata = (rte_be_to_cpu_32\n+\t\t\t\t(cq[pos].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =\n \t\t\t\t\t\t\t\tmetadata;\n \t\t\tpkts[pos]->ol_flags |= metadata ? flag : 0ULL;\n-\t\t\tmetadata = cq[pos + 1].flow_table_metadata & mask;\n+\t\t\tmetadata = (rte_be_to_cpu_32\n+\t\t\t\t(cq[pos + 1].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) =\n \t\t\t\t\t\t\t\tmetadata;\n \t\t\tpkts[pos + 1]->ol_flags |= metadata ? flag : 0ULL;\n-\t\t\tmetadata = cq[pos + 2].flow_table_metadata & mask;\n+\t\t\tmetadata = (rte_be_to_cpu_32\n+\t\t\t\t(cq[pos + 2].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) =\n \t\t\t\t\t\t\t\tmetadata;\n \t\t\tpkts[pos + 2]->ol_flags |= metadata ? flag : 0ULL;\n-\t\t\tmetadata = cq[pos + 3].flow_table_metadata & mask;\n+\t\t\tmetadata = (rte_be_to_cpu_32\n+\t\t\t\t(cq[pos + 3].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) =\n \t\t\t\t\t\t\t\tmetadata;\n \t\t\tpkts[pos + 3]->ol_flags |= metadata ? flag : 0ULL;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\nindex 2234fbe6b2..5c569ee199 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n@@ -833,23 +833,29 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t\t/* This code is subject for futher optimization. */\n \t\t\tint32_t offs = rxq->flow_meta_offset;\n \t\t\tuint32_t mask = rxq->flow_meta_port_mask;\n+\t\t\tuint32_t shift =\n+\t\t\t\t__builtin_popcount(rxq->flow_meta_port_mask);\n \n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =\n-\t\t\t\tcontainer_of(p0, struct mlx5_cqe,\n-\t\t\t\t\t pkt_info)->flow_table_metadata &\n-\t\t\t\t\t mask;\n+\t\t\t\t(rte_be_to_cpu_32(container_of\n+\t\t\t\t(p0, struct mlx5_cqe,\n+\t\t\t\tpkt_info)->flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) =\n-\t\t\t\tcontainer_of(p1, struct mlx5_cqe,\n-\t\t\t\t\t pkt_info)->flow_table_metadata &\n-\t\t\t\t\t mask;\n+\t\t\t\t(rte_be_to_cpu_32(container_of\n+\t\t\t\t(p1, struct mlx5_cqe,\n+\t\t\t\tpkt_info)->flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) =\n-\t\t\t\tcontainer_of(p2, struct mlx5_cqe,\n-\t\t\t\t\t pkt_info)->flow_table_metadata &\n-\t\t\t\t\t mask;\n+\t\t\t\t(rte_be_to_cpu_32(container_of\n+\t\t\t\t(p2, struct mlx5_cqe,\n+\t\t\t\tpkt_info)->flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) =\n-\t\t\t\tcontainer_of(p3, struct mlx5_cqe,\n-\t\t\t\t\t pkt_info)->flow_table_metadata &\n-\t\t\t\t\t mask;\n+\t\t\t\t(rte_be_to_cpu_32(container_of\n+\t\t\t\t(p3, struct mlx5_cqe,\n+\t\t\t\tpkt_info)->flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\tif (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *))\n \t\t\t\telts[pos]->ol_flags |= rxq->flow_meta_mask;\n \t\t\tif (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *))\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex c508a7a4f2..661fa7273c 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -769,15 +769,25 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t\t/* This code is subject for futher optimization. */\n \t\t\tint32_t offs = rxq->flow_meta_offset;\n \t\t\tuint32_t mask = rxq->flow_meta_port_mask;\n+\t\t\tuint32_t shift =\n+\t\t\t\t__builtin_popcount(rxq->flow_meta_port_mask);\n \n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =\n-\t\t\t\tcq[pos].flow_table_metadata & mask;\n+\t\t\t\t(rte_be_to_cpu_32\n+\t\t\t\t(cq[pos].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) =\n-\t\t\t\tcq[pos + p1].flow_table_metadata & mask;\n+\t\t\t\t(rte_be_to_cpu_32\n+\t\t\t\t(cq[pos + p1].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) =\n-\t\t\t\tcq[pos + p2].flow_table_metadata & mask;\n+\t\t\t\t(rte_be_to_cpu_32\n+\t\t\t\t(cq[pos + p2].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\t*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) =\n-\t\t\t\tcq[pos + p3].flow_table_metadata & mask;\n+\t\t\t\t(rte_be_to_cpu_32\n+\t\t\t\t(cq[pos + p3].flow_table_metadata) >> shift) &\n+\t\t\t\tmask;\n \t\t\tif (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *))\n \t\t\t\tpkts[pos]->ol_flags |= rxq->flow_meta_mask;\n \t\t\tif (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *))\n", "prefixes": [] }