Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/94298/?format=api
{ "id": 94298, "url": "https://patches.dpdk.org/api/patches/94298/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210616144236.2802978-1-akozyrev@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210616144236.2802978-1-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210616144236.2802978-1-akozyrev@nvidia.com", "date": "2021-06-16T14:42:36", "name": "net/mlx5: fix modify field action order for MAC", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8f4e469d32ced249f593304d10095fb71b10b1c3", "submitter": { "id": 1873, "url": "https://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210616144236.2802978-1-akozyrev@nvidia.com/mbox/", "series": [ { "id": 17357, "url": "https://patches.dpdk.org/api/series/17357/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17357", "date": "2021-06-16T14:42:36", "name": "net/mlx5: fix modify field action order for MAC", "version": 1, "mbox": "https://patches.dpdk.org/series/17357/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94298/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/94298/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7CD3EA0C42;\n\tWed, 16 Jun 2021 16:42:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 071C64067A;\n\tWed, 16 Jun 2021 16:42:56 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2071.outbound.protection.outlook.com [40.107.223.71])\n by mails.dpdk.org (Postfix) with ESMTP id 59ED640140;\n Wed, 16 Jun 2021 16:42:54 +0200 (CEST)", "from BN9PR03CA0491.namprd03.prod.outlook.com (2603:10b6:408:130::16)\n by BYAPR12MB2664.namprd12.prod.outlook.com (2603:10b6:a03:69::25)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.24; Wed, 16 Jun\n 2021 14:42:52 +0000", "from BN8NAM11FT062.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:130:cafe::b5) by BN9PR03CA0491.outlook.office365.com\n (2603:10b6:408:130::16) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.16 via Frontend\n Transport; Wed, 16 Jun 2021 14:42:52 +0000", "from mail.nvidia.com (216.228.112.34) by\n BN8NAM11FT062.mail.protection.outlook.com (10.13.177.34) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4242.16 via Frontend Transport; Wed, 16 Jun 2021 14:42:52 +0000", "from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun\n 2021 14:42:49 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=UgOi8tWgQMzqP8UkxNEPkB0KSsgpVb+11R4Gd3RR+DSfCMqg7SrfoSLDAM/zLrvxAQvgngl6syX2UcDm/WYub/1s+zJ7AvmneSd/Y7KwuXvqP8iLK7Z6zopshcyjlw07LrvJ8GepaY8j3T93qjO0Tfs4kHRz80JWhO7mQNSUllHGjW/2pq1Clp8oQK/3zZvQN/+4GczMMNvzYWqn4DBQaZSNXZeawsFth1PCPm46nJ01NqUCPYE7Jmdgo5CatP7Pv81gOf8JHa4HTj3IKKFncl0/nSUXhgOoUcPqO0Q0p4Z3qXmyPzlLtuqycnj6iS0DRKNPWS5uGPCYCgbWnqBPaA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=O5VgWt4dGIC3JwaiXh+sV7mXJCkVGJlATe+JMOmA4Hs=;\n b=ocB001yF/UMt5l01GYreaPwUVJAwNiHs5W38ffo7RhAJZKe8fDCC/Ps8kU+WrVDMA7+ViukT2CWJsRxFj2k2vZnW0zyUDrJgK10Gh1u28I6DyRTDVX11rDGC1gpkpyVdYwjEBy+2Q/+6gMyvL4lE2Wv3t5Cal7i0AIWxw986t5tgWzMu9Fa3I3IJMzbrm4z/adMeIQqxqUzAXcd9J15at/68xR16IPzDwhsIY5SkBYmbIGz3C7ft+wLGZZx8F7dxx5ZuDdBhZuYgqPFJJ3cRAmoYfcyTD0Nqf3qfGwJMoCep+qDv+Tp0dGVwJAC9oyrdmMOkcicIhQbgRgYs6FTK/w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=O5VgWt4dGIC3JwaiXh+sV7mXJCkVGJlATe+JMOmA4Hs=;\n b=JenEVwIUH5zJY+h7NsGYXrx6vQDDFFZc9vTwiJ+qdUcxe9XqjnBcfxQM0E6AqYdBEm4fPH9sTXUl4Qfo1algXAroThvIrxj73zEbLHM6OqWScmiDxGNI/YDjiSIfwoCQRvjQYbMQqYcNnOYO2JCClnLMwzU7fuGuWDVopgWV8AJSS2NXCkthzYk3GxkV4Nx1SdBONvOTTbKapFvygw8CSdU2r9KmPU03RWGrE63zfAkw+DvDeZVkcyORNP3wHjC90Gmao2nzY++1BTkvbbe10ff1ettJnEtaO+RUIWujSItc70906/n865LsahyLjnFcano70zeD8tEguMyjDQuaFg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<stable@dpdk.org>, <rasland@nvidia.com>, <viacheslavo@nvidia.com>,\n <matan@nvidia.com>", "Date": "Wed, 16 Jun 2021 17:42:36 +0300", "Message-ID": "<20210616144236.2802978-1-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "baae5e49-f24a-4c57-5bbf-08d930d50521", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB2664:", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB2664A4423218B85D21F297FDAF0F9@BYAPR12MB2664.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6108;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 5viX+vdfCgHMPNe7pHjhiUP9bO/FIGXlayJm2YWg2Rwqr+UgD6Yfzf2n3mVufQ8W3ZX18C+x1OKUE0MVhMc6+z661dYf9s8Z9Cx75rBi/QjZs3K1zQM4rWnz9AaPT4N60L/AWSrzTIKYBrWp6U3ZpyV8lcKn0zgx3J3jNgsfZR1oyYoxzfwZp2jie4jE1yti45WpKq/gksSV6L9y1oZaTJaSPlknD4v2UqKZh/S4nZV/2ho9lfG9gRPkjIH/sQprx5NtdtYFSKncxxXCVf5F9QeqRb3A2shGsOUKZt2okQ9SUIWAFv/HspthERIqA9o77+0XVA7mksI39JE+RM+7udbLjCloijkz9bbZHgXkik6Dr0kP2NBIxo+9e7beEFZIC5CRsWHLDobF0YVYtYd4npg0Pm8rE0PdxqidxqQ/a5d/+ho7M48RIB9QZvpBMtcxb2XAYvYwGKXEPZlVKdNscBHdgPXB8+3Qjr0s4rVfV9EAYO64LpS6uAxTYe7Llj6t67c6Cgt/9Z5MUTMoi62FeZX9srRXCqu7E2ljW48rwSWD/zrD98wl33Rvo6jZOI84P2FcW+0E08pO0pmvCcTYi4pMsPRvXed6wiQlBmMNYRTMUl0PRQkZ95bn7fQF6zT99nCN5gwQvGoV+yod369+1mZhw18lB56mRgzOv9mUHYA=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(36840700001)(46966006)(82310400003)(36906005)(8936002)(36860700001)(55016002)(1076003)(70206006)(86362001)(6286002)(6916009)(7696005)(478600001)(4326008)(36756003)(26005)(450100002)(83380400001)(82740400003)(6666004)(356005)(7636003)(16526019)(54906003)(336012)(186003)(2616005)(47076005)(2906002)(316002)(70586007)(107886003)(5660300002)(426003)(8676002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Jun 2021 14:42:52.0126 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n baae5e49-f24a-4c57-5bbf-08d930d50521", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT062.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB2664", "Subject": "[dpdk-dev] [PATCH] net/mlx5: fix modify field action order for MAC", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "MAC addresses are split into 2 parts inside Mellanox NIC:\nbits 0-15 are separate from bits 16-47. That makes a copy\nfrom another packet field tricky because any other field\nis aligned to 32 bits, not 16. This causes unexpected\nresults when using the MODIFY_FIELD action with MAC addresses.\nTrack crossing MAC addresses boundary and arrange a proper\norder for the MODIFY_FIELD action involving MAC addresses.\n\nFixes: 641dbe4fb053 (\"net/mlx5: support modify field flow action\")\nCc: stable@dpdk.org\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 109 ++++++++++++++++++++------------\n 1 file changed, 70 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex dafd37ab93..ba341197e6 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -426,6 +426,8 @@ flow_dv_convert_modify_action(struct rte_flow_item *item,\n \t\tunsigned int off_b;\n \t\tuint32_t mask;\n \t\tuint32_t data;\n+\t\tbool next_field = true;\n+\t\tbool next_dcopy = true;\n \n \t\tif (i >= MLX5_MAX_MODIFY_NUM)\n \t\t\treturn rte_flow_error_set(error, EINVAL,\n@@ -443,15 +445,13 @@ flow_dv_convert_modify_action(struct rte_flow_item *item,\n \t\tsize_b = sizeof(uint32_t) * CHAR_BIT -\n \t\t\t off_b - __builtin_clz(mask);\n \t\tMLX5_ASSERT(size_b);\n-\t\tsize_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;\n \t\tactions[i] = (struct mlx5_modification_cmd) {\n \t\t\t.action_type = type,\n \t\t\t.field = field->id,\n \t\t\t.offset = off_b,\n-\t\t\t.length = size_b,\n+\t\t\t.length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?\n+\t\t\t\t0 : size_b,\n \t\t};\n-\t\t/* Convert entire record to expected big-endian format. */\n-\t\tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n \t\tif (type == MLX5_MODIFICATION_TYPE_COPY) {\n \t\t\tMLX5_ASSERT(dcopy);\n \t\t\tactions[i].dst_field = dcopy->id;\n@@ -459,7 +459,27 @@ flow_dv_convert_modify_action(struct rte_flow_item *item,\n \t\t\t\t(int)dcopy->offset < 0 ? off_b : dcopy->offset;\n \t\t\t/* Convert entire record to big-endian format. */\n \t\t\tactions[i].data1 = rte_cpu_to_be_32(actions[i].data1);\n-\t\t\t++dcopy;\n+\t\t\t/*\n+\t\t\t * Destination field overflow. Copy leftovers of\n+\t\t\t * a source field to the next destination field.\n+\t\t\t */\n+\t\t\tif ((size_b > dcopy->size * CHAR_BIT) && dcopy->size) {\n+\t\t\t\tactions[i].length = dcopy->size * CHAR_BIT;\n+\t\t\t\tfield->offset += dcopy->size;\n+\t\t\t\tnext_field = false;\n+\t\t\t}\n+\t\t\t/*\n+\t\t\t * Not enough bits in a source filed to fill a\n+\t\t\t * destination field. Switch to the next source.\n+\t\t\t */\n+\t\t\tif (dcopy->size > field->size &&\n+\t\t\t (size_b == field->size * CHAR_BIT)) {\n+\t\t\t\tactions[i].length = field->size * CHAR_BIT;\n+\t\t\t\tdcopy->offset += field->size * CHAR_BIT;\n+\t\t\t\tnext_dcopy = false;\n+\t\t\t}\n+\t\t\tif (next_dcopy)\n+\t\t\t\t++dcopy;\n \t\t} else {\n \t\t\tMLX5_ASSERT(item->spec);\n \t\t\tdata = flow_dv_fetch_field((const uint8_t *)item->spec +\n@@ -468,8 +488,11 @@ flow_dv_convert_modify_action(struct rte_flow_item *item,\n \t\t\tdata = (data & mask) >> off_b;\n \t\t\tactions[i].data1 = rte_cpu_to_be_32(data);\n \t\t}\n+\t\t/* Convert entire record to expected big-endian format. */\n+\t\tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n+\t\tif (next_field)\n+\t\t\t++field;\n \t\t++i;\n-\t\t++field;\n \t} while (field->size);\n \tif (resource->actions_num == i)\n \t\treturn rte_flow_error_set(error, EINVAL,\n@@ -1433,6 +1456,7 @@ mlx5_flow_field_id_to_modify_info\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_config *config = &priv->config;\n \tuint32_t idx = 0;\n+\tuint32_t off = 0;\n \tuint64_t val = 0;\n \tswitch (data->field) {\n \tcase RTE_FLOW_FIELD_START:\n@@ -1440,61 +1464,63 @@ mlx5_flow_field_id_to_modify_info\n \t\tMLX5_ASSERT(false);\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_MAC_DST:\n+\t\toff = data->offset > 16 ? data->offset - 16 : 0;\n \t\tif (mask) {\n-\t\t\tif (data->offset < 32) {\n-\t\t\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\t\t\tMLX5_MODI_OUT_DMAC_47_16};\n-\t\t\t\tif (width < 32) {\n-\t\t\t\t\tmask[idx] =\n-\t\t\t\t\t\trte_cpu_to_be_32(0xffffffff >>\n-\t\t\t\t\t\t\t\t (32 - width));\n+\t\t\tif (data->offset < 16) {\n+\t\t\t\tinfo[idx] = (struct field_modify_info){2, 0,\n+\t\t\t\t\t\tMLX5_MODI_OUT_DMAC_15_0};\n+\t\t\t\tif (width < 16) {\n+\t\t\t\t\tmask[idx] = rte_cpu_to_be_16(0xffff >>\n+\t\t\t\t\t\t\t\t (16 - width));\n \t\t\t\t\twidth = 0;\n \t\t\t\t} else {\n-\t\t\t\t\tmask[idx] = RTE_BE32(0xffffffff);\n-\t\t\t\t\twidth -= 32;\n+\t\t\t\t\tmask[idx] = RTE_BE16(0xffff);\n+\t\t\t\t\twidth -= 16;\n \t\t\t\t}\n \t\t\t\tif (!width)\n \t\t\t\t\tbreak;\n \t\t\t\t++idx;\n \t\t\t}\n-\t\t\tinfo[idx] = (struct field_modify_info){2, 4 * idx,\n-\t\t\t\t\t\tMLX5_MODI_OUT_DMAC_15_0};\n-\t\t\tmask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));\n-\t\t} else {\n-\t\t\tif (data->offset < 32)\n-\t\t\t\tinfo[idx++] = (struct field_modify_info){4, 0,\n+\t\t\tinfo[idx] = (struct field_modify_info){4, 4 * idx,\n \t\t\t\t\t\tMLX5_MODI_OUT_DMAC_47_16};\n-\t\t\tinfo[idx] = (struct field_modify_info){2, 0,\n+\t\t\tmask[idx] = rte_cpu_to_be_32((0xffffffff >>\n+\t\t\t\t\t\t (32 - width)) << off);\n+\t\t} else {\n+\t\t\tif (data->offset < 16)\n+\t\t\t\tinfo[idx++] = (struct field_modify_info){2, 0,\n \t\t\t\t\t\tMLX5_MODI_OUT_DMAC_15_0};\n+\t\t\tinfo[idx] = (struct field_modify_info){4, off,\n+\t\t\t\t\t\tMLX5_MODI_OUT_DMAC_47_16};\n \t\t}\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_MAC_SRC:\n+\t\toff = data->offset > 16 ? data->offset - 16 : 0;\n \t\tif (mask) {\n-\t\t\tif (data->offset < 32) {\n-\t\t\t\tinfo[idx] = (struct field_modify_info){4, 0,\n-\t\t\t\t\t\tMLX5_MODI_OUT_SMAC_47_16};\n-\t\t\t\tif (width < 32) {\n-\t\t\t\t\tmask[idx] =\n-\t\t\t\t\t\trte_cpu_to_be_32(0xffffffff >>\n-\t\t\t\t\t\t\t\t(32 - width));\n+\t\t\tif (data->offset < 16) {\n+\t\t\t\tinfo[idx] = (struct field_modify_info){2, 0,\n+\t\t\t\t\t\tMLX5_MODI_OUT_SMAC_15_0};\n+\t\t\t\tif (width < 16) {\n+\t\t\t\t\tmask[idx] = rte_cpu_to_be_16(0xffff >>\n+\t\t\t\t\t\t\t\t (16 - width));\n \t\t\t\t\twidth = 0;\n \t\t\t\t} else {\n-\t\t\t\t\tmask[idx] = RTE_BE32(0xffffffff);\n-\t\t\t\t\twidth -= 32;\n+\t\t\t\t\tmask[idx] = RTE_BE16(0xffff);\n+\t\t\t\t\twidth -= 16;\n \t\t\t\t}\n \t\t\t\tif (!width)\n \t\t\t\t\tbreak;\n \t\t\t\t++idx;\n \t\t\t}\n-\t\t\tinfo[idx] = (struct field_modify_info){2, 4 * idx,\n-\t\t\t\t\t\tMLX5_MODI_OUT_SMAC_15_0};\n-\t\t\tmask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));\n-\t\t} else {\n-\t\t\tif (data->offset < 32)\n-\t\t\t\tinfo[idx++] = (struct field_modify_info){4, 0,\n+\t\t\tinfo[idx] = (struct field_modify_info){4, 4 * idx,\n \t\t\t\t\t\tMLX5_MODI_OUT_SMAC_47_16};\n-\t\t\tinfo[idx] = (struct field_modify_info){2, 0,\n+\t\t\tmask[idx] = rte_cpu_to_be_32((0xffffffff >>\n+\t\t\t\t\t\t (32 - width)) << off);\n+\t\t} else {\n+\t\t\tif (data->offset < 16)\n+\t\t\t\tinfo[idx++] = (struct field_modify_info){2, 0,\n \t\t\t\t\t\tMLX5_MODI_OUT_SMAC_15_0};\n+\t\t\tinfo[idx] = (struct field_modify_info){4, off,\n+\t\t\t\t\t\tMLX5_MODI_OUT_SMAC_47_16};\n \t\t}\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_VLAN_TYPE:\n@@ -1818,7 +1844,12 @@ mlx5_flow_field_id_to_modify_info\n \t\t\tval = data->value;\n \t\tfor (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {\n \t\t\tif (mask[idx]) {\n-\t\t\t\tif (dst_width > 16) {\n+\t\t\t\tif (dst_width == 48) {\n+\t\t\t\t\t/*special case for MAC addresses */\n+\t\t\t\t\tvalue[idx] = rte_cpu_to_be_16(val);\n+\t\t\t\t\tval >>= 16;\n+\t\t\t\t\tdst_width -= 16;\n+\t\t\t\t} else if (dst_width > 16) {\n \t\t\t\t\tvalue[idx] = rte_cpu_to_be_32(val);\n \t\t\t\t\tval >>= 32;\n \t\t\t\t} else if (dst_width > 8) {\n", "prefixes": [] }