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{
    "id": 94172,
    "url": "https://patches.dpdk.org/api/patches/94172/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210613000652.28191-40-ajit.khaparde@broadcom.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
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    "msgid": "<20210613000652.28191-40-ajit.khaparde@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210613000652.28191-40-ajit.khaparde@broadcom.com",
    "date": "2021-06-13T00:06:33",
    "name": "[v2,39/58] net/bnxt: refactor TRUFLOW processing",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "536e91b473dec622d6aa29bcd55b977d68d65690",
    "submitter": {
        "id": 501,
        "url": "https://patches.dpdk.org/api/people/501/?format=api",
        "name": "Ajit Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "https://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210613000652.28191-40-ajit.khaparde@broadcom.com/mbox/",
    "series": [
        {
            "id": 17305,
            "url": "https://patches.dpdk.org/api/series/17305/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17305",
            "date": "2021-06-13T00:05:54",
            "name": "enhancements to host based flow table management",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/17305/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/94172/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/94172/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>,\n Shahaji Bhosle <sbhosle@broadcom.com>,\n Randy Schacher <stuart.schacher@broadcom.com>,\n Mike Baucom <michael.baucom@broadcom.com>",
        "Date": "Sat, 12 Jun 2021 17:06:33 -0700",
        "Message-Id": "<20210613000652.28191-40-ajit.khaparde@broadcom.com>",
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        "References": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>\n <20210613000652.28191-1-ajit.khaparde@broadcom.com>",
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        "X-Mailman-Approved-At": "Mon, 14 Jun 2021 16:37:12 +0200",
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        "Subject": "[dpdk-dev] [PATCH v2 39/58] net/bnxt: refactor TRUFLOW processing",
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    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\n1. The flow database opcode is updated to split the alloc push resource\nitem so it can be controlled using the control table.\n\n2. The class and action match signatures are populated with pattern ids\nthat are matched against template pattern id to reject any unsupported\nclass and action combinations.\n\n3. The flow DB opcode should be no op when accessing the\nglobal registry identifiers.\n\n4. The resource function for branch is changed to control so that it\nis extended to perform flow database operations and not just branch\noperations.\n\n5. The conditional goto processing now supports negative numbers to\nsupport looping of the mapper tables to support flow ranges and\nalso enable conditional fail goto to support failure path mapper\ntables.\n\n6. The field mapper opcode is updated to add all ones to fields\nthat support exact match.\n\n7. Added key info and identifier list to whitney action templates\nThe whitney plus templates are updated to use the mapper infrastructure\nchanges.\n\n8. The partition interface table configuration of the default\negress rule for the representor interface needs to use the\nreserved parif interface that is specific to each\nplatform. The pipeline for the representor interface is broken\nsince incorrect parif configuration cause the miss path packets to\nbe dropped.\n\n9. In the mapper table processing, if a failure condition is hit\ndue to invalid memory type then use the conditional goto failure\nconfiguration instead of jumping to next table. This causes ipv6\nexact match entry to be skipped. This patch fixes that issue.\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Mike Baucom <michael.baucom@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c       |    32 +-\n drivers/net/bnxt/tf_ulp/ulp_def_rules.c       |     3 +\n drivers/net/bnxt/tf_ulp/ulp_flow_db.c         |    53 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.c          |   101 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.h          |     7 +\n drivers/net/bnxt/tf_ulp/ulp_matcher.c         |     2 +\n drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |   644 +-\n .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 80798 +++++++++++++++-\n .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |  4140 +-\n .../net/bnxt/tf_ulp/ulp_template_db_field.h   |   558 +-\n .../tf_ulp/ulp_template_db_stingray_act.c     |    16 +-\n .../tf_ulp/ulp_template_db_stingray_class.c   |   154 +-\n drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c |   512 +-\n drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h |     4 +\n .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c |  4470 +-\n .../tf_ulp/ulp_template_db_wh_plus_class.c    | 13072 ++-\n drivers/net/bnxt/tf_ulp/ulp_template_struct.h |     7 +-\n 17 files changed, 98370 insertions(+), 6203 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\nindex 2c1a2a7be3..ec272c3a8f 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c\n@@ -79,21 +79,23 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,\n \t\t\t    struct ulp_rte_parser_params *params,\n \t\t\t    enum bnxt_ulp_fdb_type flow_type)\n {\n-\tmapper_cparms->flow_type\t= flow_type;\n-\tmapper_cparms->app_priority\t= params->priority;\n-\tmapper_cparms->dir_attr\t\t= params->dir_attr;\n-\tmapper_cparms->class_tid\t= params->class_id;\n-\tmapper_cparms->act_tid\t\t= params->act_tmpl;\n-\tmapper_cparms->func_id\t\t= params->func_id;\n-\tmapper_cparms->hdr_bitmap\t= &params->hdr_bitmap;\n-\tmapper_cparms->hdr_field\t= params->hdr_field;\n-\tmapper_cparms->comp_fld\t\t= params->comp_fld;\n-\tmapper_cparms->act\t\t= &params->act_bitmap;\n-\tmapper_cparms->act_prop\t\t= &params->act_prop;\n-\tmapper_cparms->flow_id\t\t= params->fid;\n-\tmapper_cparms->parent_flow\t= params->parent_flow;\n-\tmapper_cparms->parent_fid\t= params->parent_fid;\n-\tmapper_cparms->fld_bitmap\t= &params->fld_bitmap;\n+\tmapper_cparms->flow_type = flow_type;\n+\tmapper_cparms->app_priority = params->priority;\n+\tmapper_cparms->dir_attr = params->dir_attr;\n+\tmapper_cparms->class_tid = params->class_id;\n+\tmapper_cparms->act_tid = params->act_tmpl;\n+\tmapper_cparms->func_id = params->func_id;\n+\tmapper_cparms->hdr_bitmap = &params->hdr_bitmap;\n+\tmapper_cparms->hdr_field = params->hdr_field;\n+\tmapper_cparms->comp_fld = params->comp_fld;\n+\tmapper_cparms->act = &params->act_bitmap;\n+\tmapper_cparms->act_prop = &params->act_prop;\n+\tmapper_cparms->flow_id = params->fid;\n+\tmapper_cparms->parent_flow = params->parent_flow;\n+\tmapper_cparms->parent_fid = params->parent_fid;\n+\tmapper_cparms->fld_bitmap = &params->fld_bitmap;\n+\tmapper_cparms->flow_pattern_id = params->flow_pattern_id;\n+\tmapper_cparms->act_pattern_id = params->act_pattern_id;\n \n \t/* update the signature fields into the computed field list */\n \tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c\nindex f3b8d81766..75640ce092 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c\n@@ -360,6 +360,9 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,\n \t\tgoto err1;\n \t}\n \n+\tBNXT_TF_DBG(DEBUG, \"Creating default flow with template id: %u\\n\",\n+\t\t    ulp_class_tid);\n+\n \t/* Protect flow creation */\n \tif (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {\n \t\tBNXT_TF_DBG(ERR, \"Flow db lock acquire failed\\n\");\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c\nindex 8537388da6..1326f79ff5 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c\n@@ -48,21 +48,17 @@ ulp_flow_db_active_flows_bit_set(struct bnxt_ulp_flow_db *flow_db,\n \tuint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE;\n \n \tif (flag) {\n-\t\tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type ==\n-\t\t    BNXT_ULP_FDB_TYPE_RID)\n+\t\tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)\n \t\t\tULP_INDEX_BITMAP_SET(f_tbl->active_reg_flows[a_idx],\n \t\t\t\t\t     idx);\n-\t\tif (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type ==\n-\t\t    BNXT_ULP_FDB_TYPE_RID)\n+\t\telse\n \t\t\tULP_INDEX_BITMAP_SET(f_tbl->active_dflt_flows[a_idx],\n \t\t\t\t\t     idx);\n \t} else {\n-\t\tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type ==\n-\t\t    BNXT_ULP_FDB_TYPE_RID)\n+\t\tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)\n \t\t\tULP_INDEX_BITMAP_RESET(f_tbl->active_reg_flows[a_idx],\n \t\t\t\t\t       idx);\n-\t\tif (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type ==\n-\t\t    BNXT_ULP_FDB_TYPE_RID)\n+\t\telse\n \t\t\tULP_INDEX_BITMAP_RESET(f_tbl->active_dflt_flows[a_idx],\n \t\t\t\t\t       idx);\n \t}\n@@ -89,15 +85,9 @@ ulp_flow_db_active_flows_bit_is_set(struct bnxt_ulp_flow_db *flow_db,\n \tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)\n \t\treturn ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],\n \t\t\t\t\t    idx);\n-\telse if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT)\n+\telse\n \t\treturn ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx],\n \t\t\t\t\t    idx);\n-\telse if (flow_type == BNXT_ULP_FDB_TYPE_RID)\n-\t\treturn (ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],\n-\t\t\t\t\t     idx) &&\n-\t\t\tULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],\n-\t\t\t\t\t     idx));\n-\treturn 0;\n }\n \n static inline enum tf_dir\n@@ -223,7 +213,7 @@ ulp_flow_db_alloc_resource(struct bnxt_ulp_flow_db *flow_db)\n \t\treturn -ENOMEM;\n \t}\n \tsize = (flow_tbl->num_flows / sizeof(uint64_t)) + 1;\n-\tsize = ULP_BYTE_ROUND_OFF_8(size);\n+\tsize =  ULP_BYTE_ROUND_OFF_8(size);\n \tflow_tbl->active_reg_flows = rte_zmalloc(\"active reg flows\", size,\n \t\t\t\t\t\t ULP_BUFFER_ALIGN_64_BYTE);\n \tif (!flow_tbl->active_reg_flows) {\n@@ -627,7 +617,7 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -684,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -698,7 +688,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,\n \n \t/* check if the flow is active or not */\n \tif (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {\n-\t\tBNXT_TF_DBG(ERR, \"flow does not exist %x:%x\\n\", flow_type, fid);\n+\t\tBNXT_TF_DBG(ERR, \"flow does not exist\\n\");\n \t\treturn -EINVAL;\n \t}\n \n@@ -779,7 +769,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -793,7 +783,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,\n \n \t/* check if the flow is active or not */\n \tif (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {\n-\t\tBNXT_TF_DBG(ERR, \"flow does not exist %x:%x\\n\", flow_type, fid);\n+\t\tBNXT_TF_DBG(ERR, \"flow does not exist\\n\");\n \t\treturn -EINVAL;\n \t}\n \n@@ -887,7 +877,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -902,7 +892,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,\n \n \t/* check if the flow is active or not */\n \tif (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {\n-\t\tBNXT_TF_DBG(ERR, \"flow does not exist %x:%x\\n\", flow_type, fid);\n+\t\tBNXT_TF_DBG(ERR, \"flow does not exist\\n\");\n \t\treturn -EINVAL;\n \t}\n \tflow_tbl->head_index--;\n@@ -910,7 +900,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,\n \t\tBNXT_TF_DBG(ERR, \"FlowDB: Head Ptr is zero\\n\");\n \t\treturn -ENOENT;\n \t}\n-\n \tflow_tbl->flow_tbl_stack[flow_tbl->head_index] = fid;\n \n \t/* Clear the flows bitmap */\n@@ -924,7 +913,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,\n }\n \n /*\n- *Get the flow database entry details\n+ * Get the flow database entry details\n  *\n  * ulp_ctxt [in] Ptr to ulp_context\n  * flow_type [in] - specify default or regular\n@@ -951,7 +940,7 @@ ulp_flow_db_resource_get(struct bnxt_ulp_context *ulp_ctxt,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -1007,14 +996,10 @@ ulp_flow_db_next_entry_get(struct bnxt_ulp_flow_db *flow_db,\n \tuint64_t *active_flows;\n \tstruct bnxt_ulp_flow_tbl *flowtbl = &flow_db->flow_tbl;\n \n-\tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) {\n+\tif (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)\n \t\tactive_flows = flowtbl->active_reg_flows;\n-\t} else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) {\n+\telse\n \t\tactive_flows = flowtbl->active_dflt_flows;\n-\t} else {\n-\t\tBNXT_TF_DBG(ERR, \"Invalid flow type %x\\n\", flow_type);\n-\t\t\treturn -EINVAL;\n-\t}\n \n \tdo {\n \t\t/* increment the flow id to find the next valid flow id */\n@@ -1207,7 +1192,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -1609,7 +1594,7 @@ ulp_flow_db_child_flow_reset(struct bnxt_ulp_context *ulp_ctxt,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {\n+\tif (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {\n \t\tBNXT_TF_DBG(ERR, \"Invalid flow type\\n\");\n \t\treturn -EINVAL;\n \t}\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\nindex e1717b5dc4..c231f765e6 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n@@ -19,6 +19,11 @@\n #include \"tf_util.h\"\n #include \"ulp_template_db_tbl.h\"\n \n+static uint8_t mapper_fld_ones[16] = {\n+\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n+\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF\n+};\n+\n static const char *\n ulp_mapper_tmpl_name_str(enum bnxt_ulp_template_type tmpl_type)\n {\n@@ -591,12 +596,11 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \tint32_t rc = 0;\n \n \tswitch (tbl->fdb_opcode) {\n-\tcase BNXT_ULP_FDB_OPC_PUSH:\n+\tcase BNXT_ULP_FDB_OPC_PUSH_FID:\n \t\tpush_fid = parms->fid;\n \t\tflow_type = parms->flow_type;\n \t\tbreak;\n-\tcase BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE:\n-\tcase BNXT_ULP_FDB_OPC_PUSH_REGFILE:\n+\tcase BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE:\n \t\t/* get the fid from the regfile */\n \t\trc = ulp_regfile_read(parms->regfile, tbl->fdb_operand,\n \t\t\t\t      &val64);\n@@ -1049,6 +1053,13 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_ONES:\n+\t\tval = mapper_fld_ones;\n+\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s too large for blob\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n \tcase BNXT_ULP_FIELD_SRC_CF:\n \t\tif (!ulp_operand_read(fld_src_oper,\n \t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n@@ -2076,6 +2087,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \t\twrite = true;\n \t\tbreak;\n \tcase BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE:\n+\t\tif (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {\n+\t\t\tBNXT_TF_DBG(ERR, \"Template error, wrong fdb opcode\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n \t\t/*\n \t\t * get the index to write to from the global regfile and then\n \t\t * write the table.\n@@ -2470,8 +2485,10 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\t\t\t    \"Failed to scan ident list\\n\");\n \t\t\t\treturn -EINVAL;\n \t\t\t}\n-\t\t\t/* increment the reference count */\n-\t\t\tULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);\n+\t\t\tif (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {\n+\t\t\t\t/* increment the reference count */\n+\t\t\t\tULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);\n+\t\t\t}\n \n \t\t\t/* it is a hit */\n \t\t\tgen_tbl_hit = 1;\n@@ -2545,6 +2562,23 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n \treturn rc;\n }\n \n+static int32_t\n+ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms,\n+\t\t\t    struct bnxt_ulp_mapper_tbl_info *tbl)\n+{\n+\tint32_t rc = 0;\n+\n+\t/* process the fdb opcode for alloc push */\n+\tif (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE) {\n+\t\trc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl);\n+\t\tif (rc) {\n+\t\t\tBNXT_TF_DBG(ERR, \"Failed to do fdb alloc\\n\");\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\treturn rc;\n+}\n+\n static int32_t\n ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,\n \t\t\t\t  struct bnxt_ulp_mapper_data *mapper_data)\n@@ -2598,7 +2632,10 @@ ulp_mapper_tbl_memtype_opcode_process(struct bnxt_ulp_mapper_parms *parms,\n \tenum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT;\n \tint32_t rc = 1;\n \n-\tbnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);\n+\tif (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {\n+\t\tBNXT_TF_DBG(ERR, \"Failed to get the mem type\\n\");\n+\t\treturn rc;\n+\t}\n \n \tswitch (tbl->mem_type_opcode) {\n \tcase BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT:\n@@ -2725,6 +2762,20 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t}\n \t\t*res = regval == 0;\n \t\tbreak;\n+\tcase BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:\n+\t\tif (parms->flow_pattern_id == operand) {\n+\t\t\tBNXT_TF_DBG(ERR, \"field pattern match failed %x\\n\",\n+\t\t\t\t    parms->flow_pattern_id);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase BNXT_ULP_COND_OPC_ACT_PAT_MATCH:\n+\t\tif (parms->act_pattern_id == operand) {\n+\t\t\tBNXT_TF_DBG(ERR, \"act pattern match failed %x\\n\",\n+\t\t\t\t    parms->act_pattern_id);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n \tdefault:\n \t\tBNXT_TF_DBG(ERR, \"Invalid conditional opcode %d\\n\", opc);\n \t\trc = -EINVAL;\n@@ -2748,7 +2799,7 @@ ulp_mapper_cond_opc_list_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\t\t int32_t *res)\n {\n \tuint32_t i;\n-\tint32_t rc = 0, trc;\n+\tint32_t rc = 0, trc = 0;\n \n \tswitch (list_opc) {\n \tcase BNXT_ULP_COND_LIST_OPC_AND:\n@@ -2870,7 +2921,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \tstruct bnxt_ulp_mapper_tbl_info *tbl;\n \tuint32_t num_tbls, tbl_idx, num_cond_tbls;\n \tint32_t rc = -EINVAL, cond_rc = 0;\n-\tuint32_t cond_goto = 1;\n+\tint32_t cond_goto = 1;\n \n \tcond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid,\n \t\t\t\t\t\t    &num_cond_tbls,\n@@ -2907,11 +2958,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \n \tfor (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {\n \t\ttbl = &tbls[tbl_idx];\n-\t\tcond_goto = tbl->execute_info.cond_goto;\n \t\t/* Handle the table level opcodes to determine if required. */\n \t\tif (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) {\n-\t\t\ttbl_idx += 1;\n-\t\t\tcontinue;\n+\t\t\tcond_goto = tbl->execute_info.cond_false_goto;\n+\t\t\tgoto next_iteration;\n \t\t}\n \n \t\tcond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl,\n@@ -2927,17 +2977,8 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\t}\n \t\t/* Skip the table if False */\n \t\tif (!cond_rc) {\n-\t\t\ttbl_idx += 1;\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\t/* process the fdb opcode for alloc push */\n-\t\tif (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) {\n-\t\t\trc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl);\n-\t\t\tif (rc) {\n-\t\t\t\tBNXT_TF_DBG(ERR, \"Failed to do fdb alloc\\n\");\n-\t\t\t\treturn rc;\n-\t\t\t}\n+\t\t\tcond_goto = tbl->execute_info.cond_false_goto;\n+\t\t\tgoto next_iteration;\n \t\t}\n \n \t\tswitch (tbl->resource_func) {\n@@ -2957,8 +2998,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\tcase BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE:\n \t\t\trc = ulp_mapper_gen_tbl_process(parms, tbl);\n \t\t\tbreak;\n+\t\tcase BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE:\n+\t\t\trc = ulp_mapper_ctrl_tbl_process(parms, tbl);\n+\t\t\tbreak;\n \t\tcase BNXT_ULP_RESOURCE_FUNC_INVALID:\n-\t\tcase BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE:\n \t\t\trc = 0;\n \t\t\tbreak;\n \t\tdefault:\n@@ -2982,6 +3025,12 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\t\trc = -EINVAL;\n \t\t\tgoto error;\n \t\t}\n+next_iteration:\n+\t\tif (cond_goto < 0 && ((int32_t)tbl_idx + cond_goto) < 0) {\n+\t\t\tBNXT_TF_DBG(ERR, \"invalid conditional goto %d\\n\",\n+\t\t\t\t    cond_goto);\n+\t\t\tgoto error;\n+\t\t}\n \t\ttbl_idx += cond_goto;\n \t}\n \n@@ -3062,7 +3111,9 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,\n \t * Set the critical resource on the first resource del, then iterate\n \t * while status is good\n \t */\n-\tres_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;\n+\tif (flow_type != BNXT_ULP_FDB_TYPE_RID)\n+\t\tres_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;\n+\n \trc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);\n \n \tif (rc) {\n@@ -3236,6 +3287,8 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,\n \tparms.fid = cparms->flow_id;\n \tparms.tun_idx = cparms->tun_idx;\n \tparms.app_priority = cparms->app_priority;\n+\tparms.flow_pattern_id = cparms->flow_pattern_id;\n+\tparms.act_pattern_id = cparms->act_pattern_id;\n \n \t/* Get the device id from the ulp context */\n \tif (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) {\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h\nindex b7399b8949..8f0b894d39 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h\n@@ -58,6 +58,8 @@ struct bnxt_ulp_mapper_parms {\n \tuint8_t\t\t\t\t\ttun_idx;\n \tuint32_t\t\t\t\tapp_priority;\n \tuint64_t\t\t\t\tshared_hndl;\n+\tuint32_t\t\t\t\tflow_pattern_id;\n+\tuint32_t\t\t\t\tact_pattern_id;\n };\n \n struct bnxt_ulp_mapper_create_parms {\n@@ -80,6 +82,11 @@ struct bnxt_ulp_mapper_create_parms {\n \t/* if set then create a parent flow */\n \tuint32_t\t\t\tparent_flow;\n \tuint8_t\t\t\t\ttun_idx;\n+\n+\t/* support pattern based rejection */\n+\tuint32_t\t\t\tflow_pattern_id;\n+\tuint32_t\t\t\tact_pattern_id;\n+\n };\n \n /* Function to initialize any dynamic mapper data. */\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c\nindex 275214d489..46ac57ac00 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c\n@@ -79,6 +79,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,\n \t*class_id = class_match->class_tid;\n \tparams->hdr_sig_id = class_match->hdr_sig_id;\n \tparams->flow_sig_id = class_match->flow_sig_id;\n+\tparams->flow_pattern_id = class_match->flow_pattern_id;\n \treturn BNXT_TF_RC_SUCCESS;\n \n error:\n@@ -115,6 +116,7 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params,\n \t\tgoto error;\n \t}\n \t*act_id = act_match->act_tid;\n+\tparams->act_pattern_id = act_match->act_pattern_id;\n \tBNXT_TF_DBG(DEBUG, \"Found matching action template %u\\n\", *act_id);\n \treturn BNXT_TF_RC_SUCCESS;\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c\nindex 50eac7f99b..29ec409ee8 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  8 14:57:13 2020 */\n+/* date: Thu Dec 17 19:43:07 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -18,32 +18,88 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {\n \t[BNXT_ULP_ACT_HID_0000] = 1,\n \t[BNXT_ULP_ACT_HID_0001] = 2,\n \t[BNXT_ULP_ACT_HID_0400] = 3,\n-\t[BNXT_ULP_ACT_HID_0325] = 4,\n+\t[BNXT_ULP_ACT_HID_01ab] = 4,\n \t[BNXT_ULP_ACT_HID_0010] = 5,\n-\t[BNXT_ULP_ACT_HID_0725] = 6,\n-\t[BNXT_ULP_ACT_HID_0335] = 7,\n+\t[BNXT_ULP_ACT_HID_05ab] = 6,\n+\t[BNXT_ULP_ACT_HID_01bb] = 7,\n \t[BNXT_ULP_ACT_HID_0002] = 8,\n \t[BNXT_ULP_ACT_HID_0003] = 9,\n \t[BNXT_ULP_ACT_HID_0402] = 10,\n-\t[BNXT_ULP_ACT_HID_0327] = 11,\n+\t[BNXT_ULP_ACT_HID_01ad] = 11,\n \t[BNXT_ULP_ACT_HID_0012] = 12,\n-\t[BNXT_ULP_ACT_HID_0727] = 13,\n-\t[BNXT_ULP_ACT_HID_0337] = 14,\n-\t[BNXT_ULP_ACT_HID_01de] = 15,\n-\t[BNXT_ULP_ACT_HID_00c6] = 16,\n-\t[BNXT_ULP_ACT_HID_0506] = 17,\n-\t[BNXT_ULP_ACT_HID_01ed] = 18,\n-\t[BNXT_ULP_ACT_HID_03ef] = 19,\n-\t[BNXT_ULP_ACT_HID_0516] = 20,\n-\t[BNXT_ULP_ACT_HID_01df] = 21,\n-\t[BNXT_ULP_ACT_HID_01e4] = 22,\n-\t[BNXT_ULP_ACT_HID_00cc] = 23,\n-\t[BNXT_ULP_ACT_HID_0504] = 24,\n-\t[BNXT_ULP_ACT_HID_01ef] = 25,\n-\t[BNXT_ULP_ACT_HID_03ed] = 26,\n-\t[BNXT_ULP_ACT_HID_0514] = 27,\n-\t[BNXT_ULP_ACT_HID_00db] = 28,\n-\t[BNXT_ULP_ACT_HID_00df] = 29\n+\t[BNXT_ULP_ACT_HID_05ad] = 13,\n+\t[BNXT_ULP_ACT_HID_01bd] = 14,\n+\t[BNXT_ULP_ACT_HID_0613] = 15,\n+\t[BNXT_ULP_ACT_HID_02a9] = 16,\n+\t[BNXT_ULP_ACT_HID_0054] = 17,\n+\t[BNXT_ULP_ACT_HID_0622] = 18,\n+\t[BNXT_ULP_ACT_HID_0454] = 19,\n+\t[BNXT_ULP_ACT_HID_0064] = 20,\n+\t[BNXT_ULP_ACT_HID_0614] = 21,\n+\t[BNXT_ULP_ACT_HID_0615] = 22,\n+\t[BNXT_ULP_ACT_HID_02ab] = 23,\n+\t[BNXT_ULP_ACT_HID_0056] = 24,\n+\t[BNXT_ULP_ACT_HID_0624] = 25,\n+\t[BNXT_ULP_ACT_HID_0456] = 26,\n+\t[BNXT_ULP_ACT_HID_0066] = 27,\n+\t[BNXT_ULP_ACT_HID_048d] = 28,\n+\t[BNXT_ULP_ACT_HID_048f] = 29,\n+\t[BNXT_ULP_ACT_HID_04bc] = 30,\n+\t[BNXT_ULP_ACT_HID_00a9] = 31,\n+\t[BNXT_ULP_ACT_HID_020f] = 32,\n+\t[BNXT_ULP_ACT_HID_04a9] = 33,\n+\t[BNXT_ULP_ACT_HID_01fc] = 34,\n+\t[BNXT_ULP_ACT_HID_04be] = 35,\n+\t[BNXT_ULP_ACT_HID_00ab] = 36,\n+\t[BNXT_ULP_ACT_HID_0211] = 37,\n+\t[BNXT_ULP_ACT_HID_04ab] = 38,\n+\t[BNXT_ULP_ACT_HID_01fe] = 39,\n+\t[BNXT_ULP_ACT_HID_0667] = 40,\n+\t[BNXT_ULP_ACT_HID_0254] = 41,\n+\t[BNXT_ULP_ACT_HID_03ba] = 42,\n+\t[BNXT_ULP_ACT_HID_0654] = 43,\n+\t[BNXT_ULP_ACT_HID_03a7] = 44,\n+\t[BNXT_ULP_ACT_HID_0669] = 45,\n+\t[BNXT_ULP_ACT_HID_0256] = 46,\n+\t[BNXT_ULP_ACT_HID_03bc] = 47,\n+\t[BNXT_ULP_ACT_HID_0656] = 48,\n+\t[BNXT_ULP_ACT_HID_03a9] = 49,\n+\t[BNXT_ULP_ACT_HID_021b] = 50,\n+\t[BNXT_ULP_ACT_HID_021c] = 51,\n+\t[BNXT_ULP_ACT_HID_021e] = 52,\n+\t[BNXT_ULP_ACT_HID_063f] = 53,\n+\t[BNXT_ULP_ACT_HID_0510] = 54,\n+\t[BNXT_ULP_ACT_HID_03c6] = 55,\n+\t[BNXT_ULP_ACT_HID_0082] = 56,\n+\t[BNXT_ULP_ACT_HID_06bb] = 57,\n+\t[BNXT_ULP_ACT_HID_021d] = 58,\n+\t[BNXT_ULP_ACT_HID_0641] = 59,\n+\t[BNXT_ULP_ACT_HID_0512] = 60,\n+\t[BNXT_ULP_ACT_HID_03c8] = 61,\n+\t[BNXT_ULP_ACT_HID_0084] = 62,\n+\t[BNXT_ULP_ACT_HID_06bd] = 63,\n+\t[BNXT_ULP_ACT_HID_06d7] = 64,\n+\t[BNXT_ULP_ACT_HID_02c4] = 65,\n+\t[BNXT_ULP_ACT_HID_042a] = 66,\n+\t[BNXT_ULP_ACT_HID_06c4] = 67,\n+\t[BNXT_ULP_ACT_HID_0417] = 68,\n+\t[BNXT_ULP_ACT_HID_06d9] = 69,\n+\t[BNXT_ULP_ACT_HID_02c6] = 70,\n+\t[BNXT_ULP_ACT_HID_042c] = 71,\n+\t[BNXT_ULP_ACT_HID_06c6] = 72,\n+\t[BNXT_ULP_ACT_HID_0419] = 73,\n+\t[BNXT_ULP_ACT_HID_0119] = 74,\n+\t[BNXT_ULP_ACT_HID_046f] = 75,\n+\t[BNXT_ULP_ACT_HID_05d5] = 76,\n+\t[BNXT_ULP_ACT_HID_0106] = 77,\n+\t[BNXT_ULP_ACT_HID_05c2] = 78,\n+\t[BNXT_ULP_ACT_HID_011b] = 79,\n+\t[BNXT_ULP_ACT_HID_0471] = 80,\n+\t[BNXT_ULP_ACT_HID_05d7] = 81,\n+\t[BNXT_ULP_ACT_HID_0108] = 82,\n+\t[BNXT_ULP_ACT_HID_05c4] = 83,\n+\t[BNXT_ULP_ACT_HID_00a2] = 84,\n+\t[BNXT_ULP_ACT_HID_00a4] = 85\n };\n \n /* Array for the act matcher list */\n@@ -69,7 +125,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[4] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0325,\n+\t.act_hid = BNXT_ULP_ACT_HID_01ab,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n@@ -83,7 +139,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[6] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0725,\n+\t.act_hid = BNXT_ULP_ACT_HID_05ab,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n \t\tBNXT_ULP_ACT_BIT_POP_VLAN |\n@@ -91,7 +147,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[7] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0335,\n+\t.act_hid = BNXT_ULP_ACT_HID_01bb,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n@@ -122,7 +178,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[11] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0327,\n+\t.act_hid = BNXT_ULP_ACT_HID_01ad,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n@@ -138,7 +194,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[13] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0727,\n+\t.act_hid = BNXT_ULP_ACT_HID_05ad,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n@@ -147,7 +203,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[14] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0337,\n+\t.act_hid = BNXT_ULP_ACT_HID_01bd,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n \t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n@@ -156,7 +212,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[15] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_01de,\n+\t.act_hid = BNXT_ULP_ACT_HID_0613,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_DROP |\n@@ -164,7 +220,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[16] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_00c6,\n+\t.act_hid = BNXT_ULP_ACT_HID_02a9,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_POP_VLAN |\n@@ -172,7 +228,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[17] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0506,\n+\t.act_hid = BNXT_ULP_ACT_HID_0054,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n@@ -180,7 +236,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[18] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_01ed,\n+\t.act_hid = BNXT_ULP_ACT_HID_0622,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n@@ -188,7 +244,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[19] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_03ef,\n+\t.act_hid = BNXT_ULP_ACT_HID_0454,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n@@ -197,7 +253,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[20] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0516,\n+\t.act_hid = BNXT_ULP_ACT_HID_0064,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n@@ -206,7 +262,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[21] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_01df,\n+\t.act_hid = BNXT_ULP_ACT_HID_0614,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -214,7 +270,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[22] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_01e4,\n+\t.act_hid = BNXT_ULP_ACT_HID_0615,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -223,7 +279,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[23] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_00cc,\n+\t.act_hid = BNXT_ULP_ACT_HID_02ab,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -232,7 +288,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[24] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0504,\n+\t.act_hid = BNXT_ULP_ACT_HID_0056,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -241,7 +297,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[25] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_01ef,\n+\t.act_hid = BNXT_ULP_ACT_HID_0624,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -250,7 +306,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[26] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_03ed,\n+\t.act_hid = BNXT_ULP_ACT_HID_0456,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -260,7 +316,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[27] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_0514,\n+\t.act_hid = BNXT_ULP_ACT_HID_0066,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n@@ -270,7 +326,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 1\n \t},\n \t[28] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_00db,\n+\t.act_hid = BNXT_ULP_ACT_HID_048d,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED |\n \t\tBNXT_ULP_ACT_BIT_SAMPLE |\n@@ -278,12 +334,514 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t.act_tid = 2\n \t},\n \t[29] = {\n-\t.act_hid = BNXT_ULP_ACT_HID_00df,\n+\t.act_hid = BNXT_ULP_ACT_HID_048f,\n \t.act_sig = { .bits =\n \t\tBNXT_ULP_ACT_BIT_SHARED |\n \t\tBNXT_ULP_ACT_BIT_SAMPLE |\n \t\tBNXT_ULP_ACT_BIT_COUNT |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 2\n+\t},\n+\t[30] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_04bc,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[31] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_00a9,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[32] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_020f,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[33] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_04a9,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[34] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_01fc,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[35] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_04be,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[36] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_00ab,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[37] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0211,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[38] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_04ab,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[39] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_01fe,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[40] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0667,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[41] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0254,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[42] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_03ba,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[43] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0654,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[44] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_03a7,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[45] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0669,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[46] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0256,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[47] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_03bc,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[48] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0656,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[49] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_03a9,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.act_tid = 3\n+\t},\n+\t[50] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_021b,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[51] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_021c,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DROP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[52] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_021e,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DROP |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[53] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_063f,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_PCP |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[54] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0510,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[55] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_03c6,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[56] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0082,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_PCP |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[57] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_06bb,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[58] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_021d,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[59] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0641,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_PCP |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[60] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0512,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[61] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_03c8,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[62] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0084,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_PCP |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[63] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_06bd,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_VLAN_VID |\n+\t\tBNXT_ULP_ACT_BIT_PUSH_VLAN |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 4\n+\t},\n+\t[64] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_06d7,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[65] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_02c4,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[66] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_042a,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[67] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_06c4,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[68] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0417,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[69] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_06d9,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[70] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_02c6,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[71] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_042c,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[72] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_06c6,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[73] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0419,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[74] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0119,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[75] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_046f,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[76] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_05d5,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[77] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0106,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[78] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_05c2,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[79] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_011b,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[80] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0471,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[81] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_05d7,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[82] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_0108,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[83] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_05c4,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_IPV4_DST |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_SRC |\n+\t\tBNXT_ULP_ACT_BIT_SET_TP_DST |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 5\n+\t},\n+\t[84] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_00a2,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_VXLAN_ENCAP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 6\n+\t},\n+\t[85] = {\n+\t.act_hid = BNXT_ULP_ACT_HID_00a4,\n+\t.act_sig = { .bits =\n+\t\tBNXT_ULP_ACT_BIT_VXLAN_ENCAP |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.act_tid = 6\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\nindex 0d9531fa0f..c37829aea9 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Dec  7 09:51:03 2020 */\n+/* date: Wed Dec 16 16:37:41 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -16,1736 +16,80484 @@\n  * maps hash id to ulp_class_match_list[] index\n  */\n uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n-\t[BNXT_ULP_CLASS_HID_005c] = 1,\n-\t[BNXT_ULP_CLASS_HID_0003] = 2,\n-\t[BNXT_ULP_CLASS_HID_0132] = 3,\n-\t[BNXT_ULP_CLASS_HID_00e1] = 4,\n-\t[BNXT_ULP_CLASS_HID_0044] = 5,\n-\t[BNXT_ULP_CLASS_HID_001b] = 6,\n-\t[BNXT_ULP_CLASS_HID_012a] = 7,\n-\t[BNXT_ULP_CLASS_HID_00f9] = 8,\n-\t[BNXT_ULP_CLASS_HID_018d] = 9,\n-\t[BNXT_ULP_CLASS_HID_00a7] = 10,\n-\t[BNXT_ULP_CLASS_HID_006f] = 11,\n-\t[BNXT_ULP_CLASS_HID_0181] = 12,\n-\t[BNXT_ULP_CLASS_HID_0195] = 13,\n-\t[BNXT_ULP_CLASS_HID_00bf] = 14,\n-\t[BNXT_ULP_CLASS_HID_0077] = 15,\n-\t[BNXT_ULP_CLASS_HID_0199] = 16,\n-\t[BNXT_ULP_CLASS_HID_009a] = 17,\n-\t[BNXT_ULP_CLASS_HID_0192] = 18,\n-\t[BNXT_ULP_CLASS_HID_01e2] = 19,\n-\t[BNXT_ULP_CLASS_HID_00fa] = 20,\n-\t[BNXT_ULP_CLASS_HID_0165] = 21,\n-\t[BNXT_ULP_CLASS_HID_0042] = 22,\n-\t[BNXT_ULP_CLASS_HID_00cd] = 23,\n-\t[BNXT_ULP_CLASS_HID_01aa] = 24,\n-\t[BNXT_ULP_CLASS_HID_0178] = 25,\n-\t[BNXT_ULP_CLASS_HID_0070] = 26,\n-\t[BNXT_ULP_CLASS_HID_00f3] = 27,\n-\t[BNXT_ULP_CLASS_HID_01d8] = 28,\n-\t[BNXT_ULP_CLASS_HID_005b] = 29,\n-\t[BNXT_ULP_CLASS_HID_0153] = 30,\n-\t[BNXT_ULP_CLASS_HID_01a3] = 31,\n-\t[BNXT_ULP_CLASS_HID_00bb] = 32,\n-\t[BNXT_ULP_CLASS_HID_0082] = 33,\n-\t[BNXT_ULP_CLASS_HID_018a] = 34,\n-\t[BNXT_ULP_CLASS_HID_01fa] = 35,\n-\t[BNXT_ULP_CLASS_HID_00e2] = 36,\n-\t[BNXT_ULP_CLASS_HID_017d] = 37,\n-\t[BNXT_ULP_CLASS_HID_005a] = 38,\n-\t[BNXT_ULP_CLASS_HID_00d5] = 39,\n-\t[BNXT_ULP_CLASS_HID_01b2] = 40,\n-\t[BNXT_ULP_CLASS_HID_0160] = 41,\n-\t[BNXT_ULP_CLASS_HID_0068] = 42,\n-\t[BNXT_ULP_CLASS_HID_00eb] = 43,\n-\t[BNXT_ULP_CLASS_HID_01c0] = 44,\n-\t[BNXT_ULP_CLASS_HID_0043] = 45,\n-\t[BNXT_ULP_CLASS_HID_014b] = 46,\n-\t[BNXT_ULP_CLASS_HID_01bb] = 47,\n-\t[BNXT_ULP_CLASS_HID_00a3] = 48,\n-\t[BNXT_ULP_CLASS_HID_00cb] = 49,\n-\t[BNXT_ULP_CLASS_HID_00b4] = 50,\n-\t[BNXT_ULP_CLASS_HID_0013] = 51,\n-\t[BNXT_ULP_CLASS_HID_001c] = 52,\n-\t[BNXT_ULP_CLASS_HID_017b] = 53,\n-\t[BNXT_ULP_CLASS_HID_0164] = 54,\n-\t[BNXT_ULP_CLASS_HID_00c3] = 55,\n-\t[BNXT_ULP_CLASS_HID_00cc] = 56,\n-\t[BNXT_ULP_CLASS_HID_01a5] = 57,\n-\t[BNXT_ULP_CLASS_HID_0196] = 58,\n-\t[BNXT_ULP_CLASS_HID_010d] = 59,\n-\t[BNXT_ULP_CLASS_HID_00fe] = 60,\n-\t[BNXT_ULP_CLASS_HID_0084] = 61,\n-\t[BNXT_ULP_CLASS_HID_0046] = 62,\n-\t[BNXT_ULP_CLASS_HID_01ec] = 63,\n-\t[BNXT_ULP_CLASS_HID_01ae] = 64,\n-\t[BNXT_ULP_CLASS_HID_00d3] = 65,\n-\t[BNXT_ULP_CLASS_HID_00ac] = 66,\n-\t[BNXT_ULP_CLASS_HID_000b] = 67,\n-\t[BNXT_ULP_CLASS_HID_0004] = 68,\n-\t[BNXT_ULP_CLASS_HID_0163] = 69,\n-\t[BNXT_ULP_CLASS_HID_017c] = 70,\n-\t[BNXT_ULP_CLASS_HID_00db] = 71,\n-\t[BNXT_ULP_CLASS_HID_00d4] = 72,\n-\t[BNXT_ULP_CLASS_HID_01bd] = 73,\n-\t[BNXT_ULP_CLASS_HID_018e] = 74,\n-\t[BNXT_ULP_CLASS_HID_0115] = 75,\n-\t[BNXT_ULP_CLASS_HID_00e6] = 76,\n-\t[BNXT_ULP_CLASS_HID_009c] = 77,\n-\t[BNXT_ULP_CLASS_HID_005e] = 78,\n-\t[BNXT_ULP_CLASS_HID_01f4] = 79,\n-\t[BNXT_ULP_CLASS_HID_01b6] = 80\n+\t[BNXT_ULP_CLASS_HID_26d1] = 1,\n+\t[BNXT_ULP_CLASS_HID_0071] = 2,\n+\t[BNXT_ULP_CLASS_HID_53a5] = 3,\n+\t[BNXT_ULP_CLASS_HID_1d49] = 4,\n+\t[BNXT_ULP_CLASS_HID_2095] = 5,\n+\t[BNXT_ULP_CLASS_HID_5701] = 6,\n+\t[BNXT_ULP_CLASS_HID_4d79] = 7,\n+\t[BNXT_ULP_CLASS_HID_170d] = 8,\n+\t[BNXT_ULP_CLASS_HID_1a69] = 9,\n+\t[BNXT_ULP_CLASS_HID_50c5] = 10,\n+\t[BNXT_ULP_CLASS_HID_473d] = 11,\n+\t[BNXT_ULP_CLASS_HID_10c1] = 12,\n+\t[BNXT_ULP_CLASS_HID_142d] = 13,\n+\t[BNXT_ULP_CLASS_HID_4a99] = 14,\n+\t[BNXT_ULP_CLASS_HID_40f1] = 15,\n+\t[BNXT_ULP_CLASS_HID_0a85] = 16,\n+\t[BNXT_ULP_CLASS_HID_0179] = 17,\n+\t[BNXT_ULP_CLASS_HID_37d5] = 18,\n+\t[BNXT_ULP_CLASS_HID_2e4d] = 19,\n+\t[BNXT_ULP_CLASS_HID_54ad] = 20,\n+\t[BNXT_ULP_CLASS_HID_5809] = 21,\n+\t[BNXT_ULP_CLASS_HID_31a9] = 22,\n+\t[BNXT_ULP_CLASS_HID_2801] = 23,\n+\t[BNXT_ULP_CLASS_HID_4e61] = 24,\n+\t[BNXT_ULP_CLASS_HID_2561] = 25,\n+\t[BNXT_ULP_CLASS_HID_2bad] = 26,\n+\t[BNXT_ULP_CLASS_HID_26f1] = 27,\n+\t[BNXT_ULP_CLASS_HID_13cf1] = 28,\n+\t[BNXT_ULP_CLASS_HID_252f1] = 29,\n+\t[BNXT_ULP_CLASS_HID_30c25] = 30,\n+\t[BNXT_ULP_CLASS_HID_0051] = 31,\n+\t[BNXT_ULP_CLASS_HID_11651] = 32,\n+\t[BNXT_ULP_CLASS_HID_22c51] = 33,\n+\t[BNXT_ULP_CLASS_HID_34251] = 34,\n+\t[BNXT_ULP_CLASS_HID_5385] = 35,\n+\t[BNXT_ULP_CLASS_HID_10cc9] = 36,\n+\t[BNXT_ULP_CLASS_HID_222c9] = 37,\n+\t[BNXT_ULP_CLASS_HID_338c9] = 38,\n+\t[BNXT_ULP_CLASS_HID_1d69] = 39,\n+\t[BNXT_ULP_CLASS_HID_13369] = 40,\n+\t[BNXT_ULP_CLASS_HID_24969] = 41,\n+\t[BNXT_ULP_CLASS_HID_3025d] = 42,\n+\t[BNXT_ULP_CLASS_HID_20b5] = 43,\n+\t[BNXT_ULP_CLASS_HID_136b5] = 44,\n+\t[BNXT_ULP_CLASS_HID_24cb5] = 45,\n+\t[BNXT_ULP_CLASS_HID_305f9] = 46,\n+\t[BNXT_ULP_CLASS_HID_5721] = 47,\n+\t[BNXT_ULP_CLASS_HID_11015] = 48,\n+\t[BNXT_ULP_CLASS_HID_22615] = 49,\n+\t[BNXT_ULP_CLASS_HID_33c15] = 50,\n+\t[BNXT_ULP_CLASS_HID_4d59] = 51,\n+\t[BNXT_ULP_CLASS_HID_1068d] = 52,\n+\t[BNXT_ULP_CLASS_HID_21c8d] = 53,\n+\t[BNXT_ULP_CLASS_HID_3328d] = 54,\n+\t[BNXT_ULP_CLASS_HID_172d] = 55,\n+\t[BNXT_ULP_CLASS_HID_12d2d] = 56,\n+\t[BNXT_ULP_CLASS_HID_2432d] = 57,\n+\t[BNXT_ULP_CLASS_HID_3592d] = 58,\n+\t[BNXT_ULP_CLASS_HID_1a49] = 59,\n+\t[BNXT_ULP_CLASS_HID_13049] = 60,\n+\t[BNXT_ULP_CLASS_HID_24649] = 61,\n+\t[BNXT_ULP_CLASS_HID_35c49] = 62,\n+\t[BNXT_ULP_CLASS_HID_50e5] = 63,\n+\t[BNXT_ULP_CLASS_HID_10a29] = 64,\n+\t[BNXT_ULP_CLASS_HID_22029] = 65,\n+\t[BNXT_ULP_CLASS_HID_33629] = 66,\n+\t[BNXT_ULP_CLASS_HID_471d] = 67,\n+\t[BNXT_ULP_CLASS_HID_10041] = 68,\n+\t[BNXT_ULP_CLASS_HID_21641] = 69,\n+\t[BNXT_ULP_CLASS_HID_32c41] = 70,\n+\t[BNXT_ULP_CLASS_HID_10e1] = 71,\n+\t[BNXT_ULP_CLASS_HID_126e1] = 72,\n+\t[BNXT_ULP_CLASS_HID_23ce1] = 73,\n+\t[BNXT_ULP_CLASS_HID_352e1] = 74,\n+\t[BNXT_ULP_CLASS_HID_140d] = 75,\n+\t[BNXT_ULP_CLASS_HID_12a0d] = 76,\n+\t[BNXT_ULP_CLASS_HID_2400d] = 77,\n+\t[BNXT_ULP_CLASS_HID_3560d] = 78,\n+\t[BNXT_ULP_CLASS_HID_4ab9] = 79,\n+\t[BNXT_ULP_CLASS_HID_103ed] = 80,\n+\t[BNXT_ULP_CLASS_HID_219ed] = 81,\n+\t[BNXT_ULP_CLASS_HID_32fed] = 82,\n+\t[BNXT_ULP_CLASS_HID_40d1] = 83,\n+\t[BNXT_ULP_CLASS_HID_156d1] = 84,\n+\t[BNXT_ULP_CLASS_HID_21005] = 85,\n+\t[BNXT_ULP_CLASS_HID_32605] = 86,\n+\t[BNXT_ULP_CLASS_HID_0aa5] = 87,\n+\t[BNXT_ULP_CLASS_HID_120a5] = 88,\n+\t[BNXT_ULP_CLASS_HID_236a5] = 89,\n+\t[BNXT_ULP_CLASS_HID_34ca5] = 90,\n+\t[BNXT_ULP_CLASS_HID_0159] = 91,\n+\t[BNXT_ULP_CLASS_HID_11759] = 92,\n+\t[BNXT_ULP_CLASS_HID_22d59] = 93,\n+\t[BNXT_ULP_CLASS_HID_34359] = 94,\n+\t[BNXT_ULP_CLASS_HID_37f5] = 95,\n+\t[BNXT_ULP_CLASS_HID_14df5] = 96,\n+\t[BNXT_ULP_CLASS_HID_20739] = 97,\n+\t[BNXT_ULP_CLASS_HID_31d39] = 98,\n+\t[BNXT_ULP_CLASS_HID_2e6d] = 99,\n+\t[BNXT_ULP_CLASS_HID_1446d] = 100,\n+\t[BNXT_ULP_CLASS_HID_25a6d] = 101,\n+\t[BNXT_ULP_CLASS_HID_31351] = 102,\n+\t[BNXT_ULP_CLASS_HID_548d] = 103,\n+\t[BNXT_ULP_CLASS_HID_10df1] = 104,\n+\t[BNXT_ULP_CLASS_HID_223f1] = 105,\n+\t[BNXT_ULP_CLASS_HID_339f1] = 106,\n+\t[BNXT_ULP_CLASS_HID_5829] = 107,\n+\t[BNXT_ULP_CLASS_HID_1111d] = 108,\n+\t[BNXT_ULP_CLASS_HID_2271d] = 109,\n+\t[BNXT_ULP_CLASS_HID_33d1d] = 110,\n+\t[BNXT_ULP_CLASS_HID_3189] = 111,\n+\t[BNXT_ULP_CLASS_HID_14789] = 112,\n+\t[BNXT_ULP_CLASS_HID_200fd] = 113,\n+\t[BNXT_ULP_CLASS_HID_316fd] = 114,\n+\t[BNXT_ULP_CLASS_HID_2821] = 115,\n+\t[BNXT_ULP_CLASS_HID_13e21] = 116,\n+\t[BNXT_ULP_CLASS_HID_25421] = 117,\n+\t[BNXT_ULP_CLASS_HID_30d15] = 118,\n+\t[BNXT_ULP_CLASS_HID_4e41] = 119,\n+\t[BNXT_ULP_CLASS_HID_107b5] = 120,\n+\t[BNXT_ULP_CLASS_HID_21db5] = 121,\n+\t[BNXT_ULP_CLASS_HID_333b5] = 122,\n+\t[BNXT_ULP_CLASS_HID_2541] = 123,\n+\t[BNXT_ULP_CLASS_HID_2b8d] = 124,\n+\t[BNXT_ULP_CLASS_HID_2691] = 125,\n+\t[BNXT_ULP_CLASS_HID_13c91] = 126,\n+\t[BNXT_ULP_CLASS_HID_25291] = 127,\n+\t[BNXT_ULP_CLASS_HID_30c45] = 128,\n+\t[BNXT_ULP_CLASS_HID_0031] = 129,\n+\t[BNXT_ULP_CLASS_HID_11631] = 130,\n+\t[BNXT_ULP_CLASS_HID_22c31] = 131,\n+\t[BNXT_ULP_CLASS_HID_34231] = 132,\n+\t[BNXT_ULP_CLASS_HID_53e5] = 133,\n+\t[BNXT_ULP_CLASS_HID_10ca9] = 134,\n+\t[BNXT_ULP_CLASS_HID_222a9] = 135,\n+\t[BNXT_ULP_CLASS_HID_338a9] = 136,\n+\t[BNXT_ULP_CLASS_HID_1d09] = 137,\n+\t[BNXT_ULP_CLASS_HID_13309] = 138,\n+\t[BNXT_ULP_CLASS_HID_24909] = 139,\n+\t[BNXT_ULP_CLASS_HID_3023d] = 140,\n+\t[BNXT_ULP_CLASS_HID_20d5] = 141,\n+\t[BNXT_ULP_CLASS_HID_136d5] = 142,\n+\t[BNXT_ULP_CLASS_HID_24cd5] = 143,\n+\t[BNXT_ULP_CLASS_HID_30599] = 144,\n+\t[BNXT_ULP_CLASS_HID_5741] = 145,\n+\t[BNXT_ULP_CLASS_HID_11075] = 146,\n+\t[BNXT_ULP_CLASS_HID_22675] = 147,\n+\t[BNXT_ULP_CLASS_HID_33c75] = 148,\n+\t[BNXT_ULP_CLASS_HID_4d39] = 149,\n+\t[BNXT_ULP_CLASS_HID_106ed] = 150,\n+\t[BNXT_ULP_CLASS_HID_21ced] = 151,\n+\t[BNXT_ULP_CLASS_HID_332ed] = 152,\n+\t[BNXT_ULP_CLASS_HID_174d] = 153,\n+\t[BNXT_ULP_CLASS_HID_12d4d] = 154,\n+\t[BNXT_ULP_CLASS_HID_2434d] = 155,\n+\t[BNXT_ULP_CLASS_HID_3594d] = 156,\n+\t[BNXT_ULP_CLASS_HID_1a29] = 157,\n+\t[BNXT_ULP_CLASS_HID_13029] = 158,\n+\t[BNXT_ULP_CLASS_HID_24629] = 159,\n+\t[BNXT_ULP_CLASS_HID_35c29] = 160,\n+\t[BNXT_ULP_CLASS_HID_5085] = 161,\n+\t[BNXT_ULP_CLASS_HID_10a49] = 162,\n+\t[BNXT_ULP_CLASS_HID_22049] = 163,\n+\t[BNXT_ULP_CLASS_HID_33649] = 164,\n+\t[BNXT_ULP_CLASS_HID_477d] = 165,\n+\t[BNXT_ULP_CLASS_HID_10021] = 166,\n+\t[BNXT_ULP_CLASS_HID_21621] = 167,\n+\t[BNXT_ULP_CLASS_HID_32c21] = 168,\n+\t[BNXT_ULP_CLASS_HID_1081] = 169,\n+\t[BNXT_ULP_CLASS_HID_12681] = 170,\n+\t[BNXT_ULP_CLASS_HID_23c81] = 171,\n+\t[BNXT_ULP_CLASS_HID_35281] = 172,\n+\t[BNXT_ULP_CLASS_HID_146d] = 173,\n+\t[BNXT_ULP_CLASS_HID_12a6d] = 174,\n+\t[BNXT_ULP_CLASS_HID_2406d] = 175,\n+\t[BNXT_ULP_CLASS_HID_3566d] = 176,\n+\t[BNXT_ULP_CLASS_HID_4ad9] = 177,\n+\t[BNXT_ULP_CLASS_HID_1038d] = 178,\n+\t[BNXT_ULP_CLASS_HID_2198d] = 179,\n+\t[BNXT_ULP_CLASS_HID_32f8d] = 180,\n+\t[BNXT_ULP_CLASS_HID_40b1] = 181,\n+\t[BNXT_ULP_CLASS_HID_156b1] = 182,\n+\t[BNXT_ULP_CLASS_HID_21065] = 183,\n+\t[BNXT_ULP_CLASS_HID_32665] = 184,\n+\t[BNXT_ULP_CLASS_HID_0ac5] = 185,\n+\t[BNXT_ULP_CLASS_HID_120c5] = 186,\n+\t[BNXT_ULP_CLASS_HID_236c5] = 187,\n+\t[BNXT_ULP_CLASS_HID_34cc5] = 188,\n+\t[BNXT_ULP_CLASS_HID_0139] = 189,\n+\t[BNXT_ULP_CLASS_HID_11739] = 190,\n+\t[BNXT_ULP_CLASS_HID_22d39] = 191,\n+\t[BNXT_ULP_CLASS_HID_34339] = 192,\n+\t[BNXT_ULP_CLASS_HID_3795] = 193,\n+\t[BNXT_ULP_CLASS_HID_14d95] = 194,\n+\t[BNXT_ULP_CLASS_HID_20759] = 195,\n+\t[BNXT_ULP_CLASS_HID_31d59] = 196,\n+\t[BNXT_ULP_CLASS_HID_2e0d] = 197,\n+\t[BNXT_ULP_CLASS_HID_1440d] = 198,\n+\t[BNXT_ULP_CLASS_HID_25a0d] = 199,\n+\t[BNXT_ULP_CLASS_HID_31331] = 200,\n+\t[BNXT_ULP_CLASS_HID_54ed] = 201,\n+\t[BNXT_ULP_CLASS_HID_10d91] = 202,\n+\t[BNXT_ULP_CLASS_HID_22391] = 203,\n+\t[BNXT_ULP_CLASS_HID_33991] = 204,\n+\t[BNXT_ULP_CLASS_HID_5849] = 205,\n+\t[BNXT_ULP_CLASS_HID_1117d] = 206,\n+\t[BNXT_ULP_CLASS_HID_2277d] = 207,\n+\t[BNXT_ULP_CLASS_HID_33d7d] = 208,\n+\t[BNXT_ULP_CLASS_HID_31e9] = 209,\n+\t[BNXT_ULP_CLASS_HID_147e9] = 210,\n+\t[BNXT_ULP_CLASS_HID_2009d] = 211,\n+\t[BNXT_ULP_CLASS_HID_3169d] = 212,\n+\t[BNXT_ULP_CLASS_HID_2841] = 213,\n+\t[BNXT_ULP_CLASS_HID_13e41] = 214,\n+\t[BNXT_ULP_CLASS_HID_25441] = 215,\n+\t[BNXT_ULP_CLASS_HID_30d75] = 216,\n+\t[BNXT_ULP_CLASS_HID_4e21] = 217,\n+\t[BNXT_ULP_CLASS_HID_107d5] = 218,\n+\t[BNXT_ULP_CLASS_HID_21dd5] = 219,\n+\t[BNXT_ULP_CLASS_HID_333d5] = 220,\n+\t[BNXT_ULP_CLASS_HID_2521] = 221,\n+\t[BNXT_ULP_CLASS_HID_2bed] = 222,\n+\t[BNXT_ULP_CLASS_HID_1865] = 223,\n+\t[BNXT_ULP_CLASS_HID_389d] = 224,\n+\t[BNXT_ULP_CLASS_HID_123d] = 225,\n+\t[BNXT_ULP_CLASS_HID_4ef1] = 226,\n+\t[BNXT_ULP_CLASS_HID_1229] = 227,\n+\t[BNXT_ULP_CLASS_HID_3241] = 228,\n+\t[BNXT_ULP_CLASS_HID_0be1] = 229,\n+\t[BNXT_ULP_CLASS_HID_48b5] = 230,\n+\t[BNXT_ULP_CLASS_HID_0bed] = 231,\n+\t[BNXT_ULP_CLASS_HID_2c05] = 232,\n+\t[BNXT_ULP_CLASS_HID_05a5] = 233,\n+\t[BNXT_ULP_CLASS_HID_4279] = 234,\n+\t[BNXT_ULP_CLASS_HID_05d1] = 235,\n+\t[BNXT_ULP_CLASS_HID_25c9] = 236,\n+\t[BNXT_ULP_CLASS_HID_5c55] = 237,\n+\t[BNXT_ULP_CLASS_HID_3c3d] = 238,\n+\t[BNXT_ULP_CLASS_HID_4fc9] = 239,\n+\t[BNXT_ULP_CLASS_HID_1335] = 240,\n+\t[BNXT_ULP_CLASS_HID_4981] = 241,\n+\t[BNXT_ULP_CLASS_HID_2969] = 242,\n+\t[BNXT_ULP_CLASS_HID_498d] = 243,\n+\t[BNXT_ULP_CLASS_HID_0cf9] = 244,\n+\t[BNXT_ULP_CLASS_HID_4345] = 245,\n+\t[BNXT_ULP_CLASS_HID_232d] = 246,\n+\t[BNXT_ULP_CLASS_HID_2579] = 247,\n+\t[BNXT_ULP_CLASS_HID_2bb5] = 248,\n+\t[BNXT_ULP_CLASS_HID_1845] = 249,\n+\t[BNXT_ULP_CLASS_HID_1399] = 250,\n+\t[BNXT_ULP_CLASS_HID_0eed] = 251,\n+\t[BNXT_ULP_CLASS_HID_0a21] = 252,\n+\t[BNXT_ULP_CLASS_HID_38bd] = 253,\n+\t[BNXT_ULP_CLASS_HID_33f1] = 254,\n+\t[BNXT_ULP_CLASS_HID_2ec5] = 255,\n+\t[BNXT_ULP_CLASS_HID_2a19] = 256,\n+\t[BNXT_ULP_CLASS_HID_121d] = 257,\n+\t[BNXT_ULP_CLASS_HID_0d51] = 258,\n+\t[BNXT_ULP_CLASS_HID_08a5] = 259,\n+\t[BNXT_ULP_CLASS_HID_03f9] = 260,\n+\t[BNXT_ULP_CLASS_HID_4ed1] = 261,\n+\t[BNXT_ULP_CLASS_HID_4a25] = 262,\n+\t[BNXT_ULP_CLASS_HID_4579] = 263,\n+\t[BNXT_ULP_CLASS_HID_404d] = 264,\n+\t[BNXT_ULP_CLASS_HID_1209] = 265,\n+\t[BNXT_ULP_CLASS_HID_0d5d] = 266,\n+\t[BNXT_ULP_CLASS_HID_0891] = 267,\n+\t[BNXT_ULP_CLASS_HID_03e5] = 268,\n+\t[BNXT_ULP_CLASS_HID_3261] = 269,\n+\t[BNXT_ULP_CLASS_HID_2db5] = 270,\n+\t[BNXT_ULP_CLASS_HID_2889] = 271,\n+\t[BNXT_ULP_CLASS_HID_23dd] = 272,\n+\t[BNXT_ULP_CLASS_HID_0bc1] = 273,\n+\t[BNXT_ULP_CLASS_HID_0715] = 274,\n+\t[BNXT_ULP_CLASS_HID_0269] = 275,\n+\t[BNXT_ULP_CLASS_HID_5a69] = 276,\n+\t[BNXT_ULP_CLASS_HID_4895] = 277,\n+\t[BNXT_ULP_CLASS_HID_43e9] = 278,\n+\t[BNXT_ULP_CLASS_HID_3f3d] = 279,\n+\t[BNXT_ULP_CLASS_HID_3a71] = 280,\n+\t[BNXT_ULP_CLASS_HID_0bcd] = 281,\n+\t[BNXT_ULP_CLASS_HID_0701] = 282,\n+\t[BNXT_ULP_CLASS_HID_0255] = 283,\n+\t[BNXT_ULP_CLASS_HID_5a55] = 284,\n+\t[BNXT_ULP_CLASS_HID_2c25] = 285,\n+\t[BNXT_ULP_CLASS_HID_2779] = 286,\n+\t[BNXT_ULP_CLASS_HID_224d] = 287,\n+\t[BNXT_ULP_CLASS_HID_1d81] = 288,\n+\t[BNXT_ULP_CLASS_HID_0585] = 289,\n+\t[BNXT_ULP_CLASS_HID_00d9] = 290,\n+\t[BNXT_ULP_CLASS_HID_58d9] = 291,\n+\t[BNXT_ULP_CLASS_HID_542d] = 292,\n+\t[BNXT_ULP_CLASS_HID_4259] = 293,\n+\t[BNXT_ULP_CLASS_HID_3dad] = 294,\n+\t[BNXT_ULP_CLASS_HID_38e1] = 295,\n+\t[BNXT_ULP_CLASS_HID_3435] = 296,\n+\t[BNXT_ULP_CLASS_HID_05f1] = 297,\n+\t[BNXT_ULP_CLASS_HID_00c5] = 298,\n+\t[BNXT_ULP_CLASS_HID_58c5] = 299,\n+\t[BNXT_ULP_CLASS_HID_5419] = 300,\n+\t[BNXT_ULP_CLASS_HID_25e9] = 301,\n+\t[BNXT_ULP_CLASS_HID_213d] = 302,\n+\t[BNXT_ULP_CLASS_HID_1c71] = 303,\n+\t[BNXT_ULP_CLASS_HID_1745] = 304,\n+\t[BNXT_ULP_CLASS_HID_5c75] = 305,\n+\t[BNXT_ULP_CLASS_HID_5749] = 306,\n+\t[BNXT_ULP_CLASS_HID_529d] = 307,\n+\t[BNXT_ULP_CLASS_HID_4dd1] = 308,\n+\t[BNXT_ULP_CLASS_HID_3c1d] = 309,\n+\t[BNXT_ULP_CLASS_HID_3751] = 310,\n+\t[BNXT_ULP_CLASS_HID_32a5] = 311,\n+\t[BNXT_ULP_CLASS_HID_2df9] = 312,\n+\t[BNXT_ULP_CLASS_HID_4fe9] = 313,\n+\t[BNXT_ULP_CLASS_HID_4b3d] = 314,\n+\t[BNXT_ULP_CLASS_HID_4671] = 315,\n+\t[BNXT_ULP_CLASS_HID_4145] = 316,\n+\t[BNXT_ULP_CLASS_HID_1315] = 317,\n+\t[BNXT_ULP_CLASS_HID_0e69] = 318,\n+\t[BNXT_ULP_CLASS_HID_09bd] = 319,\n+\t[BNXT_ULP_CLASS_HID_04f1] = 320,\n+\t[BNXT_ULP_CLASS_HID_49a1] = 321,\n+\t[BNXT_ULP_CLASS_HID_44f5] = 322,\n+\t[BNXT_ULP_CLASS_HID_3fc9] = 323,\n+\t[BNXT_ULP_CLASS_HID_3b1d] = 324,\n+\t[BNXT_ULP_CLASS_HID_2949] = 325,\n+\t[BNXT_ULP_CLASS_HID_249d] = 326,\n+\t[BNXT_ULP_CLASS_HID_1fd1] = 327,\n+\t[BNXT_ULP_CLASS_HID_1b25] = 328,\n+\t[BNXT_ULP_CLASS_HID_49ad] = 329,\n+\t[BNXT_ULP_CLASS_HID_44e1] = 330,\n+\t[BNXT_ULP_CLASS_HID_4035] = 331,\n+\t[BNXT_ULP_CLASS_HID_3b09] = 332,\n+\t[BNXT_ULP_CLASS_HID_0cd9] = 333,\n+\t[BNXT_ULP_CLASS_HID_082d] = 334,\n+\t[BNXT_ULP_CLASS_HID_0361] = 335,\n+\t[BNXT_ULP_CLASS_HID_5b61] = 336,\n+\t[BNXT_ULP_CLASS_HID_4365] = 337,\n+\t[BNXT_ULP_CLASS_HID_3eb9] = 338,\n+\t[BNXT_ULP_CLASS_HID_398d] = 339,\n+\t[BNXT_ULP_CLASS_HID_34c1] = 340,\n+\t[BNXT_ULP_CLASS_HID_230d] = 341,\n+\t[BNXT_ULP_CLASS_HID_1e41] = 342,\n+\t[BNXT_ULP_CLASS_HID_1995] = 343,\n+\t[BNXT_ULP_CLASS_HID_14e9] = 344,\n+\t[BNXT_ULP_CLASS_HID_2559] = 345,\n+\t[BNXT_ULP_CLASS_HID_2b95] = 346,\n+\t[BNXT_ULP_CLASS_HID_1825] = 347,\n+\t[BNXT_ULP_CLASS_HID_13f9] = 348,\n+\t[BNXT_ULP_CLASS_HID_0e8d] = 349,\n+\t[BNXT_ULP_CLASS_HID_0a41] = 350,\n+\t[BNXT_ULP_CLASS_HID_38dd] = 351,\n+\t[BNXT_ULP_CLASS_HID_3391] = 352,\n+\t[BNXT_ULP_CLASS_HID_2ea5] = 353,\n+\t[BNXT_ULP_CLASS_HID_2a79] = 354,\n+\t[BNXT_ULP_CLASS_HID_127d] = 355,\n+\t[BNXT_ULP_CLASS_HID_0d31] = 356,\n+\t[BNXT_ULP_CLASS_HID_08c5] = 357,\n+\t[BNXT_ULP_CLASS_HID_0399] = 358,\n+\t[BNXT_ULP_CLASS_HID_4eb1] = 359,\n+\t[BNXT_ULP_CLASS_HID_4a45] = 360,\n+\t[BNXT_ULP_CLASS_HID_4519] = 361,\n+\t[BNXT_ULP_CLASS_HID_402d] = 362,\n+\t[BNXT_ULP_CLASS_HID_1269] = 363,\n+\t[BNXT_ULP_CLASS_HID_0d3d] = 364,\n+\t[BNXT_ULP_CLASS_HID_08f1] = 365,\n+\t[BNXT_ULP_CLASS_HID_0385] = 366,\n+\t[BNXT_ULP_CLASS_HID_3201] = 367,\n+\t[BNXT_ULP_CLASS_HID_2dd5] = 368,\n+\t[BNXT_ULP_CLASS_HID_28e9] = 369,\n+\t[BNXT_ULP_CLASS_HID_23bd] = 370,\n+\t[BNXT_ULP_CLASS_HID_0ba1] = 371,\n+\t[BNXT_ULP_CLASS_HID_0775] = 372,\n+\t[BNXT_ULP_CLASS_HID_0209] = 373,\n+\t[BNXT_ULP_CLASS_HID_5a09] = 374,\n+\t[BNXT_ULP_CLASS_HID_48f5] = 375,\n+\t[BNXT_ULP_CLASS_HID_4389] = 376,\n+\t[BNXT_ULP_CLASS_HID_3f5d] = 377,\n+\t[BNXT_ULP_CLASS_HID_3a11] = 378,\n+\t[BNXT_ULP_CLASS_HID_0bad] = 379,\n+\t[BNXT_ULP_CLASS_HID_0761] = 380,\n+\t[BNXT_ULP_CLASS_HID_0235] = 381,\n+\t[BNXT_ULP_CLASS_HID_5a35] = 382,\n+\t[BNXT_ULP_CLASS_HID_2c45] = 383,\n+\t[BNXT_ULP_CLASS_HID_2719] = 384,\n+\t[BNXT_ULP_CLASS_HID_222d] = 385,\n+\t[BNXT_ULP_CLASS_HID_1de1] = 386,\n+\t[BNXT_ULP_CLASS_HID_05e5] = 387,\n+\t[BNXT_ULP_CLASS_HID_00b9] = 388,\n+\t[BNXT_ULP_CLASS_HID_58b9] = 389,\n+\t[BNXT_ULP_CLASS_HID_544d] = 390,\n+\t[BNXT_ULP_CLASS_HID_4239] = 391,\n+\t[BNXT_ULP_CLASS_HID_3dcd] = 392,\n+\t[BNXT_ULP_CLASS_HID_3881] = 393,\n+\t[BNXT_ULP_CLASS_HID_3455] = 394,\n+\t[BNXT_ULP_CLASS_HID_0591] = 395,\n+\t[BNXT_ULP_CLASS_HID_00a5] = 396,\n+\t[BNXT_ULP_CLASS_HID_58a5] = 397,\n+\t[BNXT_ULP_CLASS_HID_5479] = 398,\n+\t[BNXT_ULP_CLASS_HID_2589] = 399,\n+\t[BNXT_ULP_CLASS_HID_215d] = 400,\n+\t[BNXT_ULP_CLASS_HID_1c11] = 401,\n+\t[BNXT_ULP_CLASS_HID_1725] = 402,\n+\t[BNXT_ULP_CLASS_HID_5c15] = 403,\n+\t[BNXT_ULP_CLASS_HID_5729] = 404,\n+\t[BNXT_ULP_CLASS_HID_52fd] = 405,\n+\t[BNXT_ULP_CLASS_HID_4db1] = 406,\n+\t[BNXT_ULP_CLASS_HID_3c7d] = 407,\n+\t[BNXT_ULP_CLASS_HID_3731] = 408,\n+\t[BNXT_ULP_CLASS_HID_32c5] = 409,\n+\t[BNXT_ULP_CLASS_HID_2d99] = 410,\n+\t[BNXT_ULP_CLASS_HID_4f89] = 411,\n+\t[BNXT_ULP_CLASS_HID_4b5d] = 412,\n+\t[BNXT_ULP_CLASS_HID_4611] = 413,\n+\t[BNXT_ULP_CLASS_HID_4125] = 414,\n+\t[BNXT_ULP_CLASS_HID_1375] = 415,\n+\t[BNXT_ULP_CLASS_HID_0e09] = 416,\n+\t[BNXT_ULP_CLASS_HID_09dd] = 417,\n+\t[BNXT_ULP_CLASS_HID_0491] = 418,\n+\t[BNXT_ULP_CLASS_HID_49c1] = 419,\n+\t[BNXT_ULP_CLASS_HID_4495] = 420,\n+\t[BNXT_ULP_CLASS_HID_3fa9] = 421,\n+\t[BNXT_ULP_CLASS_HID_3b7d] = 422,\n+\t[BNXT_ULP_CLASS_HID_2929] = 423,\n+\t[BNXT_ULP_CLASS_HID_24fd] = 424,\n+\t[BNXT_ULP_CLASS_HID_1fb1] = 425,\n+\t[BNXT_ULP_CLASS_HID_1b45] = 426,\n+\t[BNXT_ULP_CLASS_HID_49cd] = 427,\n+\t[BNXT_ULP_CLASS_HID_4481] = 428,\n+\t[BNXT_ULP_CLASS_HID_4055] = 429,\n+\t[BNXT_ULP_CLASS_HID_3b69] = 430,\n+\t[BNXT_ULP_CLASS_HID_0cb9] = 431,\n+\t[BNXT_ULP_CLASS_HID_084d] = 432,\n+\t[BNXT_ULP_CLASS_HID_0301] = 433,\n+\t[BNXT_ULP_CLASS_HID_5b01] = 434,\n+\t[BNXT_ULP_CLASS_HID_4305] = 435,\n+\t[BNXT_ULP_CLASS_HID_3ed9] = 436,\n+\t[BNXT_ULP_CLASS_HID_39ed] = 437,\n+\t[BNXT_ULP_CLASS_HID_34a1] = 438,\n+\t[BNXT_ULP_CLASS_HID_236d] = 439,\n+\t[BNXT_ULP_CLASS_HID_1e21] = 440,\n+\t[BNXT_ULP_CLASS_HID_19f5] = 441,\n+\t[BNXT_ULP_CLASS_HID_1489] = 442,\n+\t[BNXT_ULP_CLASS_HID_2539] = 443,\n+\t[BNXT_ULP_CLASS_HID_2bf5] = 444,\n+\t[BNXT_ULP_CLASS_HID_b6af] = 445,\n+\t[BNXT_ULP_CLASS_HID_b1d3] = 446,\n+\t[BNXT_ULP_CLASS_HID_1c7d3] = 447,\n+\t[BNXT_ULP_CLASS_HID_1ccaf] = 448,\n+\t[BNXT_ULP_CLASS_HID_da33] = 449,\n+\t[BNXT_ULP_CLASS_HID_d567] = 450,\n+\t[BNXT_ULP_CLASS_HID_18eab] = 451,\n+\t[BNXT_ULP_CLASS_HID_19367] = 452,\n+\t[BNXT_ULP_CLASS_HID_a10b] = 453,\n+\t[BNXT_ULP_CLASS_HID_9c3f] = 454,\n+\t[BNXT_ULP_CLASS_HID_1b23f] = 455,\n+\t[BNXT_ULP_CLASS_HID_1b70b] = 456,\n+\t[BNXT_ULP_CLASS_HID_c49f] = 457,\n+\t[BNXT_ULP_CLASS_HID_bfc3] = 458,\n+\t[BNXT_ULP_CLASS_HID_1d5c3] = 459,\n+\t[BNXT_ULP_CLASS_HID_1da9f] = 460,\n+\t[BNXT_ULP_CLASS_HID_b063] = 461,\n+\t[BNXT_ULP_CLASS_HID_ab97] = 462,\n+\t[BNXT_ULP_CLASS_HID_1c197] = 463,\n+\t[BNXT_ULP_CLASS_HID_1c663] = 464,\n+\t[BNXT_ULP_CLASS_HID_d3f7] = 465,\n+\t[BNXT_ULP_CLASS_HID_cf3b] = 466,\n+\t[BNXT_ULP_CLASS_HID_1886f] = 467,\n+\t[BNXT_ULP_CLASS_HID_18d3b] = 468,\n+\t[BNXT_ULP_CLASS_HID_9acf] = 469,\n+\t[BNXT_ULP_CLASS_HID_95f3] = 470,\n+\t[BNXT_ULP_CLASS_HID_1abf3] = 471,\n+\t[BNXT_ULP_CLASS_HID_1b0cf] = 472,\n+\t[BNXT_ULP_CLASS_HID_be53] = 473,\n+\t[BNXT_ULP_CLASS_HID_b987] = 474,\n+\t[BNXT_ULP_CLASS_HID_1cf87] = 475,\n+\t[BNXT_ULP_CLASS_HID_1d453] = 476,\n+\t[BNXT_ULP_CLASS_HID_aa27] = 477,\n+\t[BNXT_ULP_CLASS_HID_a56b] = 478,\n+\t[BNXT_ULP_CLASS_HID_1bb6b] = 479,\n+\t[BNXT_ULP_CLASS_HID_1c027] = 480,\n+\t[BNXT_ULP_CLASS_HID_cdcb] = 481,\n+\t[BNXT_ULP_CLASS_HID_c8ff] = 482,\n+\t[BNXT_ULP_CLASS_HID_18223] = 483,\n+\t[BNXT_ULP_CLASS_HID_186ff] = 484,\n+\t[BNXT_ULP_CLASS_HID_9483] = 485,\n+\t[BNXT_ULP_CLASS_HID_8fb7] = 486,\n+\t[BNXT_ULP_CLASS_HID_1a5b7] = 487,\n+\t[BNXT_ULP_CLASS_HID_1aa83] = 488,\n+\t[BNXT_ULP_CLASS_HID_b817] = 489,\n+\t[BNXT_ULP_CLASS_HID_b35b] = 490,\n+\t[BNXT_ULP_CLASS_HID_1c95b] = 491,\n+\t[BNXT_ULP_CLASS_HID_1ce17] = 492,\n+\t[BNXT_ULP_CLASS_HID_a3fb] = 493,\n+\t[BNXT_ULP_CLASS_HID_9f2f] = 494,\n+\t[BNXT_ULP_CLASS_HID_1b52f] = 495,\n+\t[BNXT_ULP_CLASS_HID_1b9fb] = 496,\n+\t[BNXT_ULP_CLASS_HID_c78f] = 497,\n+\t[BNXT_ULP_CLASS_HID_c2b3] = 498,\n+\t[BNXT_ULP_CLASS_HID_1d8b3] = 499,\n+\t[BNXT_ULP_CLASS_HID_180b3] = 500,\n+\t[BNXT_ULP_CLASS_HID_8e47] = 501,\n+\t[BNXT_ULP_CLASS_HID_898b] = 502,\n+\t[BNXT_ULP_CLASS_HID_19f8b] = 503,\n+\t[BNXT_ULP_CLASS_HID_1a447] = 504,\n+\t[BNXT_ULP_CLASS_HID_b1eb] = 505,\n+\t[BNXT_ULP_CLASS_HID_ad1f] = 506,\n+\t[BNXT_ULP_CLASS_HID_1c31f] = 507,\n+\t[BNXT_ULP_CLASS_HID_1c7eb] = 508,\n+\t[BNXT_ULP_CLASS_HID_9137] = 509,\n+\t[BNXT_ULP_CLASS_HID_8c7b] = 510,\n+\t[BNXT_ULP_CLASS_HID_1a27b] = 511,\n+\t[BNXT_ULP_CLASS_HID_1a737] = 512,\n+\t[BNXT_ULP_CLASS_HID_b4db] = 513,\n+\t[BNXT_ULP_CLASS_HID_b00f] = 514,\n+\t[BNXT_ULP_CLASS_HID_1c60f] = 515,\n+\t[BNXT_ULP_CLASS_HID_1cadb] = 516,\n+\t[BNXT_ULP_CLASS_HID_8b0b] = 517,\n+\t[BNXT_ULP_CLASS_HID_863f] = 518,\n+\t[BNXT_ULP_CLASS_HID_19c3f] = 519,\n+\t[BNXT_ULP_CLASS_HID_1a10b] = 520,\n+\t[BNXT_ULP_CLASS_HID_ae9f] = 521,\n+\t[BNXT_ULP_CLASS_HID_a9c3] = 522,\n+\t[BNXT_ULP_CLASS_HID_1bfc3] = 523,\n+\t[BNXT_ULP_CLASS_HID_1c49f] = 524,\n+\t[BNXT_ULP_CLASS_HID_2563] = 525,\n+\t[BNXT_ULP_CLASS_HID_2baf] = 526,\n+\t[BNXT_ULP_CLASS_HID_4f33] = 527,\n+\t[BNXT_ULP_CLASS_HID_160b] = 528,\n+\t[BNXT_ULP_CLASS_HID_399f] = 529,\n+\t[BNXT_ULP_CLASS_HID_48f7] = 530,\n+\t[BNXT_ULP_CLASS_HID_0fcf] = 531,\n+\t[BNXT_ULP_CLASS_HID_3353] = 532,\n+\t[BNXT_ULP_CLASS_HID_b68f] = 533,\n+\t[BNXT_ULP_CLASS_HID_b94f] = 534,\n+\t[BNXT_ULP_CLASS_HID_fc0f] = 535,\n+\t[BNXT_ULP_CLASS_HID_fecf] = 536,\n+\t[BNXT_ULP_CLASS_HID_b1f3] = 537,\n+\t[BNXT_ULP_CLASS_HID_b4b3] = 538,\n+\t[BNXT_ULP_CLASS_HID_f773] = 539,\n+\t[BNXT_ULP_CLASS_HID_fa33] = 540,\n+\t[BNXT_ULP_CLASS_HID_1c7f3] = 541,\n+\t[BNXT_ULP_CLASS_HID_1eab3] = 542,\n+\t[BNXT_ULP_CLASS_HID_1cd73] = 543,\n+\t[BNXT_ULP_CLASS_HID_1f033] = 544,\n+\t[BNXT_ULP_CLASS_HID_1cc8f] = 545,\n+\t[BNXT_ULP_CLASS_HID_1ef4f] = 546,\n+\t[BNXT_ULP_CLASS_HID_1d20f] = 547,\n+\t[BNXT_ULP_CLASS_HID_1f4cf] = 548,\n+\t[BNXT_ULP_CLASS_HID_da13] = 549,\n+\t[BNXT_ULP_CLASS_HID_a007] = 550,\n+\t[BNXT_ULP_CLASS_HID_c2c7] = 551,\n+\t[BNXT_ULP_CLASS_HID_e587] = 552,\n+\t[BNXT_ULP_CLASS_HID_d547] = 553,\n+\t[BNXT_ULP_CLASS_HID_f807] = 554,\n+\t[BNXT_ULP_CLASS_HID_dac7] = 555,\n+\t[BNXT_ULP_CLASS_HID_e0cb] = 556,\n+\t[BNXT_ULP_CLASS_HID_18e8b] = 557,\n+\t[BNXT_ULP_CLASS_HID_1b14b] = 558,\n+\t[BNXT_ULP_CLASS_HID_1d40b] = 559,\n+\t[BNXT_ULP_CLASS_HID_1f6cb] = 560,\n+\t[BNXT_ULP_CLASS_HID_19347] = 561,\n+\t[BNXT_ULP_CLASS_HID_1b607] = 562,\n+\t[BNXT_ULP_CLASS_HID_1d8c7] = 563,\n+\t[BNXT_ULP_CLASS_HID_1fb87] = 564,\n+\t[BNXT_ULP_CLASS_HID_a12b] = 565,\n+\t[BNXT_ULP_CLASS_HID_a3eb] = 566,\n+\t[BNXT_ULP_CLASS_HID_e6ab] = 567,\n+\t[BNXT_ULP_CLASS_HID_e96b] = 568,\n+\t[BNXT_ULP_CLASS_HID_9c1f] = 569,\n+\t[BNXT_ULP_CLASS_HID_bedf] = 570,\n+\t[BNXT_ULP_CLASS_HID_e19f] = 571,\n+\t[BNXT_ULP_CLASS_HID_e45f] = 572,\n+\t[BNXT_ULP_CLASS_HID_1b21f] = 573,\n+\t[BNXT_ULP_CLASS_HID_1b4df] = 574,\n+\t[BNXT_ULP_CLASS_HID_1f79f] = 575,\n+\t[BNXT_ULP_CLASS_HID_1fa5f] = 576,\n+\t[BNXT_ULP_CLASS_HID_1b72b] = 577,\n+\t[BNXT_ULP_CLASS_HID_1b9eb] = 578,\n+\t[BNXT_ULP_CLASS_HID_1fcab] = 579,\n+\t[BNXT_ULP_CLASS_HID_1ff6b] = 580,\n+\t[BNXT_ULP_CLASS_HID_c4bf] = 581,\n+\t[BNXT_ULP_CLASS_HID_e77f] = 582,\n+\t[BNXT_ULP_CLASS_HID_ca3f] = 583,\n+\t[BNXT_ULP_CLASS_HID_ecff] = 584,\n+\t[BNXT_ULP_CLASS_HID_bfe3] = 585,\n+\t[BNXT_ULP_CLASS_HID_e2a3] = 586,\n+\t[BNXT_ULP_CLASS_HID_c563] = 587,\n+\t[BNXT_ULP_CLASS_HID_e823] = 588,\n+\t[BNXT_ULP_CLASS_HID_1d5e3] = 589,\n+\t[BNXT_ULP_CLASS_HID_1f8a3] = 590,\n+\t[BNXT_ULP_CLASS_HID_1db63] = 591,\n+\t[BNXT_ULP_CLASS_HID_1e117] = 592,\n+\t[BNXT_ULP_CLASS_HID_1dabf] = 593,\n+\t[BNXT_ULP_CLASS_HID_1a0a3] = 594,\n+\t[BNXT_ULP_CLASS_HID_1c363] = 595,\n+\t[BNXT_ULP_CLASS_HID_1e623] = 596,\n+\t[BNXT_ULP_CLASS_HID_b043] = 597,\n+\t[BNXT_ULP_CLASS_HID_b303] = 598,\n+\t[BNXT_ULP_CLASS_HID_f5c3] = 599,\n+\t[BNXT_ULP_CLASS_HID_f883] = 600,\n+\t[BNXT_ULP_CLASS_HID_abb7] = 601,\n+\t[BNXT_ULP_CLASS_HID_ae77] = 602,\n+\t[BNXT_ULP_CLASS_HID_f137] = 603,\n+\t[BNXT_ULP_CLASS_HID_f3f7] = 604,\n+\t[BNXT_ULP_CLASS_HID_1c1b7] = 605,\n+\t[BNXT_ULP_CLASS_HID_1e477] = 606,\n+\t[BNXT_ULP_CLASS_HID_1c737] = 607,\n+\t[BNXT_ULP_CLASS_HID_1e9f7] = 608,\n+\t[BNXT_ULP_CLASS_HID_1c643] = 609,\n+\t[BNXT_ULP_CLASS_HID_1e903] = 610,\n+\t[BNXT_ULP_CLASS_HID_1cbc3] = 611,\n+\t[BNXT_ULP_CLASS_HID_1ee83] = 612,\n+\t[BNXT_ULP_CLASS_HID_d3d7] = 613,\n+\t[BNXT_ULP_CLASS_HID_f697] = 614,\n+\t[BNXT_ULP_CLASS_HID_d957] = 615,\n+\t[BNXT_ULP_CLASS_HID_fc17] = 616,\n+\t[BNXT_ULP_CLASS_HID_cf1b] = 617,\n+\t[BNXT_ULP_CLASS_HID_f1db] = 618,\n+\t[BNXT_ULP_CLASS_HID_d49b] = 619,\n+\t[BNXT_ULP_CLASS_HID_f75b] = 620,\n+\t[BNXT_ULP_CLASS_HID_1884f] = 621,\n+\t[BNXT_ULP_CLASS_HID_1ab0f] = 622,\n+\t[BNXT_ULP_CLASS_HID_1cdcf] = 623,\n+\t[BNXT_ULP_CLASS_HID_1f08f] = 624,\n+\t[BNXT_ULP_CLASS_HID_18d1b] = 625,\n+\t[BNXT_ULP_CLASS_HID_1afdb] = 626,\n+\t[BNXT_ULP_CLASS_HID_1d29b] = 627,\n+\t[BNXT_ULP_CLASS_HID_1f55b] = 628,\n+\t[BNXT_ULP_CLASS_HID_9aef] = 629,\n+\t[BNXT_ULP_CLASS_HID_bdaf] = 630,\n+\t[BNXT_ULP_CLASS_HID_e06f] = 631,\n+\t[BNXT_ULP_CLASS_HID_e32f] = 632,\n+\t[BNXT_ULP_CLASS_HID_95d3] = 633,\n+\t[BNXT_ULP_CLASS_HID_b893] = 634,\n+\t[BNXT_ULP_CLASS_HID_db53] = 635,\n+\t[BNXT_ULP_CLASS_HID_fe13] = 636,\n+\t[BNXT_ULP_CLASS_HID_1abd3] = 637,\n+\t[BNXT_ULP_CLASS_HID_1ae93] = 638,\n+\t[BNXT_ULP_CLASS_HID_1f153] = 639,\n+\t[BNXT_ULP_CLASS_HID_1f413] = 640,\n+\t[BNXT_ULP_CLASS_HID_1b0ef] = 641,\n+\t[BNXT_ULP_CLASS_HID_1b3af] = 642,\n+\t[BNXT_ULP_CLASS_HID_1f66f] = 643,\n+\t[BNXT_ULP_CLASS_HID_1f92f] = 644,\n+\t[BNXT_ULP_CLASS_HID_be73] = 645,\n+\t[BNXT_ULP_CLASS_HID_e133] = 646,\n+\t[BNXT_ULP_CLASS_HID_c3f3] = 647,\n+\t[BNXT_ULP_CLASS_HID_e6b3] = 648,\n+\t[BNXT_ULP_CLASS_HID_b9a7] = 649,\n+\t[BNXT_ULP_CLASS_HID_bc67] = 650,\n+\t[BNXT_ULP_CLASS_HID_ff27] = 651,\n+\t[BNXT_ULP_CLASS_HID_e1e7] = 652,\n+\t[BNXT_ULP_CLASS_HID_1cfa7] = 653,\n+\t[BNXT_ULP_CLASS_HID_1f267] = 654,\n+\t[BNXT_ULP_CLASS_HID_1d527] = 655,\n+\t[BNXT_ULP_CLASS_HID_1f7e7] = 656,\n+\t[BNXT_ULP_CLASS_HID_1d473] = 657,\n+\t[BNXT_ULP_CLASS_HID_1f733] = 658,\n+\t[BNXT_ULP_CLASS_HID_1d9f3] = 659,\n+\t[BNXT_ULP_CLASS_HID_1fcb3] = 660,\n+\t[BNXT_ULP_CLASS_HID_aa07] = 661,\n+\t[BNXT_ULP_CLASS_HID_acc7] = 662,\n+\t[BNXT_ULP_CLASS_HID_ef87] = 663,\n+\t[BNXT_ULP_CLASS_HID_f247] = 664,\n+\t[BNXT_ULP_CLASS_HID_a54b] = 665,\n+\t[BNXT_ULP_CLASS_HID_a80b] = 666,\n+\t[BNXT_ULP_CLASS_HID_eacb] = 667,\n+\t[BNXT_ULP_CLASS_HID_ed8b] = 668,\n+\t[BNXT_ULP_CLASS_HID_1bb4b] = 669,\n+\t[BNXT_ULP_CLASS_HID_1be0b] = 670,\n+\t[BNXT_ULP_CLASS_HID_1c0cb] = 671,\n+\t[BNXT_ULP_CLASS_HID_1e38b] = 672,\n+\t[BNXT_ULP_CLASS_HID_1c007] = 673,\n+\t[BNXT_ULP_CLASS_HID_1e2c7] = 674,\n+\t[BNXT_ULP_CLASS_HID_1c587] = 675,\n+\t[BNXT_ULP_CLASS_HID_1e847] = 676,\n+\t[BNXT_ULP_CLASS_HID_cdeb] = 677,\n+\t[BNXT_ULP_CLASS_HID_f0ab] = 678,\n+\t[BNXT_ULP_CLASS_HID_d36b] = 679,\n+\t[BNXT_ULP_CLASS_HID_f62b] = 680,\n+\t[BNXT_ULP_CLASS_HID_c8df] = 681,\n+\t[BNXT_ULP_CLASS_HID_eb9f] = 682,\n+\t[BNXT_ULP_CLASS_HID_ce5f] = 683,\n+\t[BNXT_ULP_CLASS_HID_f11f] = 684,\n+\t[BNXT_ULP_CLASS_HID_18203] = 685,\n+\t[BNXT_ULP_CLASS_HID_1a4c3] = 686,\n+\t[BNXT_ULP_CLASS_HID_1c783] = 687,\n+\t[BNXT_ULP_CLASS_HID_1ea43] = 688,\n+\t[BNXT_ULP_CLASS_HID_186df] = 689,\n+\t[BNXT_ULP_CLASS_HID_1a99f] = 690,\n+\t[BNXT_ULP_CLASS_HID_1cc5f] = 691,\n+\t[BNXT_ULP_CLASS_HID_1ef1f] = 692,\n+\t[BNXT_ULP_CLASS_HID_94a3] = 693,\n+\t[BNXT_ULP_CLASS_HID_b763] = 694,\n+\t[BNXT_ULP_CLASS_HID_da23] = 695,\n+\t[BNXT_ULP_CLASS_HID_fce3] = 696,\n+\t[BNXT_ULP_CLASS_HID_8f97] = 697,\n+\t[BNXT_ULP_CLASS_HID_b257] = 698,\n+\t[BNXT_ULP_CLASS_HID_d517] = 699,\n+\t[BNXT_ULP_CLASS_HID_f7d7] = 700,\n+\t[BNXT_ULP_CLASS_HID_1a597] = 701,\n+\t[BNXT_ULP_CLASS_HID_1a857] = 702,\n+\t[BNXT_ULP_CLASS_HID_1eb17] = 703,\n+\t[BNXT_ULP_CLASS_HID_1edd7] = 704,\n+\t[BNXT_ULP_CLASS_HID_1aaa3] = 705,\n+\t[BNXT_ULP_CLASS_HID_1ad63] = 706,\n+\t[BNXT_ULP_CLASS_HID_1f023] = 707,\n+\t[BNXT_ULP_CLASS_HID_1f2e3] = 708,\n+\t[BNXT_ULP_CLASS_HID_b837] = 709,\n+\t[BNXT_ULP_CLASS_HID_baf7] = 710,\n+\t[BNXT_ULP_CLASS_HID_fdb7] = 711,\n+\t[BNXT_ULP_CLASS_HID_e077] = 712,\n+\t[BNXT_ULP_CLASS_HID_b37b] = 713,\n+\t[BNXT_ULP_CLASS_HID_b63b] = 714,\n+\t[BNXT_ULP_CLASS_HID_f8fb] = 715,\n+\t[BNXT_ULP_CLASS_HID_fbbb] = 716,\n+\t[BNXT_ULP_CLASS_HID_1c97b] = 717,\n+\t[BNXT_ULP_CLASS_HID_1ec3b] = 718,\n+\t[BNXT_ULP_CLASS_HID_1cefb] = 719,\n+\t[BNXT_ULP_CLASS_HID_1f1bb] = 720,\n+\t[BNXT_ULP_CLASS_HID_1ce37] = 721,\n+\t[BNXT_ULP_CLASS_HID_1f0f7] = 722,\n+\t[BNXT_ULP_CLASS_HID_1d3b7] = 723,\n+\t[BNXT_ULP_CLASS_HID_1f677] = 724,\n+\t[BNXT_ULP_CLASS_HID_a3db] = 725,\n+\t[BNXT_ULP_CLASS_HID_a69b] = 726,\n+\t[BNXT_ULP_CLASS_HID_e95b] = 727,\n+\t[BNXT_ULP_CLASS_HID_ec1b] = 728,\n+\t[BNXT_ULP_CLASS_HID_9f0f] = 729,\n+\t[BNXT_ULP_CLASS_HID_a1cf] = 730,\n+\t[BNXT_ULP_CLASS_HID_e48f] = 731,\n+\t[BNXT_ULP_CLASS_HID_e74f] = 732,\n+\t[BNXT_ULP_CLASS_HID_1b50f] = 733,\n+\t[BNXT_ULP_CLASS_HID_1b7cf] = 734,\n+\t[BNXT_ULP_CLASS_HID_1fa8f] = 735,\n+\t[BNXT_ULP_CLASS_HID_1fd4f] = 736,\n+\t[BNXT_ULP_CLASS_HID_1b9db] = 737,\n+\t[BNXT_ULP_CLASS_HID_1bc9b] = 738,\n+\t[BNXT_ULP_CLASS_HID_1ff5b] = 739,\n+\t[BNXT_ULP_CLASS_HID_1e21b] = 740,\n+\t[BNXT_ULP_CLASS_HID_c7af] = 741,\n+\t[BNXT_ULP_CLASS_HID_ea6f] = 742,\n+\t[BNXT_ULP_CLASS_HID_cd2f] = 743,\n+\t[BNXT_ULP_CLASS_HID_efef] = 744,\n+\t[BNXT_ULP_CLASS_HID_c293] = 745,\n+\t[BNXT_ULP_CLASS_HID_e553] = 746,\n+\t[BNXT_ULP_CLASS_HID_c813] = 747,\n+\t[BNXT_ULP_CLASS_HID_ead3] = 748,\n+\t[BNXT_ULP_CLASS_HID_1d893] = 749,\n+\t[BNXT_ULP_CLASS_HID_1fb53] = 750,\n+\t[BNXT_ULP_CLASS_HID_1c147] = 751,\n+\t[BNXT_ULP_CLASS_HID_1e407] = 752,\n+\t[BNXT_ULP_CLASS_HID_18093] = 753,\n+\t[BNXT_ULP_CLASS_HID_1a353] = 754,\n+\t[BNXT_ULP_CLASS_HID_1c613] = 755,\n+\t[BNXT_ULP_CLASS_HID_1e8d3] = 756,\n+\t[BNXT_ULP_CLASS_HID_8e67] = 757,\n+\t[BNXT_ULP_CLASS_HID_b127] = 758,\n+\t[BNXT_ULP_CLASS_HID_d3e7] = 759,\n+\t[BNXT_ULP_CLASS_HID_f6a7] = 760,\n+\t[BNXT_ULP_CLASS_HID_89ab] = 761,\n+\t[BNXT_ULP_CLASS_HID_ac6b] = 762,\n+\t[BNXT_ULP_CLASS_HID_cf2b] = 763,\n+\t[BNXT_ULP_CLASS_HID_f1eb] = 764,\n+\t[BNXT_ULP_CLASS_HID_19fab] = 765,\n+\t[BNXT_ULP_CLASS_HID_1a26b] = 766,\n+\t[BNXT_ULP_CLASS_HID_1e52b] = 767,\n+\t[BNXT_ULP_CLASS_HID_1e7eb] = 768,\n+\t[BNXT_ULP_CLASS_HID_1a467] = 769,\n+\t[BNXT_ULP_CLASS_HID_1a727] = 770,\n+\t[BNXT_ULP_CLASS_HID_1e9e7] = 771,\n+\t[BNXT_ULP_CLASS_HID_1eca7] = 772,\n+\t[BNXT_ULP_CLASS_HID_b1cb] = 773,\n+\t[BNXT_ULP_CLASS_HID_b48b] = 774,\n+\t[BNXT_ULP_CLASS_HID_f74b] = 775,\n+\t[BNXT_ULP_CLASS_HID_fa0b] = 776,\n+\t[BNXT_ULP_CLASS_HID_ad3f] = 777,\n+\t[BNXT_ULP_CLASS_HID_afff] = 778,\n+\t[BNXT_ULP_CLASS_HID_f2bf] = 779,\n+\t[BNXT_ULP_CLASS_HID_f57f] = 780,\n+\t[BNXT_ULP_CLASS_HID_1c33f] = 781,\n+\t[BNXT_ULP_CLASS_HID_1e5ff] = 782,\n+\t[BNXT_ULP_CLASS_HID_1c8bf] = 783,\n+\t[BNXT_ULP_CLASS_HID_1eb7f] = 784,\n+\t[BNXT_ULP_CLASS_HID_1c7cb] = 785,\n+\t[BNXT_ULP_CLASS_HID_1ea8b] = 786,\n+\t[BNXT_ULP_CLASS_HID_1cd4b] = 787,\n+\t[BNXT_ULP_CLASS_HID_1f00b] = 788,\n+\t[BNXT_ULP_CLASS_HID_9117] = 789,\n+\t[BNXT_ULP_CLASS_HID_b3d7] = 790,\n+\t[BNXT_ULP_CLASS_HID_d697] = 791,\n+\t[BNXT_ULP_CLASS_HID_f957] = 792,\n+\t[BNXT_ULP_CLASS_HID_8c5b] = 793,\n+\t[BNXT_ULP_CLASS_HID_af1b] = 794,\n+\t[BNXT_ULP_CLASS_HID_d1db] = 795,\n+\t[BNXT_ULP_CLASS_HID_f49b] = 796,\n+\t[BNXT_ULP_CLASS_HID_1a25b] = 797,\n+\t[BNXT_ULP_CLASS_HID_1a51b] = 798,\n+\t[BNXT_ULP_CLASS_HID_1e7db] = 799,\n+\t[BNXT_ULP_CLASS_HID_1ea9b] = 800,\n+\t[BNXT_ULP_CLASS_HID_1a717] = 801,\n+\t[BNXT_ULP_CLASS_HID_1a9d7] = 802,\n+\t[BNXT_ULP_CLASS_HID_1ec97] = 803,\n+\t[BNXT_ULP_CLASS_HID_1ef57] = 804,\n+\t[BNXT_ULP_CLASS_HID_b4fb] = 805,\n+\t[BNXT_ULP_CLASS_HID_b7bb] = 806,\n+\t[BNXT_ULP_CLASS_HID_fa7b] = 807,\n+\t[BNXT_ULP_CLASS_HID_fd3b] = 808,\n+\t[BNXT_ULP_CLASS_HID_b02f] = 809,\n+\t[BNXT_ULP_CLASS_HID_b2ef] = 810,\n+\t[BNXT_ULP_CLASS_HID_f5af] = 811,\n+\t[BNXT_ULP_CLASS_HID_f86f] = 812,\n+\t[BNXT_ULP_CLASS_HID_1c62f] = 813,\n+\t[BNXT_ULP_CLASS_HID_1e8ef] = 814,\n+\t[BNXT_ULP_CLASS_HID_1cbaf] = 815,\n+\t[BNXT_ULP_CLASS_HID_1ee6f] = 816,\n+\t[BNXT_ULP_CLASS_HID_1cafb] = 817,\n+\t[BNXT_ULP_CLASS_HID_1edbb] = 818,\n+\t[BNXT_ULP_CLASS_HID_1d07b] = 819,\n+\t[BNXT_ULP_CLASS_HID_1f33b] = 820,\n+\t[BNXT_ULP_CLASS_HID_8b2b] = 821,\n+\t[BNXT_ULP_CLASS_HID_adeb] = 822,\n+\t[BNXT_ULP_CLASS_HID_d0ab] = 823,\n+\t[BNXT_ULP_CLASS_HID_f36b] = 824,\n+\t[BNXT_ULP_CLASS_HID_861f] = 825,\n+\t[BNXT_ULP_CLASS_HID_a8df] = 826,\n+\t[BNXT_ULP_CLASS_HID_cb9f] = 827,\n+\t[BNXT_ULP_CLASS_HID_ee5f] = 828,\n+\t[BNXT_ULP_CLASS_HID_19c1f] = 829,\n+\t[BNXT_ULP_CLASS_HID_1bedf] = 830,\n+\t[BNXT_ULP_CLASS_HID_1e19f] = 831,\n+\t[BNXT_ULP_CLASS_HID_1e45f] = 832,\n+\t[BNXT_ULP_CLASS_HID_1a12b] = 833,\n+\t[BNXT_ULP_CLASS_HID_1a3eb] = 834,\n+\t[BNXT_ULP_CLASS_HID_1e6ab] = 835,\n+\t[BNXT_ULP_CLASS_HID_1e96b] = 836,\n+\t[BNXT_ULP_CLASS_HID_aebf] = 837,\n+\t[BNXT_ULP_CLASS_HID_b17f] = 838,\n+\t[BNXT_ULP_CLASS_HID_f43f] = 839,\n+\t[BNXT_ULP_CLASS_HID_f6ff] = 840,\n+\t[BNXT_ULP_CLASS_HID_a9e3] = 841,\n+\t[BNXT_ULP_CLASS_HID_aca3] = 842,\n+\t[BNXT_ULP_CLASS_HID_ef63] = 843,\n+\t[BNXT_ULP_CLASS_HID_f223] = 844,\n+\t[BNXT_ULP_CLASS_HID_1bfe3] = 845,\n+\t[BNXT_ULP_CLASS_HID_1e2a3] = 846,\n+\t[BNXT_ULP_CLASS_HID_1c563] = 847,\n+\t[BNXT_ULP_CLASS_HID_1e823] = 848,\n+\t[BNXT_ULP_CLASS_HID_1c4bf] = 849,\n+\t[BNXT_ULP_CLASS_HID_1e77f] = 850,\n+\t[BNXT_ULP_CLASS_HID_1ca3f] = 851,\n+\t[BNXT_ULP_CLASS_HID_1ecff] = 852,\n+\t[BNXT_ULP_CLASS_HID_2543] = 853,\n+\t[BNXT_ULP_CLASS_HID_2b8f] = 854,\n+\t[BNXT_ULP_CLASS_HID_4f13] = 855,\n+\t[BNXT_ULP_CLASS_HID_162b] = 856,\n+\t[BNXT_ULP_CLASS_HID_39bf] = 857,\n+\t[BNXT_ULP_CLASS_HID_48d7] = 858,\n+\t[BNXT_ULP_CLASS_HID_0fef] = 859,\n+\t[BNXT_ULP_CLASS_HID_3373] = 860,\n+\t[BNXT_ULP_CLASS_HID_b6ef] = 861,\n+\t[BNXT_ULP_CLASS_HID_b92f] = 862,\n+\t[BNXT_ULP_CLASS_HID_fc6f] = 863,\n+\t[BNXT_ULP_CLASS_HID_feaf] = 864,\n+\t[BNXT_ULP_CLASS_HID_b193] = 865,\n+\t[BNXT_ULP_CLASS_HID_b4d3] = 866,\n+\t[BNXT_ULP_CLASS_HID_f713] = 867,\n+\t[BNXT_ULP_CLASS_HID_fa53] = 868,\n+\t[BNXT_ULP_CLASS_HID_1c793] = 869,\n+\t[BNXT_ULP_CLASS_HID_1ead3] = 870,\n+\t[BNXT_ULP_CLASS_HID_1cd13] = 871,\n+\t[BNXT_ULP_CLASS_HID_1f053] = 872,\n+\t[BNXT_ULP_CLASS_HID_1ccef] = 873,\n+\t[BNXT_ULP_CLASS_HID_1ef2f] = 874,\n+\t[BNXT_ULP_CLASS_HID_1d26f] = 875,\n+\t[BNXT_ULP_CLASS_HID_1f4af] = 876,\n+\t[BNXT_ULP_CLASS_HID_da73] = 877,\n+\t[BNXT_ULP_CLASS_HID_a067] = 878,\n+\t[BNXT_ULP_CLASS_HID_c2a7] = 879,\n+\t[BNXT_ULP_CLASS_HID_e5e7] = 880,\n+\t[BNXT_ULP_CLASS_HID_d527] = 881,\n+\t[BNXT_ULP_CLASS_HID_f867] = 882,\n+\t[BNXT_ULP_CLASS_HID_daa7] = 883,\n+\t[BNXT_ULP_CLASS_HID_e0ab] = 884,\n+\t[BNXT_ULP_CLASS_HID_18eeb] = 885,\n+\t[BNXT_ULP_CLASS_HID_1b12b] = 886,\n+\t[BNXT_ULP_CLASS_HID_1d46b] = 887,\n+\t[BNXT_ULP_CLASS_HID_1f6ab] = 888,\n+\t[BNXT_ULP_CLASS_HID_19327] = 889,\n+\t[BNXT_ULP_CLASS_HID_1b667] = 890,\n+\t[BNXT_ULP_CLASS_HID_1d8a7] = 891,\n+\t[BNXT_ULP_CLASS_HID_1fbe7] = 892,\n+\t[BNXT_ULP_CLASS_HID_a14b] = 893,\n+\t[BNXT_ULP_CLASS_HID_a38b] = 894,\n+\t[BNXT_ULP_CLASS_HID_e6cb] = 895,\n+\t[BNXT_ULP_CLASS_HID_e90b] = 896,\n+\t[BNXT_ULP_CLASS_HID_9c7f] = 897,\n+\t[BNXT_ULP_CLASS_HID_bebf] = 898,\n+\t[BNXT_ULP_CLASS_HID_e1ff] = 899,\n+\t[BNXT_ULP_CLASS_HID_e43f] = 900,\n+\t[BNXT_ULP_CLASS_HID_1b27f] = 901,\n+\t[BNXT_ULP_CLASS_HID_1b4bf] = 902,\n+\t[BNXT_ULP_CLASS_HID_1f7ff] = 903,\n+\t[BNXT_ULP_CLASS_HID_1fa3f] = 904,\n+\t[BNXT_ULP_CLASS_HID_1b74b] = 905,\n+\t[BNXT_ULP_CLASS_HID_1b98b] = 906,\n+\t[BNXT_ULP_CLASS_HID_1fccb] = 907,\n+\t[BNXT_ULP_CLASS_HID_1ff0b] = 908,\n+\t[BNXT_ULP_CLASS_HID_c4df] = 909,\n+\t[BNXT_ULP_CLASS_HID_e71f] = 910,\n+\t[BNXT_ULP_CLASS_HID_ca5f] = 911,\n+\t[BNXT_ULP_CLASS_HID_ec9f] = 912,\n+\t[BNXT_ULP_CLASS_HID_bf83] = 913,\n+\t[BNXT_ULP_CLASS_HID_e2c3] = 914,\n+\t[BNXT_ULP_CLASS_HID_c503] = 915,\n+\t[BNXT_ULP_CLASS_HID_e843] = 916,\n+\t[BNXT_ULP_CLASS_HID_1d583] = 917,\n+\t[BNXT_ULP_CLASS_HID_1f8c3] = 918,\n+\t[BNXT_ULP_CLASS_HID_1db03] = 919,\n+\t[BNXT_ULP_CLASS_HID_1e177] = 920,\n+\t[BNXT_ULP_CLASS_HID_1dadf] = 921,\n+\t[BNXT_ULP_CLASS_HID_1a0c3] = 922,\n+\t[BNXT_ULP_CLASS_HID_1c303] = 923,\n+\t[BNXT_ULP_CLASS_HID_1e643] = 924,\n+\t[BNXT_ULP_CLASS_HID_b023] = 925,\n+\t[BNXT_ULP_CLASS_HID_b363] = 926,\n+\t[BNXT_ULP_CLASS_HID_f5a3] = 927,\n+\t[BNXT_ULP_CLASS_HID_f8e3] = 928,\n+\t[BNXT_ULP_CLASS_HID_abd7] = 929,\n+\t[BNXT_ULP_CLASS_HID_ae17] = 930,\n+\t[BNXT_ULP_CLASS_HID_f157] = 931,\n+\t[BNXT_ULP_CLASS_HID_f397] = 932,\n+\t[BNXT_ULP_CLASS_HID_1c1d7] = 933,\n+\t[BNXT_ULP_CLASS_HID_1e417] = 934,\n+\t[BNXT_ULP_CLASS_HID_1c757] = 935,\n+\t[BNXT_ULP_CLASS_HID_1e997] = 936,\n+\t[BNXT_ULP_CLASS_HID_1c623] = 937,\n+\t[BNXT_ULP_CLASS_HID_1e963] = 938,\n+\t[BNXT_ULP_CLASS_HID_1cba3] = 939,\n+\t[BNXT_ULP_CLASS_HID_1eee3] = 940,\n+\t[BNXT_ULP_CLASS_HID_d3b7] = 941,\n+\t[BNXT_ULP_CLASS_HID_f6f7] = 942,\n+\t[BNXT_ULP_CLASS_HID_d937] = 943,\n+\t[BNXT_ULP_CLASS_HID_fc77] = 944,\n+\t[BNXT_ULP_CLASS_HID_cf7b] = 945,\n+\t[BNXT_ULP_CLASS_HID_f1bb] = 946,\n+\t[BNXT_ULP_CLASS_HID_d4fb] = 947,\n+\t[BNXT_ULP_CLASS_HID_f73b] = 948,\n+\t[BNXT_ULP_CLASS_HID_1882f] = 949,\n+\t[BNXT_ULP_CLASS_HID_1ab6f] = 950,\n+\t[BNXT_ULP_CLASS_HID_1cdaf] = 951,\n+\t[BNXT_ULP_CLASS_HID_1f0ef] = 952,\n+\t[BNXT_ULP_CLASS_HID_18d7b] = 953,\n+\t[BNXT_ULP_CLASS_HID_1afbb] = 954,\n+\t[BNXT_ULP_CLASS_HID_1d2fb] = 955,\n+\t[BNXT_ULP_CLASS_HID_1f53b] = 956,\n+\t[BNXT_ULP_CLASS_HID_9a8f] = 957,\n+\t[BNXT_ULP_CLASS_HID_bdcf] = 958,\n+\t[BNXT_ULP_CLASS_HID_e00f] = 959,\n+\t[BNXT_ULP_CLASS_HID_e34f] = 960,\n+\t[BNXT_ULP_CLASS_HID_95b3] = 961,\n+\t[BNXT_ULP_CLASS_HID_b8f3] = 962,\n+\t[BNXT_ULP_CLASS_HID_db33] = 963,\n+\t[BNXT_ULP_CLASS_HID_fe73] = 964,\n+\t[BNXT_ULP_CLASS_HID_1abb3] = 965,\n+\t[BNXT_ULP_CLASS_HID_1aef3] = 966,\n+\t[BNXT_ULP_CLASS_HID_1f133] = 967,\n+\t[BNXT_ULP_CLASS_HID_1f473] = 968,\n+\t[BNXT_ULP_CLASS_HID_1b08f] = 969,\n+\t[BNXT_ULP_CLASS_HID_1b3cf] = 970,\n+\t[BNXT_ULP_CLASS_HID_1f60f] = 971,\n+\t[BNXT_ULP_CLASS_HID_1f94f] = 972,\n+\t[BNXT_ULP_CLASS_HID_be13] = 973,\n+\t[BNXT_ULP_CLASS_HID_e153] = 974,\n+\t[BNXT_ULP_CLASS_HID_c393] = 975,\n+\t[BNXT_ULP_CLASS_HID_e6d3] = 976,\n+\t[BNXT_ULP_CLASS_HID_b9c7] = 977,\n+\t[BNXT_ULP_CLASS_HID_bc07] = 978,\n+\t[BNXT_ULP_CLASS_HID_ff47] = 979,\n+\t[BNXT_ULP_CLASS_HID_e187] = 980,\n+\t[BNXT_ULP_CLASS_HID_1cfc7] = 981,\n+\t[BNXT_ULP_CLASS_HID_1f207] = 982,\n+\t[BNXT_ULP_CLASS_HID_1d547] = 983,\n+\t[BNXT_ULP_CLASS_HID_1f787] = 984,\n+\t[BNXT_ULP_CLASS_HID_1d413] = 985,\n+\t[BNXT_ULP_CLASS_HID_1f753] = 986,\n+\t[BNXT_ULP_CLASS_HID_1d993] = 987,\n+\t[BNXT_ULP_CLASS_HID_1fcd3] = 988,\n+\t[BNXT_ULP_CLASS_HID_aa67] = 989,\n+\t[BNXT_ULP_CLASS_HID_aca7] = 990,\n+\t[BNXT_ULP_CLASS_HID_efe7] = 991,\n+\t[BNXT_ULP_CLASS_HID_f227] = 992,\n+\t[BNXT_ULP_CLASS_HID_a52b] = 993,\n+\t[BNXT_ULP_CLASS_HID_a86b] = 994,\n+\t[BNXT_ULP_CLASS_HID_eaab] = 995,\n+\t[BNXT_ULP_CLASS_HID_edeb] = 996,\n+\t[BNXT_ULP_CLASS_HID_1bb2b] = 997,\n+\t[BNXT_ULP_CLASS_HID_1be6b] = 998,\n+\t[BNXT_ULP_CLASS_HID_1c0ab] = 999,\n+\t[BNXT_ULP_CLASS_HID_1e3eb] = 1000,\n+\t[BNXT_ULP_CLASS_HID_1c067] = 1001,\n+\t[BNXT_ULP_CLASS_HID_1e2a7] = 1002,\n+\t[BNXT_ULP_CLASS_HID_1c5e7] = 1003,\n+\t[BNXT_ULP_CLASS_HID_1e827] = 1004,\n+\t[BNXT_ULP_CLASS_HID_cd8b] = 1005,\n+\t[BNXT_ULP_CLASS_HID_f0cb] = 1006,\n+\t[BNXT_ULP_CLASS_HID_d30b] = 1007,\n+\t[BNXT_ULP_CLASS_HID_f64b] = 1008,\n+\t[BNXT_ULP_CLASS_HID_c8bf] = 1009,\n+\t[BNXT_ULP_CLASS_HID_ebff] = 1010,\n+\t[BNXT_ULP_CLASS_HID_ce3f] = 1011,\n+\t[BNXT_ULP_CLASS_HID_f17f] = 1012,\n+\t[BNXT_ULP_CLASS_HID_18263] = 1013,\n+\t[BNXT_ULP_CLASS_HID_1a4a3] = 1014,\n+\t[BNXT_ULP_CLASS_HID_1c7e3] = 1015,\n+\t[BNXT_ULP_CLASS_HID_1ea23] = 1016,\n+\t[BNXT_ULP_CLASS_HID_186bf] = 1017,\n+\t[BNXT_ULP_CLASS_HID_1a9ff] = 1018,\n+\t[BNXT_ULP_CLASS_HID_1cc3f] = 1019,\n+\t[BNXT_ULP_CLASS_HID_1ef7f] = 1020,\n+\t[BNXT_ULP_CLASS_HID_94c3] = 1021,\n+\t[BNXT_ULP_CLASS_HID_b703] = 1022,\n+\t[BNXT_ULP_CLASS_HID_da43] = 1023,\n+\t[BNXT_ULP_CLASS_HID_fc83] = 1024,\n+\t[BNXT_ULP_CLASS_HID_8ff7] = 1025,\n+\t[BNXT_ULP_CLASS_HID_b237] = 1026,\n+\t[BNXT_ULP_CLASS_HID_d577] = 1027,\n+\t[BNXT_ULP_CLASS_HID_f7b7] = 1028,\n+\t[BNXT_ULP_CLASS_HID_1a5f7] = 1029,\n+\t[BNXT_ULP_CLASS_HID_1a837] = 1030,\n+\t[BNXT_ULP_CLASS_HID_1eb77] = 1031,\n+\t[BNXT_ULP_CLASS_HID_1edb7] = 1032,\n+\t[BNXT_ULP_CLASS_HID_1aac3] = 1033,\n+\t[BNXT_ULP_CLASS_HID_1ad03] = 1034,\n+\t[BNXT_ULP_CLASS_HID_1f043] = 1035,\n+\t[BNXT_ULP_CLASS_HID_1f283] = 1036,\n+\t[BNXT_ULP_CLASS_HID_b857] = 1037,\n+\t[BNXT_ULP_CLASS_HID_ba97] = 1038,\n+\t[BNXT_ULP_CLASS_HID_fdd7] = 1039,\n+\t[BNXT_ULP_CLASS_HID_e017] = 1040,\n+\t[BNXT_ULP_CLASS_HID_b31b] = 1041,\n+\t[BNXT_ULP_CLASS_HID_b65b] = 1042,\n+\t[BNXT_ULP_CLASS_HID_f89b] = 1043,\n+\t[BNXT_ULP_CLASS_HID_fbdb] = 1044,\n+\t[BNXT_ULP_CLASS_HID_1c91b] = 1045,\n+\t[BNXT_ULP_CLASS_HID_1ec5b] = 1046,\n+\t[BNXT_ULP_CLASS_HID_1ce9b] = 1047,\n+\t[BNXT_ULP_CLASS_HID_1f1db] = 1048,\n+\t[BNXT_ULP_CLASS_HID_1ce57] = 1049,\n+\t[BNXT_ULP_CLASS_HID_1f097] = 1050,\n+\t[BNXT_ULP_CLASS_HID_1d3d7] = 1051,\n+\t[BNXT_ULP_CLASS_HID_1f617] = 1052,\n+\t[BNXT_ULP_CLASS_HID_a3bb] = 1053,\n+\t[BNXT_ULP_CLASS_HID_a6fb] = 1054,\n+\t[BNXT_ULP_CLASS_HID_e93b] = 1055,\n+\t[BNXT_ULP_CLASS_HID_ec7b] = 1056,\n+\t[BNXT_ULP_CLASS_HID_9f6f] = 1057,\n+\t[BNXT_ULP_CLASS_HID_a1af] = 1058,\n+\t[BNXT_ULP_CLASS_HID_e4ef] = 1059,\n+\t[BNXT_ULP_CLASS_HID_e72f] = 1060,\n+\t[BNXT_ULP_CLASS_HID_1b56f] = 1061,\n+\t[BNXT_ULP_CLASS_HID_1b7af] = 1062,\n+\t[BNXT_ULP_CLASS_HID_1faef] = 1063,\n+\t[BNXT_ULP_CLASS_HID_1fd2f] = 1064,\n+\t[BNXT_ULP_CLASS_HID_1b9bb] = 1065,\n+\t[BNXT_ULP_CLASS_HID_1bcfb] = 1066,\n+\t[BNXT_ULP_CLASS_HID_1ff3b] = 1067,\n+\t[BNXT_ULP_CLASS_HID_1e27b] = 1068,\n+\t[BNXT_ULP_CLASS_HID_c7cf] = 1069,\n+\t[BNXT_ULP_CLASS_HID_ea0f] = 1070,\n+\t[BNXT_ULP_CLASS_HID_cd4f] = 1071,\n+\t[BNXT_ULP_CLASS_HID_ef8f] = 1072,\n+\t[BNXT_ULP_CLASS_HID_c2f3] = 1073,\n+\t[BNXT_ULP_CLASS_HID_e533] = 1074,\n+\t[BNXT_ULP_CLASS_HID_c873] = 1075,\n+\t[BNXT_ULP_CLASS_HID_eab3] = 1076,\n+\t[BNXT_ULP_CLASS_HID_1d8f3] = 1077,\n+\t[BNXT_ULP_CLASS_HID_1fb33] = 1078,\n+\t[BNXT_ULP_CLASS_HID_1c127] = 1079,\n+\t[BNXT_ULP_CLASS_HID_1e467] = 1080,\n+\t[BNXT_ULP_CLASS_HID_180f3] = 1081,\n+\t[BNXT_ULP_CLASS_HID_1a333] = 1082,\n+\t[BNXT_ULP_CLASS_HID_1c673] = 1083,\n+\t[BNXT_ULP_CLASS_HID_1e8b3] = 1084,\n+\t[BNXT_ULP_CLASS_HID_8e07] = 1085,\n+\t[BNXT_ULP_CLASS_HID_b147] = 1086,\n+\t[BNXT_ULP_CLASS_HID_d387] = 1087,\n+\t[BNXT_ULP_CLASS_HID_f6c7] = 1088,\n+\t[BNXT_ULP_CLASS_HID_89cb] = 1089,\n+\t[BNXT_ULP_CLASS_HID_ac0b] = 1090,\n+\t[BNXT_ULP_CLASS_HID_cf4b] = 1091,\n+\t[BNXT_ULP_CLASS_HID_f18b] = 1092,\n+\t[BNXT_ULP_CLASS_HID_19fcb] = 1093,\n+\t[BNXT_ULP_CLASS_HID_1a20b] = 1094,\n+\t[BNXT_ULP_CLASS_HID_1e54b] = 1095,\n+\t[BNXT_ULP_CLASS_HID_1e78b] = 1096,\n+\t[BNXT_ULP_CLASS_HID_1a407] = 1097,\n+\t[BNXT_ULP_CLASS_HID_1a747] = 1098,\n+\t[BNXT_ULP_CLASS_HID_1e987] = 1099,\n+\t[BNXT_ULP_CLASS_HID_1ecc7] = 1100,\n+\t[BNXT_ULP_CLASS_HID_b1ab] = 1101,\n+\t[BNXT_ULP_CLASS_HID_b4eb] = 1102,\n+\t[BNXT_ULP_CLASS_HID_f72b] = 1103,\n+\t[BNXT_ULP_CLASS_HID_fa6b] = 1104,\n+\t[BNXT_ULP_CLASS_HID_ad5f] = 1105,\n+\t[BNXT_ULP_CLASS_HID_af9f] = 1106,\n+\t[BNXT_ULP_CLASS_HID_f2df] = 1107,\n+\t[BNXT_ULP_CLASS_HID_f51f] = 1108,\n+\t[BNXT_ULP_CLASS_HID_1c35f] = 1109,\n+\t[BNXT_ULP_CLASS_HID_1e59f] = 1110,\n+\t[BNXT_ULP_CLASS_HID_1c8df] = 1111,\n+\t[BNXT_ULP_CLASS_HID_1eb1f] = 1112,\n+\t[BNXT_ULP_CLASS_HID_1c7ab] = 1113,\n+\t[BNXT_ULP_CLASS_HID_1eaeb] = 1114,\n+\t[BNXT_ULP_CLASS_HID_1cd2b] = 1115,\n+\t[BNXT_ULP_CLASS_HID_1f06b] = 1116,\n+\t[BNXT_ULP_CLASS_HID_9177] = 1117,\n+\t[BNXT_ULP_CLASS_HID_b3b7] = 1118,\n+\t[BNXT_ULP_CLASS_HID_d6f7] = 1119,\n+\t[BNXT_ULP_CLASS_HID_f937] = 1120,\n+\t[BNXT_ULP_CLASS_HID_8c3b] = 1121,\n+\t[BNXT_ULP_CLASS_HID_af7b] = 1122,\n+\t[BNXT_ULP_CLASS_HID_d1bb] = 1123,\n+\t[BNXT_ULP_CLASS_HID_f4fb] = 1124,\n+\t[BNXT_ULP_CLASS_HID_1a23b] = 1125,\n+\t[BNXT_ULP_CLASS_HID_1a57b] = 1126,\n+\t[BNXT_ULP_CLASS_HID_1e7bb] = 1127,\n+\t[BNXT_ULP_CLASS_HID_1eafb] = 1128,\n+\t[BNXT_ULP_CLASS_HID_1a777] = 1129,\n+\t[BNXT_ULP_CLASS_HID_1a9b7] = 1130,\n+\t[BNXT_ULP_CLASS_HID_1ecf7] = 1131,\n+\t[BNXT_ULP_CLASS_HID_1ef37] = 1132,\n+\t[BNXT_ULP_CLASS_HID_b49b] = 1133,\n+\t[BNXT_ULP_CLASS_HID_b7db] = 1134,\n+\t[BNXT_ULP_CLASS_HID_fa1b] = 1135,\n+\t[BNXT_ULP_CLASS_HID_fd5b] = 1136,\n+\t[BNXT_ULP_CLASS_HID_b04f] = 1137,\n+\t[BNXT_ULP_CLASS_HID_b28f] = 1138,\n+\t[BNXT_ULP_CLASS_HID_f5cf] = 1139,\n+\t[BNXT_ULP_CLASS_HID_f80f] = 1140,\n+\t[BNXT_ULP_CLASS_HID_1c64f] = 1141,\n+\t[BNXT_ULP_CLASS_HID_1e88f] = 1142,\n+\t[BNXT_ULP_CLASS_HID_1cbcf] = 1143,\n+\t[BNXT_ULP_CLASS_HID_1ee0f] = 1144,\n+\t[BNXT_ULP_CLASS_HID_1ca9b] = 1145,\n+\t[BNXT_ULP_CLASS_HID_1eddb] = 1146,\n+\t[BNXT_ULP_CLASS_HID_1d01b] = 1147,\n+\t[BNXT_ULP_CLASS_HID_1f35b] = 1148,\n+\t[BNXT_ULP_CLASS_HID_8b4b] = 1149,\n+\t[BNXT_ULP_CLASS_HID_ad8b] = 1150,\n+\t[BNXT_ULP_CLASS_HID_d0cb] = 1151,\n+\t[BNXT_ULP_CLASS_HID_f30b] = 1152,\n+\t[BNXT_ULP_CLASS_HID_867f] = 1153,\n+\t[BNXT_ULP_CLASS_HID_a8bf] = 1154,\n+\t[BNXT_ULP_CLASS_HID_cbff] = 1155,\n+\t[BNXT_ULP_CLASS_HID_ee3f] = 1156,\n+\t[BNXT_ULP_CLASS_HID_19c7f] = 1157,\n+\t[BNXT_ULP_CLASS_HID_1bebf] = 1158,\n+\t[BNXT_ULP_CLASS_HID_1e1ff] = 1159,\n+\t[BNXT_ULP_CLASS_HID_1e43f] = 1160,\n+\t[BNXT_ULP_CLASS_HID_1a14b] = 1161,\n+\t[BNXT_ULP_CLASS_HID_1a38b] = 1162,\n+\t[BNXT_ULP_CLASS_HID_1e6cb] = 1163,\n+\t[BNXT_ULP_CLASS_HID_1e90b] = 1164,\n+\t[BNXT_ULP_CLASS_HID_aedf] = 1165,\n+\t[BNXT_ULP_CLASS_HID_b11f] = 1166,\n+\t[BNXT_ULP_CLASS_HID_f45f] = 1167,\n+\t[BNXT_ULP_CLASS_HID_f69f] = 1168,\n+\t[BNXT_ULP_CLASS_HID_a983] = 1169,\n+\t[BNXT_ULP_CLASS_HID_acc3] = 1170,\n+\t[BNXT_ULP_CLASS_HID_ef03] = 1171,\n+\t[BNXT_ULP_CLASS_HID_f243] = 1172,\n+\t[BNXT_ULP_CLASS_HID_1bf83] = 1173,\n+\t[BNXT_ULP_CLASS_HID_1e2c3] = 1174,\n+\t[BNXT_ULP_CLASS_HID_1c503] = 1175,\n+\t[BNXT_ULP_CLASS_HID_1e843] = 1176,\n+\t[BNXT_ULP_CLASS_HID_1c4df] = 1177,\n+\t[BNXT_ULP_CLASS_HID_1e71f] = 1178,\n+\t[BNXT_ULP_CLASS_HID_1ca5f] = 1179,\n+\t[BNXT_ULP_CLASS_HID_1ec9f] = 1180,\n+\t[BNXT_ULP_CLASS_HID_2523] = 1181,\n+\t[BNXT_ULP_CLASS_HID_2bef] = 1182,\n+\t[BNXT_ULP_CLASS_HID_4f73] = 1183,\n+\t[BNXT_ULP_CLASS_HID_164b] = 1184,\n+\t[BNXT_ULP_CLASS_HID_39df] = 1185,\n+\t[BNXT_ULP_CLASS_HID_48b7] = 1186,\n+\t[BNXT_ULP_CLASS_HID_0f8f] = 1187,\n+\t[BNXT_ULP_CLASS_HID_3313] = 1188,\n+\t[BNXT_ULP_CLASS_HID_257b7] = 1189,\n+\t[BNXT_ULP_CLASS_HID_24467] = 1190,\n+\t[BNXT_ULP_CLASS_HID_23fbb] = 1191,\n+\t[BNXT_ULP_CLASS_HID_252cb] = 1192,\n+\t[BNXT_ULP_CLASS_HID_21e7f] = 1193,\n+\t[BNXT_ULP_CLASS_HID_20b2f] = 1194,\n+\t[BNXT_ULP_CLASS_HID_20663] = 1195,\n+\t[BNXT_ULP_CLASS_HID_219b3] = 1196,\n+\t[BNXT_ULP_CLASS_HID_24213] = 1197,\n+\t[BNXT_ULP_CLASS_HID_22ec3] = 1198,\n+\t[BNXT_ULP_CLASS_HID_22a17] = 1199,\n+\t[BNXT_ULP_CLASS_HID_23d27] = 1200,\n+\t[BNXT_ULP_CLASS_HID_208db] = 1201,\n+\t[BNXT_ULP_CLASS_HID_25277] = 1202,\n+\t[BNXT_ULP_CLASS_HID_24d8b] = 1203,\n+\t[BNXT_ULP_CLASS_HID_203ef] = 1204,\n+\t[BNXT_ULP_CLASS_HID_2517b] = 1205,\n+\t[BNXT_ULP_CLASS_HID_23e2b] = 1206,\n+\t[BNXT_ULP_CLASS_HID_2397f] = 1207,\n+\t[BNXT_ULP_CLASS_HID_24c8f] = 1208,\n+\t[BNXT_ULP_CLASS_HID_21823] = 1209,\n+\t[BNXT_ULP_CLASS_HID_20513] = 1210,\n+\t[BNXT_ULP_CLASS_HID_20027] = 1211,\n+\t[BNXT_ULP_CLASS_HID_21377] = 1212,\n+\t[BNXT_ULP_CLASS_HID_23bd7] = 1213,\n+\t[BNXT_ULP_CLASS_HID_22887] = 1214,\n+\t[BNXT_ULP_CLASS_HID_223db] = 1215,\n+\t[BNXT_ULP_CLASS_HID_236eb] = 1216,\n+\t[BNXT_ULP_CLASS_HID_2029f] = 1217,\n+\t[BNXT_ULP_CLASS_HID_24c3b] = 1218,\n+\t[BNXT_ULP_CLASS_HID_2474f] = 1219,\n+\t[BNXT_ULP_CLASS_HID_25a9f] = 1220,\n+\t[BNXT_ULP_CLASS_HID_24b3f] = 1221,\n+\t[BNXT_ULP_CLASS_HID_237ef] = 1222,\n+\t[BNXT_ULP_CLASS_HID_23323] = 1223,\n+\t[BNXT_ULP_CLASS_HID_24673] = 1224,\n+\t[BNXT_ULP_CLASS_HID_211e7] = 1225,\n+\t[BNXT_ULP_CLASS_HID_25b83] = 1226,\n+\t[BNXT_ULP_CLASS_HID_256d7] = 1227,\n+\t[BNXT_ULP_CLASS_HID_20d3b] = 1228,\n+\t[BNXT_ULP_CLASS_HID_2359b] = 1229,\n+\t[BNXT_ULP_CLASS_HID_2224b] = 1230,\n+\t[BNXT_ULP_CLASS_HID_21d9f] = 1231,\n+\t[BNXT_ULP_CLASS_HID_230af] = 1232,\n+\t[BNXT_ULP_CLASS_HID_2590f] = 1233,\n+\t[BNXT_ULP_CLASS_HID_245ff] = 1234,\n+\t[BNXT_ULP_CLASS_HID_24133] = 1235,\n+\t[BNXT_ULP_CLASS_HID_25443] = 1236,\n+\t[BNXT_ULP_CLASS_HID_244e3] = 1237,\n+\t[BNXT_ULP_CLASS_HID_231d3] = 1238,\n+\t[BNXT_ULP_CLASS_HID_22ce7] = 1239,\n+\t[BNXT_ULP_CLASS_HID_24037] = 1240,\n+\t[BNXT_ULP_CLASS_HID_20bab] = 1241,\n+\t[BNXT_ULP_CLASS_HID_25547] = 1242,\n+\t[BNXT_ULP_CLASS_HID_2509b] = 1243,\n+\t[BNXT_ULP_CLASS_HID_206ff] = 1244,\n+\t[BNXT_ULP_CLASS_HID_22f5f] = 1245,\n+\t[BNXT_ULP_CLASS_HID_21c0f] = 1246,\n+\t[BNXT_ULP_CLASS_HID_21743] = 1247,\n+\t[BNXT_ULP_CLASS_HID_22a93] = 1248,\n+\t[BNXT_ULP_CLASS_HID_252f3] = 1249,\n+\t[BNXT_ULP_CLASS_HID_23fa3] = 1250,\n+\t[BNXT_ULP_CLASS_HID_23af7] = 1251,\n+\t[BNXT_ULP_CLASS_HID_24e07] = 1252,\n+\t[BNXT_ULP_CLASS_HID_2322f] = 1253,\n+\t[BNXT_ULP_CLASS_HID_21f1f] = 1254,\n+\t[BNXT_ULP_CLASS_HID_21a53] = 1255,\n+\t[BNXT_ULP_CLASS_HID_22d63] = 1256,\n+\t[BNXT_ULP_CLASS_HID_255c3] = 1257,\n+\t[BNXT_ULP_CLASS_HID_242b3] = 1258,\n+\t[BNXT_ULP_CLASS_HID_23dc7] = 1259,\n+\t[BNXT_ULP_CLASS_HID_25117] = 1260,\n+\t[BNXT_ULP_CLASS_HID_22c13] = 1261,\n+\t[BNXT_ULP_CLASS_HID_218c3] = 1262,\n+\t[BNXT_ULP_CLASS_HID_21417] = 1263,\n+\t[BNXT_ULP_CLASS_HID_22727] = 1264,\n+\t[BNXT_ULP_CLASS_HID_24f87] = 1265,\n+\t[BNXT_ULP_CLASS_HID_23c77] = 1266,\n+\t[BNXT_ULP_CLASS_HID_2378b] = 1267,\n+\t[BNXT_ULP_CLASS_HID_24adb] = 1268,\n+\t[BNXT_ULP_CLASS_HID_257b] = 1269,\n+\t[BNXT_ULP_CLASS_HID_2bb7] = 1270,\n+\t[BNXT_ULP_CLASS_HID_4f2b] = 1271,\n+\t[BNXT_ULP_CLASS_HID_1613] = 1272,\n+\t[BNXT_ULP_CLASS_HID_3987] = 1273,\n+\t[BNXT_ULP_CLASS_HID_48ef] = 1274,\n+\t[BNXT_ULP_CLASS_HID_0fd7] = 1275,\n+\t[BNXT_ULP_CLASS_HID_334b] = 1276,\n+\t[BNXT_ULP_CLASS_HID_25797] = 1277,\n+\t[BNXT_ULP_CLASS_HID_285eb] = 1278,\n+\t[BNXT_ULP_CLASS_HID_310eb] = 1279,\n+\t[BNXT_ULP_CLASS_HID_39beb] = 1280,\n+\t[BNXT_ULP_CLASS_HID_24447] = 1281,\n+\t[BNXT_ULP_CLASS_HID_2cf47] = 1282,\n+\t[BNXT_ULP_CLASS_HID_35a47] = 1283,\n+\t[BNXT_ULP_CLASS_HID_3889b] = 1284,\n+\t[BNXT_ULP_CLASS_HID_23f9b] = 1285,\n+\t[BNXT_ULP_CLASS_HID_2ca9b] = 1286,\n+\t[BNXT_ULP_CLASS_HID_3559b] = 1287,\n+\t[BNXT_ULP_CLASS_HID_383ef] = 1288,\n+\t[BNXT_ULP_CLASS_HID_252eb] = 1289,\n+\t[BNXT_ULP_CLASS_HID_2813f] = 1290,\n+\t[BNXT_ULP_CLASS_HID_30c3f] = 1291,\n+\t[BNXT_ULP_CLASS_HID_3973f] = 1292,\n+\t[BNXT_ULP_CLASS_HID_21e5f] = 1293,\n+\t[BNXT_ULP_CLASS_HID_2a95f] = 1294,\n+\t[BNXT_ULP_CLASS_HID_3345f] = 1295,\n+\t[BNXT_ULP_CLASS_HID_3bf5f] = 1296,\n+\t[BNXT_ULP_CLASS_HID_20b0f] = 1297,\n+\t[BNXT_ULP_CLASS_HID_2960f] = 1298,\n+\t[BNXT_ULP_CLASS_HID_3210f] = 1299,\n+\t[BNXT_ULP_CLASS_HID_3ac0f] = 1300,\n+\t[BNXT_ULP_CLASS_HID_20643] = 1301,\n+\t[BNXT_ULP_CLASS_HID_29143] = 1302,\n+\t[BNXT_ULP_CLASS_HID_31c43] = 1303,\n+\t[BNXT_ULP_CLASS_HID_3a743] = 1304,\n+\t[BNXT_ULP_CLASS_HID_21993] = 1305,\n+\t[BNXT_ULP_CLASS_HID_2a493] = 1306,\n+\t[BNXT_ULP_CLASS_HID_32f93] = 1307,\n+\t[BNXT_ULP_CLASS_HID_3ba93] = 1308,\n+\t[BNXT_ULP_CLASS_HID_24233] = 1309,\n+\t[BNXT_ULP_CLASS_HID_2cd33] = 1310,\n+\t[BNXT_ULP_CLASS_HID_35833] = 1311,\n+\t[BNXT_ULP_CLASS_HID_38607] = 1312,\n+\t[BNXT_ULP_CLASS_HID_22ee3] = 1313,\n+\t[BNXT_ULP_CLASS_HID_2b9e3] = 1314,\n+\t[BNXT_ULP_CLASS_HID_344e3] = 1315,\n+\t[BNXT_ULP_CLASS_HID_3cfe3] = 1316,\n+\t[BNXT_ULP_CLASS_HID_22a37] = 1317,\n+\t[BNXT_ULP_CLASS_HID_2b537] = 1318,\n+\t[BNXT_ULP_CLASS_HID_34037] = 1319,\n+\t[BNXT_ULP_CLASS_HID_3cb37] = 1320,\n+\t[BNXT_ULP_CLASS_HID_23d07] = 1321,\n+\t[BNXT_ULP_CLASS_HID_2c807] = 1322,\n+\t[BNXT_ULP_CLASS_HID_35307] = 1323,\n+\t[BNXT_ULP_CLASS_HID_3815b] = 1324,\n+\t[BNXT_ULP_CLASS_HID_208fb] = 1325,\n+\t[BNXT_ULP_CLASS_HID_293fb] = 1326,\n+\t[BNXT_ULP_CLASS_HID_31efb] = 1327,\n+\t[BNXT_ULP_CLASS_HID_3a9fb] = 1328,\n+\t[BNXT_ULP_CLASS_HID_25257] = 1329,\n+\t[BNXT_ULP_CLASS_HID_280ab] = 1330,\n+\t[BNXT_ULP_CLASS_HID_30bab] = 1331,\n+\t[BNXT_ULP_CLASS_HID_396ab] = 1332,\n+\t[BNXT_ULP_CLASS_HID_24dab] = 1333,\n+\t[BNXT_ULP_CLASS_HID_2d8ab] = 1334,\n+\t[BNXT_ULP_CLASS_HID_306ff] = 1335,\n+\t[BNXT_ULP_CLASS_HID_391ff] = 1336,\n+\t[BNXT_ULP_CLASS_HID_203cf] = 1337,\n+\t[BNXT_ULP_CLASS_HID_28ecf] = 1338,\n+\t[BNXT_ULP_CLASS_HID_319cf] = 1339,\n+\t[BNXT_ULP_CLASS_HID_3a4cf] = 1340,\n+\t[BNXT_ULP_CLASS_HID_2515b] = 1341,\n+\t[BNXT_ULP_CLASS_HID_2dc5b] = 1342,\n+\t[BNXT_ULP_CLASS_HID_30aaf] = 1343,\n+\t[BNXT_ULP_CLASS_HID_395af] = 1344,\n+\t[BNXT_ULP_CLASS_HID_23e0b] = 1345,\n+\t[BNXT_ULP_CLASS_HID_2c90b] = 1346,\n+\t[BNXT_ULP_CLASS_HID_3540b] = 1347,\n+\t[BNXT_ULP_CLASS_HID_3825f] = 1348,\n+\t[BNXT_ULP_CLASS_HID_2395f] = 1349,\n+\t[BNXT_ULP_CLASS_HID_2c45f] = 1350,\n+\t[BNXT_ULP_CLASS_HID_34f5f] = 1351,\n+\t[BNXT_ULP_CLASS_HID_3da5f] = 1352,\n+\t[BNXT_ULP_CLASS_HID_24caf] = 1353,\n+\t[BNXT_ULP_CLASS_HID_2d7af] = 1354,\n+\t[BNXT_ULP_CLASS_HID_305e3] = 1355,\n+\t[BNXT_ULP_CLASS_HID_390e3] = 1356,\n+\t[BNXT_ULP_CLASS_HID_21803] = 1357,\n+\t[BNXT_ULP_CLASS_HID_2a303] = 1358,\n+\t[BNXT_ULP_CLASS_HID_32e03] = 1359,\n+\t[BNXT_ULP_CLASS_HID_3b903] = 1360,\n+\t[BNXT_ULP_CLASS_HID_20533] = 1361,\n+\t[BNXT_ULP_CLASS_HID_29033] = 1362,\n+\t[BNXT_ULP_CLASS_HID_31b33] = 1363,\n+\t[BNXT_ULP_CLASS_HID_3a633] = 1364,\n+\t[BNXT_ULP_CLASS_HID_20007] = 1365,\n+\t[BNXT_ULP_CLASS_HID_28b07] = 1366,\n+\t[BNXT_ULP_CLASS_HID_31607] = 1367,\n+\t[BNXT_ULP_CLASS_HID_3a107] = 1368,\n+\t[BNXT_ULP_CLASS_HID_21357] = 1369,\n+\t[BNXT_ULP_CLASS_HID_29e57] = 1370,\n+\t[BNXT_ULP_CLASS_HID_32957] = 1371,\n+\t[BNXT_ULP_CLASS_HID_3b457] = 1372,\n+\t[BNXT_ULP_CLASS_HID_23bf7] = 1373,\n+\t[BNXT_ULP_CLASS_HID_2c6f7] = 1374,\n+\t[BNXT_ULP_CLASS_HID_351f7] = 1375,\n+\t[BNXT_ULP_CLASS_HID_3dcf7] = 1376,\n+\t[BNXT_ULP_CLASS_HID_228a7] = 1377,\n+\t[BNXT_ULP_CLASS_HID_2b3a7] = 1378,\n+\t[BNXT_ULP_CLASS_HID_33ea7] = 1379,\n+\t[BNXT_ULP_CLASS_HID_3c9a7] = 1380,\n+\t[BNXT_ULP_CLASS_HID_223fb] = 1381,\n+\t[BNXT_ULP_CLASS_HID_2aefb] = 1382,\n+\t[BNXT_ULP_CLASS_HID_339fb] = 1383,\n+\t[BNXT_ULP_CLASS_HID_3c4fb] = 1384,\n+\t[BNXT_ULP_CLASS_HID_236cb] = 1385,\n+\t[BNXT_ULP_CLASS_HID_2c1cb] = 1386,\n+\t[BNXT_ULP_CLASS_HID_34ccb] = 1387,\n+\t[BNXT_ULP_CLASS_HID_3d7cb] = 1388,\n+\t[BNXT_ULP_CLASS_HID_202bf] = 1389,\n+\t[BNXT_ULP_CLASS_HID_28dbf] = 1390,\n+\t[BNXT_ULP_CLASS_HID_318bf] = 1391,\n+\t[BNXT_ULP_CLASS_HID_3a3bf] = 1392,\n+\t[BNXT_ULP_CLASS_HID_24c1b] = 1393,\n+\t[BNXT_ULP_CLASS_HID_2d71b] = 1394,\n+\t[BNXT_ULP_CLASS_HID_3056f] = 1395,\n+\t[BNXT_ULP_CLASS_HID_3906f] = 1396,\n+\t[BNXT_ULP_CLASS_HID_2476f] = 1397,\n+\t[BNXT_ULP_CLASS_HID_2d26f] = 1398,\n+\t[BNXT_ULP_CLASS_HID_300a3] = 1399,\n+\t[BNXT_ULP_CLASS_HID_38ba3] = 1400,\n+\t[BNXT_ULP_CLASS_HID_25abf] = 1401,\n+\t[BNXT_ULP_CLASS_HID_288f3] = 1402,\n+\t[BNXT_ULP_CLASS_HID_313f3] = 1403,\n+\t[BNXT_ULP_CLASS_HID_39ef3] = 1404,\n+\t[BNXT_ULP_CLASS_HID_24b1f] = 1405,\n+\t[BNXT_ULP_CLASS_HID_2d61f] = 1406,\n+\t[BNXT_ULP_CLASS_HID_30453] = 1407,\n+\t[BNXT_ULP_CLASS_HID_38f53] = 1408,\n+\t[BNXT_ULP_CLASS_HID_237cf] = 1409,\n+\t[BNXT_ULP_CLASS_HID_2c2cf] = 1410,\n+\t[BNXT_ULP_CLASS_HID_34dcf] = 1411,\n+\t[BNXT_ULP_CLASS_HID_3d8cf] = 1412,\n+\t[BNXT_ULP_CLASS_HID_23303] = 1413,\n+\t[BNXT_ULP_CLASS_HID_2be03] = 1414,\n+\t[BNXT_ULP_CLASS_HID_34903] = 1415,\n+\t[BNXT_ULP_CLASS_HID_3d403] = 1416,\n+\t[BNXT_ULP_CLASS_HID_24653] = 1417,\n+\t[BNXT_ULP_CLASS_HID_2d153] = 1418,\n+\t[BNXT_ULP_CLASS_HID_35c53] = 1419,\n+\t[BNXT_ULP_CLASS_HID_38aa7] = 1420,\n+\t[BNXT_ULP_CLASS_HID_211c7] = 1421,\n+\t[BNXT_ULP_CLASS_HID_29cc7] = 1422,\n+\t[BNXT_ULP_CLASS_HID_327c7] = 1423,\n+\t[BNXT_ULP_CLASS_HID_3b2c7] = 1424,\n+\t[BNXT_ULP_CLASS_HID_25ba3] = 1425,\n+\t[BNXT_ULP_CLASS_HID_289f7] = 1426,\n+\t[BNXT_ULP_CLASS_HID_314f7] = 1427,\n+\t[BNXT_ULP_CLASS_HID_39ff7] = 1428,\n+\t[BNXT_ULP_CLASS_HID_256f7] = 1429,\n+\t[BNXT_ULP_CLASS_HID_284cb] = 1430,\n+\t[BNXT_ULP_CLASS_HID_30fcb] = 1431,\n+\t[BNXT_ULP_CLASS_HID_39acb] = 1432,\n+\t[BNXT_ULP_CLASS_HID_20d1b] = 1433,\n+\t[BNXT_ULP_CLASS_HID_2981b] = 1434,\n+\t[BNXT_ULP_CLASS_HID_3231b] = 1435,\n+\t[BNXT_ULP_CLASS_HID_3ae1b] = 1436,\n+\t[BNXT_ULP_CLASS_HID_235bb] = 1437,\n+\t[BNXT_ULP_CLASS_HID_2c0bb] = 1438,\n+\t[BNXT_ULP_CLASS_HID_34bbb] = 1439,\n+\t[BNXT_ULP_CLASS_HID_3d6bb] = 1440,\n+\t[BNXT_ULP_CLASS_HID_2226b] = 1441,\n+\t[BNXT_ULP_CLASS_HID_2ad6b] = 1442,\n+\t[BNXT_ULP_CLASS_HID_3386b] = 1443,\n+\t[BNXT_ULP_CLASS_HID_3c36b] = 1444,\n+\t[BNXT_ULP_CLASS_HID_21dbf] = 1445,\n+\t[BNXT_ULP_CLASS_HID_2a8bf] = 1446,\n+\t[BNXT_ULP_CLASS_HID_333bf] = 1447,\n+\t[BNXT_ULP_CLASS_HID_3bebf] = 1448,\n+\t[BNXT_ULP_CLASS_HID_2308f] = 1449,\n+\t[BNXT_ULP_CLASS_HID_2bb8f] = 1450,\n+\t[BNXT_ULP_CLASS_HID_3468f] = 1451,\n+\t[BNXT_ULP_CLASS_HID_3d18f] = 1452,\n+\t[BNXT_ULP_CLASS_HID_2592f] = 1453,\n+\t[BNXT_ULP_CLASS_HID_28763] = 1454,\n+\t[BNXT_ULP_CLASS_HID_31263] = 1455,\n+\t[BNXT_ULP_CLASS_HID_39d63] = 1456,\n+\t[BNXT_ULP_CLASS_HID_245df] = 1457,\n+\t[BNXT_ULP_CLASS_HID_2d0df] = 1458,\n+\t[BNXT_ULP_CLASS_HID_35bdf] = 1459,\n+\t[BNXT_ULP_CLASS_HID_38a13] = 1460,\n+\t[BNXT_ULP_CLASS_HID_24113] = 1461,\n+\t[BNXT_ULP_CLASS_HID_2cc13] = 1462,\n+\t[BNXT_ULP_CLASS_HID_35713] = 1463,\n+\t[BNXT_ULP_CLASS_HID_38567] = 1464,\n+\t[BNXT_ULP_CLASS_HID_25463] = 1465,\n+\t[BNXT_ULP_CLASS_HID_282b7] = 1466,\n+\t[BNXT_ULP_CLASS_HID_30db7] = 1467,\n+\t[BNXT_ULP_CLASS_HID_398b7] = 1468,\n+\t[BNXT_ULP_CLASS_HID_244c3] = 1469,\n+\t[BNXT_ULP_CLASS_HID_2cfc3] = 1470,\n+\t[BNXT_ULP_CLASS_HID_35ac3] = 1471,\n+\t[BNXT_ULP_CLASS_HID_38917] = 1472,\n+\t[BNXT_ULP_CLASS_HID_231f3] = 1473,\n+\t[BNXT_ULP_CLASS_HID_2bcf3] = 1474,\n+\t[BNXT_ULP_CLASS_HID_347f3] = 1475,\n+\t[BNXT_ULP_CLASS_HID_3d2f3] = 1476,\n+\t[BNXT_ULP_CLASS_HID_22cc7] = 1477,\n+\t[BNXT_ULP_CLASS_HID_2b7c7] = 1478,\n+\t[BNXT_ULP_CLASS_HID_342c7] = 1479,\n+\t[BNXT_ULP_CLASS_HID_3cdc7] = 1480,\n+\t[BNXT_ULP_CLASS_HID_24017] = 1481,\n+\t[BNXT_ULP_CLASS_HID_2cb17] = 1482,\n+\t[BNXT_ULP_CLASS_HID_35617] = 1483,\n+\t[BNXT_ULP_CLASS_HID_3846b] = 1484,\n+\t[BNXT_ULP_CLASS_HID_20b8b] = 1485,\n+\t[BNXT_ULP_CLASS_HID_2968b] = 1486,\n+\t[BNXT_ULP_CLASS_HID_3218b] = 1487,\n+\t[BNXT_ULP_CLASS_HID_3ac8b] = 1488,\n+\t[BNXT_ULP_CLASS_HID_25567] = 1489,\n+\t[BNXT_ULP_CLASS_HID_283bb] = 1490,\n+\t[BNXT_ULP_CLASS_HID_30ebb] = 1491,\n+\t[BNXT_ULP_CLASS_HID_399bb] = 1492,\n+\t[BNXT_ULP_CLASS_HID_250bb] = 1493,\n+\t[BNXT_ULP_CLASS_HID_2dbbb] = 1494,\n+\t[BNXT_ULP_CLASS_HID_3098f] = 1495,\n+\t[BNXT_ULP_CLASS_HID_3948f] = 1496,\n+\t[BNXT_ULP_CLASS_HID_206df] = 1497,\n+\t[BNXT_ULP_CLASS_HID_291df] = 1498,\n+\t[BNXT_ULP_CLASS_HID_31cdf] = 1499,\n+\t[BNXT_ULP_CLASS_HID_3a7df] = 1500,\n+\t[BNXT_ULP_CLASS_HID_22f7f] = 1501,\n+\t[BNXT_ULP_CLASS_HID_2ba7f] = 1502,\n+\t[BNXT_ULP_CLASS_HID_3457f] = 1503,\n+\t[BNXT_ULP_CLASS_HID_3d07f] = 1504,\n+\t[BNXT_ULP_CLASS_HID_21c2f] = 1505,\n+\t[BNXT_ULP_CLASS_HID_2a72f] = 1506,\n+\t[BNXT_ULP_CLASS_HID_3322f] = 1507,\n+\t[BNXT_ULP_CLASS_HID_3bd2f] = 1508,\n+\t[BNXT_ULP_CLASS_HID_21763] = 1509,\n+\t[BNXT_ULP_CLASS_HID_2a263] = 1510,\n+\t[BNXT_ULP_CLASS_HID_32d63] = 1511,\n+\t[BNXT_ULP_CLASS_HID_3b863] = 1512,\n+\t[BNXT_ULP_CLASS_HID_22ab3] = 1513,\n+\t[BNXT_ULP_CLASS_HID_2b5b3] = 1514,\n+\t[BNXT_ULP_CLASS_HID_340b3] = 1515,\n+\t[BNXT_ULP_CLASS_HID_3cbb3] = 1516,\n+\t[BNXT_ULP_CLASS_HID_252d3] = 1517,\n+\t[BNXT_ULP_CLASS_HID_28127] = 1518,\n+\t[BNXT_ULP_CLASS_HID_30c27] = 1519,\n+\t[BNXT_ULP_CLASS_HID_39727] = 1520,\n+\t[BNXT_ULP_CLASS_HID_23f83] = 1521,\n+\t[BNXT_ULP_CLASS_HID_2ca83] = 1522,\n+\t[BNXT_ULP_CLASS_HID_35583] = 1523,\n+\t[BNXT_ULP_CLASS_HID_383d7] = 1524,\n+\t[BNXT_ULP_CLASS_HID_23ad7] = 1525,\n+\t[BNXT_ULP_CLASS_HID_2c5d7] = 1526,\n+\t[BNXT_ULP_CLASS_HID_350d7] = 1527,\n+\t[BNXT_ULP_CLASS_HID_3dbd7] = 1528,\n+\t[BNXT_ULP_CLASS_HID_24e27] = 1529,\n+\t[BNXT_ULP_CLASS_HID_2d927] = 1530,\n+\t[BNXT_ULP_CLASS_HID_3077b] = 1531,\n+\t[BNXT_ULP_CLASS_HID_3927b] = 1532,\n+\t[BNXT_ULP_CLASS_HID_2320f] = 1533,\n+\t[BNXT_ULP_CLASS_HID_2bd0f] = 1534,\n+\t[BNXT_ULP_CLASS_HID_3480f] = 1535,\n+\t[BNXT_ULP_CLASS_HID_3d30f] = 1536,\n+\t[BNXT_ULP_CLASS_HID_21f3f] = 1537,\n+\t[BNXT_ULP_CLASS_HID_2aa3f] = 1538,\n+\t[BNXT_ULP_CLASS_HID_3353f] = 1539,\n+\t[BNXT_ULP_CLASS_HID_3c03f] = 1540,\n+\t[BNXT_ULP_CLASS_HID_21a73] = 1541,\n+\t[BNXT_ULP_CLASS_HID_2a573] = 1542,\n+\t[BNXT_ULP_CLASS_HID_33073] = 1543,\n+\t[BNXT_ULP_CLASS_HID_3bb73] = 1544,\n+\t[BNXT_ULP_CLASS_HID_22d43] = 1545,\n+\t[BNXT_ULP_CLASS_HID_2b843] = 1546,\n+\t[BNXT_ULP_CLASS_HID_34343] = 1547,\n+\t[BNXT_ULP_CLASS_HID_3ce43] = 1548,\n+\t[BNXT_ULP_CLASS_HID_255e3] = 1549,\n+\t[BNXT_ULP_CLASS_HID_28437] = 1550,\n+\t[BNXT_ULP_CLASS_HID_30f37] = 1551,\n+\t[BNXT_ULP_CLASS_HID_39a37] = 1552,\n+\t[BNXT_ULP_CLASS_HID_24293] = 1553,\n+\t[BNXT_ULP_CLASS_HID_2cd93] = 1554,\n+\t[BNXT_ULP_CLASS_HID_35893] = 1555,\n+\t[BNXT_ULP_CLASS_HID_386e7] = 1556,\n+\t[BNXT_ULP_CLASS_HID_23de7] = 1557,\n+\t[BNXT_ULP_CLASS_HID_2c8e7] = 1558,\n+\t[BNXT_ULP_CLASS_HID_353e7] = 1559,\n+\t[BNXT_ULP_CLASS_HID_3823b] = 1560,\n+\t[BNXT_ULP_CLASS_HID_25137] = 1561,\n+\t[BNXT_ULP_CLASS_HID_2dc37] = 1562,\n+\t[BNXT_ULP_CLASS_HID_30a0b] = 1563,\n+\t[BNXT_ULP_CLASS_HID_3950b] = 1564,\n+\t[BNXT_ULP_CLASS_HID_22c33] = 1565,\n+\t[BNXT_ULP_CLASS_HID_2b733] = 1566,\n+\t[BNXT_ULP_CLASS_HID_34233] = 1567,\n+\t[BNXT_ULP_CLASS_HID_3cd33] = 1568,\n+\t[BNXT_ULP_CLASS_HID_218e3] = 1569,\n+\t[BNXT_ULP_CLASS_HID_2a3e3] = 1570,\n+\t[BNXT_ULP_CLASS_HID_32ee3] = 1571,\n+\t[BNXT_ULP_CLASS_HID_3b9e3] = 1572,\n+\t[BNXT_ULP_CLASS_HID_21437] = 1573,\n+\t[BNXT_ULP_CLASS_HID_29f37] = 1574,\n+\t[BNXT_ULP_CLASS_HID_32a37] = 1575,\n+\t[BNXT_ULP_CLASS_HID_3b537] = 1576,\n+\t[BNXT_ULP_CLASS_HID_22707] = 1577,\n+\t[BNXT_ULP_CLASS_HID_2b207] = 1578,\n+\t[BNXT_ULP_CLASS_HID_33d07] = 1579,\n+\t[BNXT_ULP_CLASS_HID_3c807] = 1580,\n+\t[BNXT_ULP_CLASS_HID_24fa7] = 1581,\n+\t[BNXT_ULP_CLASS_HID_2daa7] = 1582,\n+\t[BNXT_ULP_CLASS_HID_308fb] = 1583,\n+\t[BNXT_ULP_CLASS_HID_393fb] = 1584,\n+\t[BNXT_ULP_CLASS_HID_23c57] = 1585,\n+\t[BNXT_ULP_CLASS_HID_2c757] = 1586,\n+\t[BNXT_ULP_CLASS_HID_35257] = 1587,\n+\t[BNXT_ULP_CLASS_HID_380ab] = 1588,\n+\t[BNXT_ULP_CLASS_HID_237ab] = 1589,\n+\t[BNXT_ULP_CLASS_HID_2c2ab] = 1590,\n+\t[BNXT_ULP_CLASS_HID_34dab] = 1591,\n+\t[BNXT_ULP_CLASS_HID_3d8ab] = 1592,\n+\t[BNXT_ULP_CLASS_HID_24afb] = 1593,\n+\t[BNXT_ULP_CLASS_HID_2d5fb] = 1594,\n+\t[BNXT_ULP_CLASS_HID_303cf] = 1595,\n+\t[BNXT_ULP_CLASS_HID_38ecf] = 1596,\n+\t[BNXT_ULP_CLASS_HID_255b] = 1597,\n+\t[BNXT_ULP_CLASS_HID_2b97] = 1598,\n+\t[BNXT_ULP_CLASS_HID_4f0b] = 1599,\n+\t[BNXT_ULP_CLASS_HID_1633] = 1600,\n+\t[BNXT_ULP_CLASS_HID_39a7] = 1601,\n+\t[BNXT_ULP_CLASS_HID_48cf] = 1602,\n+\t[BNXT_ULP_CLASS_HID_0ff7] = 1603,\n+\t[BNXT_ULP_CLASS_HID_336b] = 1604,\n+\t[BNXT_ULP_CLASS_HID_257f7] = 1605,\n+\t[BNXT_ULP_CLASS_HID_2858b] = 1606,\n+\t[BNXT_ULP_CLASS_HID_3108b] = 1607,\n+\t[BNXT_ULP_CLASS_HID_39b8b] = 1608,\n+\t[BNXT_ULP_CLASS_HID_24427] = 1609,\n+\t[BNXT_ULP_CLASS_HID_2cf27] = 1610,\n+\t[BNXT_ULP_CLASS_HID_35a27] = 1611,\n+\t[BNXT_ULP_CLASS_HID_388fb] = 1612,\n+\t[BNXT_ULP_CLASS_HID_23ffb] = 1613,\n+\t[BNXT_ULP_CLASS_HID_2cafb] = 1614,\n+\t[BNXT_ULP_CLASS_HID_355fb] = 1615,\n+\t[BNXT_ULP_CLASS_HID_3838f] = 1616,\n+\t[BNXT_ULP_CLASS_HID_2528b] = 1617,\n+\t[BNXT_ULP_CLASS_HID_2815f] = 1618,\n+\t[BNXT_ULP_CLASS_HID_30c5f] = 1619,\n+\t[BNXT_ULP_CLASS_HID_3975f] = 1620,\n+\t[BNXT_ULP_CLASS_HID_21e3f] = 1621,\n+\t[BNXT_ULP_CLASS_HID_2a93f] = 1622,\n+\t[BNXT_ULP_CLASS_HID_3343f] = 1623,\n+\t[BNXT_ULP_CLASS_HID_3bf3f] = 1624,\n+\t[BNXT_ULP_CLASS_HID_20b6f] = 1625,\n+\t[BNXT_ULP_CLASS_HID_2966f] = 1626,\n+\t[BNXT_ULP_CLASS_HID_3216f] = 1627,\n+\t[BNXT_ULP_CLASS_HID_3ac6f] = 1628,\n+\t[BNXT_ULP_CLASS_HID_20623] = 1629,\n+\t[BNXT_ULP_CLASS_HID_29123] = 1630,\n+\t[BNXT_ULP_CLASS_HID_31c23] = 1631,\n+\t[BNXT_ULP_CLASS_HID_3a723] = 1632,\n+\t[BNXT_ULP_CLASS_HID_219f3] = 1633,\n+\t[BNXT_ULP_CLASS_HID_2a4f3] = 1634,\n+\t[BNXT_ULP_CLASS_HID_32ff3] = 1635,\n+\t[BNXT_ULP_CLASS_HID_3baf3] = 1636,\n+\t[BNXT_ULP_CLASS_HID_24253] = 1637,\n+\t[BNXT_ULP_CLASS_HID_2cd53] = 1638,\n+\t[BNXT_ULP_CLASS_HID_35853] = 1639,\n+\t[BNXT_ULP_CLASS_HID_38667] = 1640,\n+\t[BNXT_ULP_CLASS_HID_22e83] = 1641,\n+\t[BNXT_ULP_CLASS_HID_2b983] = 1642,\n+\t[BNXT_ULP_CLASS_HID_34483] = 1643,\n+\t[BNXT_ULP_CLASS_HID_3cf83] = 1644,\n+\t[BNXT_ULP_CLASS_HID_22a57] = 1645,\n+\t[BNXT_ULP_CLASS_HID_2b557] = 1646,\n+\t[BNXT_ULP_CLASS_HID_34057] = 1647,\n+\t[BNXT_ULP_CLASS_HID_3cb57] = 1648,\n+\t[BNXT_ULP_CLASS_HID_23d67] = 1649,\n+\t[BNXT_ULP_CLASS_HID_2c867] = 1650,\n+\t[BNXT_ULP_CLASS_HID_35367] = 1651,\n+\t[BNXT_ULP_CLASS_HID_3813b] = 1652,\n+\t[BNXT_ULP_CLASS_HID_2089b] = 1653,\n+\t[BNXT_ULP_CLASS_HID_2939b] = 1654,\n+\t[BNXT_ULP_CLASS_HID_31e9b] = 1655,\n+\t[BNXT_ULP_CLASS_HID_3a99b] = 1656,\n+\t[BNXT_ULP_CLASS_HID_25237] = 1657,\n+\t[BNXT_ULP_CLASS_HID_280cb] = 1658,\n+\t[BNXT_ULP_CLASS_HID_30bcb] = 1659,\n+\t[BNXT_ULP_CLASS_HID_396cb] = 1660,\n+\t[BNXT_ULP_CLASS_HID_24dcb] = 1661,\n+\t[BNXT_ULP_CLASS_HID_2d8cb] = 1662,\n+\t[BNXT_ULP_CLASS_HID_3069f] = 1663,\n+\t[BNXT_ULP_CLASS_HID_3919f] = 1664,\n+\t[BNXT_ULP_CLASS_HID_203af] = 1665,\n+\t[BNXT_ULP_CLASS_HID_28eaf] = 1666,\n+\t[BNXT_ULP_CLASS_HID_319af] = 1667,\n+\t[BNXT_ULP_CLASS_HID_3a4af] = 1668,\n+\t[BNXT_ULP_CLASS_HID_2513b] = 1669,\n+\t[BNXT_ULP_CLASS_HID_2dc3b] = 1670,\n+\t[BNXT_ULP_CLASS_HID_30acf] = 1671,\n+\t[BNXT_ULP_CLASS_HID_395cf] = 1672,\n+\t[BNXT_ULP_CLASS_HID_23e6b] = 1673,\n+\t[BNXT_ULP_CLASS_HID_2c96b] = 1674,\n+\t[BNXT_ULP_CLASS_HID_3546b] = 1675,\n+\t[BNXT_ULP_CLASS_HID_3823f] = 1676,\n+\t[BNXT_ULP_CLASS_HID_2393f] = 1677,\n+\t[BNXT_ULP_CLASS_HID_2c43f] = 1678,\n+\t[BNXT_ULP_CLASS_HID_34f3f] = 1679,\n+\t[BNXT_ULP_CLASS_HID_3da3f] = 1680,\n+\t[BNXT_ULP_CLASS_HID_24ccf] = 1681,\n+\t[BNXT_ULP_CLASS_HID_2d7cf] = 1682,\n+\t[BNXT_ULP_CLASS_HID_30583] = 1683,\n+\t[BNXT_ULP_CLASS_HID_39083] = 1684,\n+\t[BNXT_ULP_CLASS_HID_21863] = 1685,\n+\t[BNXT_ULP_CLASS_HID_2a363] = 1686,\n+\t[BNXT_ULP_CLASS_HID_32e63] = 1687,\n+\t[BNXT_ULP_CLASS_HID_3b963] = 1688,\n+\t[BNXT_ULP_CLASS_HID_20553] = 1689,\n+\t[BNXT_ULP_CLASS_HID_29053] = 1690,\n+\t[BNXT_ULP_CLASS_HID_31b53] = 1691,\n+\t[BNXT_ULP_CLASS_HID_3a653] = 1692,\n+\t[BNXT_ULP_CLASS_HID_20067] = 1693,\n+\t[BNXT_ULP_CLASS_HID_28b67] = 1694,\n+\t[BNXT_ULP_CLASS_HID_31667] = 1695,\n+\t[BNXT_ULP_CLASS_HID_3a167] = 1696,\n+\t[BNXT_ULP_CLASS_HID_21337] = 1697,\n+\t[BNXT_ULP_CLASS_HID_29e37] = 1698,\n+\t[BNXT_ULP_CLASS_HID_32937] = 1699,\n+\t[BNXT_ULP_CLASS_HID_3b437] = 1700,\n+\t[BNXT_ULP_CLASS_HID_23b97] = 1701,\n+\t[BNXT_ULP_CLASS_HID_2c697] = 1702,\n+\t[BNXT_ULP_CLASS_HID_35197] = 1703,\n+\t[BNXT_ULP_CLASS_HID_3dc97] = 1704,\n+\t[BNXT_ULP_CLASS_HID_228c7] = 1705,\n+\t[BNXT_ULP_CLASS_HID_2b3c7] = 1706,\n+\t[BNXT_ULP_CLASS_HID_33ec7] = 1707,\n+\t[BNXT_ULP_CLASS_HID_3c9c7] = 1708,\n+\t[BNXT_ULP_CLASS_HID_2239b] = 1709,\n+\t[BNXT_ULP_CLASS_HID_2ae9b] = 1710,\n+\t[BNXT_ULP_CLASS_HID_3399b] = 1711,\n+\t[BNXT_ULP_CLASS_HID_3c49b] = 1712,\n+\t[BNXT_ULP_CLASS_HID_236ab] = 1713,\n+\t[BNXT_ULP_CLASS_HID_2c1ab] = 1714,\n+\t[BNXT_ULP_CLASS_HID_34cab] = 1715,\n+\t[BNXT_ULP_CLASS_HID_3d7ab] = 1716,\n+\t[BNXT_ULP_CLASS_HID_202df] = 1717,\n+\t[BNXT_ULP_CLASS_HID_28ddf] = 1718,\n+\t[BNXT_ULP_CLASS_HID_318df] = 1719,\n+\t[BNXT_ULP_CLASS_HID_3a3df] = 1720,\n+\t[BNXT_ULP_CLASS_HID_24c7b] = 1721,\n+\t[BNXT_ULP_CLASS_HID_2d77b] = 1722,\n+\t[BNXT_ULP_CLASS_HID_3050f] = 1723,\n+\t[BNXT_ULP_CLASS_HID_3900f] = 1724,\n+\t[BNXT_ULP_CLASS_HID_2470f] = 1725,\n+\t[BNXT_ULP_CLASS_HID_2d20f] = 1726,\n+\t[BNXT_ULP_CLASS_HID_300c3] = 1727,\n+\t[BNXT_ULP_CLASS_HID_38bc3] = 1728,\n+\t[BNXT_ULP_CLASS_HID_25adf] = 1729,\n+\t[BNXT_ULP_CLASS_HID_28893] = 1730,\n+\t[BNXT_ULP_CLASS_HID_31393] = 1731,\n+\t[BNXT_ULP_CLASS_HID_39e93] = 1732,\n+\t[BNXT_ULP_CLASS_HID_24b7f] = 1733,\n+\t[BNXT_ULP_CLASS_HID_2d67f] = 1734,\n+\t[BNXT_ULP_CLASS_HID_30433] = 1735,\n+\t[BNXT_ULP_CLASS_HID_38f33] = 1736,\n+\t[BNXT_ULP_CLASS_HID_237af] = 1737,\n+\t[BNXT_ULP_CLASS_HID_2c2af] = 1738,\n+\t[BNXT_ULP_CLASS_HID_34daf] = 1739,\n+\t[BNXT_ULP_CLASS_HID_3d8af] = 1740,\n+\t[BNXT_ULP_CLASS_HID_23363] = 1741,\n+\t[BNXT_ULP_CLASS_HID_2be63] = 1742,\n+\t[BNXT_ULP_CLASS_HID_34963] = 1743,\n+\t[BNXT_ULP_CLASS_HID_3d463] = 1744,\n+\t[BNXT_ULP_CLASS_HID_24633] = 1745,\n+\t[BNXT_ULP_CLASS_HID_2d133] = 1746,\n+\t[BNXT_ULP_CLASS_HID_35c33] = 1747,\n+\t[BNXT_ULP_CLASS_HID_38ac7] = 1748,\n+\t[BNXT_ULP_CLASS_HID_211a7] = 1749,\n+\t[BNXT_ULP_CLASS_HID_29ca7] = 1750,\n+\t[BNXT_ULP_CLASS_HID_327a7] = 1751,\n+\t[BNXT_ULP_CLASS_HID_3b2a7] = 1752,\n+\t[BNXT_ULP_CLASS_HID_25bc3] = 1753,\n+\t[BNXT_ULP_CLASS_HID_28997] = 1754,\n+\t[BNXT_ULP_CLASS_HID_31497] = 1755,\n+\t[BNXT_ULP_CLASS_HID_39f97] = 1756,\n+\t[BNXT_ULP_CLASS_HID_25697] = 1757,\n+\t[BNXT_ULP_CLASS_HID_284ab] = 1758,\n+\t[BNXT_ULP_CLASS_HID_30fab] = 1759,\n+\t[BNXT_ULP_CLASS_HID_39aab] = 1760,\n+\t[BNXT_ULP_CLASS_HID_20d7b] = 1761,\n+\t[BNXT_ULP_CLASS_HID_2987b] = 1762,\n+\t[BNXT_ULP_CLASS_HID_3237b] = 1763,\n+\t[BNXT_ULP_CLASS_HID_3ae7b] = 1764,\n+\t[BNXT_ULP_CLASS_HID_235db] = 1765,\n+\t[BNXT_ULP_CLASS_HID_2c0db] = 1766,\n+\t[BNXT_ULP_CLASS_HID_34bdb] = 1767,\n+\t[BNXT_ULP_CLASS_HID_3d6db] = 1768,\n+\t[BNXT_ULP_CLASS_HID_2220b] = 1769,\n+\t[BNXT_ULP_CLASS_HID_2ad0b] = 1770,\n+\t[BNXT_ULP_CLASS_HID_3380b] = 1771,\n+\t[BNXT_ULP_CLASS_HID_3c30b] = 1772,\n+\t[BNXT_ULP_CLASS_HID_21ddf] = 1773,\n+\t[BNXT_ULP_CLASS_HID_2a8df] = 1774,\n+\t[BNXT_ULP_CLASS_HID_333df] = 1775,\n+\t[BNXT_ULP_CLASS_HID_3bedf] = 1776,\n+\t[BNXT_ULP_CLASS_HID_230ef] = 1777,\n+\t[BNXT_ULP_CLASS_HID_2bbef] = 1778,\n+\t[BNXT_ULP_CLASS_HID_346ef] = 1779,\n+\t[BNXT_ULP_CLASS_HID_3d1ef] = 1780,\n+\t[BNXT_ULP_CLASS_HID_2594f] = 1781,\n+\t[BNXT_ULP_CLASS_HID_28703] = 1782,\n+\t[BNXT_ULP_CLASS_HID_31203] = 1783,\n+\t[BNXT_ULP_CLASS_HID_39d03] = 1784,\n+\t[BNXT_ULP_CLASS_HID_245bf] = 1785,\n+\t[BNXT_ULP_CLASS_HID_2d0bf] = 1786,\n+\t[BNXT_ULP_CLASS_HID_35bbf] = 1787,\n+\t[BNXT_ULP_CLASS_HID_38a73] = 1788,\n+\t[BNXT_ULP_CLASS_HID_24173] = 1789,\n+\t[BNXT_ULP_CLASS_HID_2cc73] = 1790,\n+\t[BNXT_ULP_CLASS_HID_35773] = 1791,\n+\t[BNXT_ULP_CLASS_HID_38507] = 1792,\n+\t[BNXT_ULP_CLASS_HID_25403] = 1793,\n+\t[BNXT_ULP_CLASS_HID_282d7] = 1794,\n+\t[BNXT_ULP_CLASS_HID_30dd7] = 1795,\n+\t[BNXT_ULP_CLASS_HID_398d7] = 1796,\n+\t[BNXT_ULP_CLASS_HID_244a3] = 1797,\n+\t[BNXT_ULP_CLASS_HID_2cfa3] = 1798,\n+\t[BNXT_ULP_CLASS_HID_35aa3] = 1799,\n+\t[BNXT_ULP_CLASS_HID_38977] = 1800,\n+\t[BNXT_ULP_CLASS_HID_23193] = 1801,\n+\t[BNXT_ULP_CLASS_HID_2bc93] = 1802,\n+\t[BNXT_ULP_CLASS_HID_34793] = 1803,\n+\t[BNXT_ULP_CLASS_HID_3d293] = 1804,\n+\t[BNXT_ULP_CLASS_HID_22ca7] = 1805,\n+\t[BNXT_ULP_CLASS_HID_2b7a7] = 1806,\n+\t[BNXT_ULP_CLASS_HID_342a7] = 1807,\n+\t[BNXT_ULP_CLASS_HID_3cda7] = 1808,\n+\t[BNXT_ULP_CLASS_HID_24077] = 1809,\n+\t[BNXT_ULP_CLASS_HID_2cb77] = 1810,\n+\t[BNXT_ULP_CLASS_HID_35677] = 1811,\n+\t[BNXT_ULP_CLASS_HID_3840b] = 1812,\n+\t[BNXT_ULP_CLASS_HID_20beb] = 1813,\n+\t[BNXT_ULP_CLASS_HID_296eb] = 1814,\n+\t[BNXT_ULP_CLASS_HID_321eb] = 1815,\n+\t[BNXT_ULP_CLASS_HID_3aceb] = 1816,\n+\t[BNXT_ULP_CLASS_HID_25507] = 1817,\n+\t[BNXT_ULP_CLASS_HID_283db] = 1818,\n+\t[BNXT_ULP_CLASS_HID_30edb] = 1819,\n+\t[BNXT_ULP_CLASS_HID_399db] = 1820,\n+\t[BNXT_ULP_CLASS_HID_250db] = 1821,\n+\t[BNXT_ULP_CLASS_HID_2dbdb] = 1822,\n+\t[BNXT_ULP_CLASS_HID_309ef] = 1823,\n+\t[BNXT_ULP_CLASS_HID_394ef] = 1824,\n+\t[BNXT_ULP_CLASS_HID_206bf] = 1825,\n+\t[BNXT_ULP_CLASS_HID_291bf] = 1826,\n+\t[BNXT_ULP_CLASS_HID_31cbf] = 1827,\n+\t[BNXT_ULP_CLASS_HID_3a7bf] = 1828,\n+\t[BNXT_ULP_CLASS_HID_22f1f] = 1829,\n+\t[BNXT_ULP_CLASS_HID_2ba1f] = 1830,\n+\t[BNXT_ULP_CLASS_HID_3451f] = 1831,\n+\t[BNXT_ULP_CLASS_HID_3d01f] = 1832,\n+\t[BNXT_ULP_CLASS_HID_21c4f] = 1833,\n+\t[BNXT_ULP_CLASS_HID_2a74f] = 1834,\n+\t[BNXT_ULP_CLASS_HID_3324f] = 1835,\n+\t[BNXT_ULP_CLASS_HID_3bd4f] = 1836,\n+\t[BNXT_ULP_CLASS_HID_21703] = 1837,\n+\t[BNXT_ULP_CLASS_HID_2a203] = 1838,\n+\t[BNXT_ULP_CLASS_HID_32d03] = 1839,\n+\t[BNXT_ULP_CLASS_HID_3b803] = 1840,\n+\t[BNXT_ULP_CLASS_HID_22ad3] = 1841,\n+\t[BNXT_ULP_CLASS_HID_2b5d3] = 1842,\n+\t[BNXT_ULP_CLASS_HID_340d3] = 1843,\n+\t[BNXT_ULP_CLASS_HID_3cbd3] = 1844,\n+\t[BNXT_ULP_CLASS_HID_252b3] = 1845,\n+\t[BNXT_ULP_CLASS_HID_28147] = 1846,\n+\t[BNXT_ULP_CLASS_HID_30c47] = 1847,\n+\t[BNXT_ULP_CLASS_HID_39747] = 1848,\n+\t[BNXT_ULP_CLASS_HID_23fe3] = 1849,\n+\t[BNXT_ULP_CLASS_HID_2cae3] = 1850,\n+\t[BNXT_ULP_CLASS_HID_355e3] = 1851,\n+\t[BNXT_ULP_CLASS_HID_383b7] = 1852,\n+\t[BNXT_ULP_CLASS_HID_23ab7] = 1853,\n+\t[BNXT_ULP_CLASS_HID_2c5b7] = 1854,\n+\t[BNXT_ULP_CLASS_HID_350b7] = 1855,\n+\t[BNXT_ULP_CLASS_HID_3dbb7] = 1856,\n+\t[BNXT_ULP_CLASS_HID_24e47] = 1857,\n+\t[BNXT_ULP_CLASS_HID_2d947] = 1858,\n+\t[BNXT_ULP_CLASS_HID_3071b] = 1859,\n+\t[BNXT_ULP_CLASS_HID_3921b] = 1860,\n+\t[BNXT_ULP_CLASS_HID_2326f] = 1861,\n+\t[BNXT_ULP_CLASS_HID_2bd6f] = 1862,\n+\t[BNXT_ULP_CLASS_HID_3486f] = 1863,\n+\t[BNXT_ULP_CLASS_HID_3d36f] = 1864,\n+\t[BNXT_ULP_CLASS_HID_21f5f] = 1865,\n+\t[BNXT_ULP_CLASS_HID_2aa5f] = 1866,\n+\t[BNXT_ULP_CLASS_HID_3355f] = 1867,\n+\t[BNXT_ULP_CLASS_HID_3c05f] = 1868,\n+\t[BNXT_ULP_CLASS_HID_21a13] = 1869,\n+\t[BNXT_ULP_CLASS_HID_2a513] = 1870,\n+\t[BNXT_ULP_CLASS_HID_33013] = 1871,\n+\t[BNXT_ULP_CLASS_HID_3bb13] = 1872,\n+\t[BNXT_ULP_CLASS_HID_22d23] = 1873,\n+\t[BNXT_ULP_CLASS_HID_2b823] = 1874,\n+\t[BNXT_ULP_CLASS_HID_34323] = 1875,\n+\t[BNXT_ULP_CLASS_HID_3ce23] = 1876,\n+\t[BNXT_ULP_CLASS_HID_25583] = 1877,\n+\t[BNXT_ULP_CLASS_HID_28457] = 1878,\n+\t[BNXT_ULP_CLASS_HID_30f57] = 1879,\n+\t[BNXT_ULP_CLASS_HID_39a57] = 1880,\n+\t[BNXT_ULP_CLASS_HID_242f3] = 1881,\n+\t[BNXT_ULP_CLASS_HID_2cdf3] = 1882,\n+\t[BNXT_ULP_CLASS_HID_358f3] = 1883,\n+\t[BNXT_ULP_CLASS_HID_38687] = 1884,\n+\t[BNXT_ULP_CLASS_HID_23d87] = 1885,\n+\t[BNXT_ULP_CLASS_HID_2c887] = 1886,\n+\t[BNXT_ULP_CLASS_HID_35387] = 1887,\n+\t[BNXT_ULP_CLASS_HID_3825b] = 1888,\n+\t[BNXT_ULP_CLASS_HID_25157] = 1889,\n+\t[BNXT_ULP_CLASS_HID_2dc57] = 1890,\n+\t[BNXT_ULP_CLASS_HID_30a6b] = 1891,\n+\t[BNXT_ULP_CLASS_HID_3956b] = 1892,\n+\t[BNXT_ULP_CLASS_HID_22c53] = 1893,\n+\t[BNXT_ULP_CLASS_HID_2b753] = 1894,\n+\t[BNXT_ULP_CLASS_HID_34253] = 1895,\n+\t[BNXT_ULP_CLASS_HID_3cd53] = 1896,\n+\t[BNXT_ULP_CLASS_HID_21883] = 1897,\n+\t[BNXT_ULP_CLASS_HID_2a383] = 1898,\n+\t[BNXT_ULP_CLASS_HID_32e83] = 1899,\n+\t[BNXT_ULP_CLASS_HID_3b983] = 1900,\n+\t[BNXT_ULP_CLASS_HID_21457] = 1901,\n+\t[BNXT_ULP_CLASS_HID_29f57] = 1902,\n+\t[BNXT_ULP_CLASS_HID_32a57] = 1903,\n+\t[BNXT_ULP_CLASS_HID_3b557] = 1904,\n+\t[BNXT_ULP_CLASS_HID_22767] = 1905,\n+\t[BNXT_ULP_CLASS_HID_2b267] = 1906,\n+\t[BNXT_ULP_CLASS_HID_33d67] = 1907,\n+\t[BNXT_ULP_CLASS_HID_3c867] = 1908,\n+\t[BNXT_ULP_CLASS_HID_24fc7] = 1909,\n+\t[BNXT_ULP_CLASS_HID_2dac7] = 1910,\n+\t[BNXT_ULP_CLASS_HID_3089b] = 1911,\n+\t[BNXT_ULP_CLASS_HID_3939b] = 1912,\n+\t[BNXT_ULP_CLASS_HID_23c37] = 1913,\n+\t[BNXT_ULP_CLASS_HID_2c737] = 1914,\n+\t[BNXT_ULP_CLASS_HID_35237] = 1915,\n+\t[BNXT_ULP_CLASS_HID_380cb] = 1916,\n+\t[BNXT_ULP_CLASS_HID_237cb] = 1917,\n+\t[BNXT_ULP_CLASS_HID_2c2cb] = 1918,\n+\t[BNXT_ULP_CLASS_HID_34dcb] = 1919,\n+\t[BNXT_ULP_CLASS_HID_3d8cb] = 1920,\n+\t[BNXT_ULP_CLASS_HID_24a9b] = 1921,\n+\t[BNXT_ULP_CLASS_HID_2d59b] = 1922,\n+\t[BNXT_ULP_CLASS_HID_303af] = 1923,\n+\t[BNXT_ULP_CLASS_HID_38eaf] = 1924,\n+\t[BNXT_ULP_CLASS_HID_253b] = 1925,\n+\t[BNXT_ULP_CLASS_HID_2bf7] = 1926,\n+\t[BNXT_ULP_CLASS_HID_4f6b] = 1927,\n+\t[BNXT_ULP_CLASS_HID_1653] = 1928,\n+\t[BNXT_ULP_CLASS_HID_39c7] = 1929,\n+\t[BNXT_ULP_CLASS_HID_48af] = 1930,\n+\t[BNXT_ULP_CLASS_HID_0f97] = 1931,\n+\t[BNXT_ULP_CLASS_HID_330b] = 1932,\n+\t[BNXT_ULP_CLASS_HID_374e] = 1933,\n+\t[BNXT_ULP_CLASS_HID_11ee] = 1934,\n+\t[BNXT_ULP_CLASS_HID_423a] = 1935,\n+\t[BNXT_ULP_CLASS_HID_0cd6] = 1936,\n+\t[BNXT_ULP_CLASS_HID_310a] = 1937,\n+\t[BNXT_ULP_CLASS_HID_469e] = 1938,\n+\t[BNXT_ULP_CLASS_HID_5ce6] = 1939,\n+\t[BNXT_ULP_CLASS_HID_0692] = 1940,\n+\t[BNXT_ULP_CLASS_HID_1c7e] = 1941,\n+\t[BNXT_ULP_CLASS_HID_55c2] = 1942,\n+\t[BNXT_ULP_CLASS_HID_2b2a] = 1943,\n+\t[BNXT_ULP_CLASS_HID_15c6] = 1944,\n+\t[BNXT_ULP_CLASS_HID_163a] = 1945,\n+\t[BNXT_ULP_CLASS_HID_2f8e] = 1946,\n+\t[BNXT_ULP_CLASS_HID_2516] = 1947,\n+\t[BNXT_ULP_CLASS_HID_4b76] = 1948,\n+\t[BNXT_ULP_CLASS_HID_10e6] = 1949,\n+\t[BNXT_ULP_CLASS_HID_264a] = 1950,\n+\t[BNXT_ULP_CLASS_HID_3fd2] = 1951,\n+\t[BNXT_ULP_CLASS_HID_4532] = 1952,\n+\t[BNXT_ULP_CLASS_HID_4996] = 1953,\n+\t[BNXT_ULP_CLASS_HID_2036] = 1954,\n+\t[BNXT_ULP_CLASS_HID_399e] = 1955,\n+\t[BNXT_ULP_CLASS_HID_5ffe] = 1956,\n+\t[BNXT_ULP_CLASS_HID_34fe] = 1957,\n+\t[BNXT_ULP_CLASS_HID_3a32] = 1958,\n+\t[BNXT_ULP_CLASS_HID_376e] = 1959,\n+\t[BNXT_ULP_CLASS_HID_12d6e] = 1960,\n+\t[BNXT_ULP_CLASS_HID_2436e] = 1961,\n+\t[BNXT_ULP_CLASS_HID_31dba] = 1962,\n+\t[BNXT_ULP_CLASS_HID_11ce] = 1963,\n+\t[BNXT_ULP_CLASS_HID_107ce] = 1964,\n+\t[BNXT_ULP_CLASS_HID_23dce] = 1965,\n+\t[BNXT_ULP_CLASS_HID_353ce] = 1966,\n+\t[BNXT_ULP_CLASS_HID_421a] = 1967,\n+\t[BNXT_ULP_CLASS_HID_11d56] = 1968,\n+\t[BNXT_ULP_CLASS_HID_23356] = 1969,\n+\t[BNXT_ULP_CLASS_HID_32956] = 1970,\n+\t[BNXT_ULP_CLASS_HID_0cf6] = 1971,\n+\t[BNXT_ULP_CLASS_HID_122f6] = 1972,\n+\t[BNXT_ULP_CLASS_HID_258f6] = 1973,\n+\t[BNXT_ULP_CLASS_HID_313c2] = 1974,\n+\t[BNXT_ULP_CLASS_HID_312a] = 1975,\n+\t[BNXT_ULP_CLASS_HID_1272a] = 1976,\n+\t[BNXT_ULP_CLASS_HID_25d2a] = 1977,\n+\t[BNXT_ULP_CLASS_HID_31466] = 1978,\n+\t[BNXT_ULP_CLASS_HID_46be] = 1979,\n+\t[BNXT_ULP_CLASS_HID_1018a] = 1980,\n+\t[BNXT_ULP_CLASS_HID_2378a] = 1981,\n+\t[BNXT_ULP_CLASS_HID_32d8a] = 1982,\n+\t[BNXT_ULP_CLASS_HID_5cc6] = 1983,\n+\t[BNXT_ULP_CLASS_HID_11712] = 1984,\n+\t[BNXT_ULP_CLASS_HID_20d12] = 1985,\n+\t[BNXT_ULP_CLASS_HID_32312] = 1986,\n+\t[BNXT_ULP_CLASS_HID_06b2] = 1987,\n+\t[BNXT_ULP_CLASS_HID_13cb2] = 1988,\n+\t[BNXT_ULP_CLASS_HID_252b2] = 1989,\n+\t[BNXT_ULP_CLASS_HID_348b2] = 1990,\n+\t[BNXT_ULP_CLASS_HID_1c5e] = 1991,\n+\t[BNXT_ULP_CLASS_HID_1325e] = 1992,\n+\t[BNXT_ULP_CLASS_HID_2285e] = 1993,\n+\t[BNXT_ULP_CLASS_HID_35e5e] = 1994,\n+\t[BNXT_ULP_CLASS_HID_55e2] = 1995,\n+\t[BNXT_ULP_CLASS_HID_14be2] = 1996,\n+\t[BNXT_ULP_CLASS_HID_2023e] = 1997,\n+\t[BNXT_ULP_CLASS_HID_3383e] = 1998,\n+\t[BNXT_ULP_CLASS_HID_2b0a] = 1999,\n+\t[BNXT_ULP_CLASS_HID_1410a] = 2000,\n+\t[BNXT_ULP_CLASS_HID_21846] = 2001,\n+\t[BNXT_ULP_CLASS_HID_30e46] = 2002,\n+\t[BNXT_ULP_CLASS_HID_15e6] = 2003,\n+\t[BNXT_ULP_CLASS_HID_10be6] = 2004,\n+\t[BNXT_ULP_CLASS_HID_221e6] = 2005,\n+\t[BNXT_ULP_CLASS_HID_357e6] = 2006,\n+\t[BNXT_ULP_CLASS_HID_161a] = 2007,\n+\t[BNXT_ULP_CLASS_HID_10c1a] = 2008,\n+\t[BNXT_ULP_CLASS_HID_2221a] = 2009,\n+\t[BNXT_ULP_CLASS_HID_3581a] = 2010,\n+\t[BNXT_ULP_CLASS_HID_2fae] = 2011,\n+\t[BNXT_ULP_CLASS_HID_145ae] = 2012,\n+\t[BNXT_ULP_CLASS_HID_21cfa] = 2013,\n+\t[BNXT_ULP_CLASS_HID_332fa] = 2014,\n+\t[BNXT_ULP_CLASS_HID_2536] = 2015,\n+\t[BNXT_ULP_CLASS_HID_15b36] = 2016,\n+\t[BNXT_ULP_CLASS_HID_21202] = 2017,\n+\t[BNXT_ULP_CLASS_HID_30802] = 2018,\n+\t[BNXT_ULP_CLASS_HID_4b56] = 2019,\n+\t[BNXT_ULP_CLASS_HID_105a2] = 2020,\n+\t[BNXT_ULP_CLASS_HID_23ba2] = 2021,\n+\t[BNXT_ULP_CLASS_HID_351a2] = 2022,\n+\t[BNXT_ULP_CLASS_HID_10c6] = 2023,\n+\t[BNXT_ULP_CLASS_HID_106c6] = 2024,\n+\t[BNXT_ULP_CLASS_HID_23cc6] = 2025,\n+\t[BNXT_ULP_CLASS_HID_352c6] = 2026,\n+\t[BNXT_ULP_CLASS_HID_266a] = 2027,\n+\t[BNXT_ULP_CLASS_HID_15c6a] = 2028,\n+\t[BNXT_ULP_CLASS_HID_216a6] = 2029,\n+\t[BNXT_ULP_CLASS_HID_30ca6] = 2030,\n+\t[BNXT_ULP_CLASS_HID_3ff2] = 2031,\n+\t[BNXT_ULP_CLASS_HID_155f2] = 2032,\n+\t[BNXT_ULP_CLASS_HID_24bf2] = 2033,\n+\t[BNXT_ULP_CLASS_HID_302ce] = 2034,\n+\t[BNXT_ULP_CLASS_HID_4512] = 2035,\n+\t[BNXT_ULP_CLASS_HID_11c6e] = 2036,\n+\t[BNXT_ULP_CLASS_HID_2326e] = 2037,\n+\t[BNXT_ULP_CLASS_HID_3286e] = 2038,\n+\t[BNXT_ULP_CLASS_HID_49b6] = 2039,\n+\t[BNXT_ULP_CLASS_HID_10082] = 2040,\n+\t[BNXT_ULP_CLASS_HID_23682] = 2041,\n+\t[BNXT_ULP_CLASS_HID_32c82] = 2042,\n+\t[BNXT_ULP_CLASS_HID_2016] = 2043,\n+\t[BNXT_ULP_CLASS_HID_15616] = 2044,\n+\t[BNXT_ULP_CLASS_HID_21162] = 2045,\n+\t[BNXT_ULP_CLASS_HID_30762] = 2046,\n+\t[BNXT_ULP_CLASS_HID_39be] = 2047,\n+\t[BNXT_ULP_CLASS_HID_12fbe] = 2048,\n+\t[BNXT_ULP_CLASS_HID_245be] = 2049,\n+\t[BNXT_ULP_CLASS_HID_31c8a] = 2050,\n+\t[BNXT_ULP_CLASS_HID_5fde] = 2051,\n+\t[BNXT_ULP_CLASS_HID_1162a] = 2052,\n+\t[BNXT_ULP_CLASS_HID_20c2a] = 2053,\n+\t[BNXT_ULP_CLASS_HID_3222a] = 2054,\n+\t[BNXT_ULP_CLASS_HID_34de] = 2055,\n+\t[BNXT_ULP_CLASS_HID_3a12] = 2056,\n+\t[BNXT_ULP_CLASS_HID_370e] = 2057,\n+\t[BNXT_ULP_CLASS_HID_12d0e] = 2058,\n+\t[BNXT_ULP_CLASS_HID_2430e] = 2059,\n+\t[BNXT_ULP_CLASS_HID_31dda] = 2060,\n+\t[BNXT_ULP_CLASS_HID_11ae] = 2061,\n+\t[BNXT_ULP_CLASS_HID_107ae] = 2062,\n+\t[BNXT_ULP_CLASS_HID_23dae] = 2063,\n+\t[BNXT_ULP_CLASS_HID_353ae] = 2064,\n+\t[BNXT_ULP_CLASS_HID_427a] = 2065,\n+\t[BNXT_ULP_CLASS_HID_11d36] = 2066,\n+\t[BNXT_ULP_CLASS_HID_23336] = 2067,\n+\t[BNXT_ULP_CLASS_HID_32936] = 2068,\n+\t[BNXT_ULP_CLASS_HID_0c96] = 2069,\n+\t[BNXT_ULP_CLASS_HID_12296] = 2070,\n+\t[BNXT_ULP_CLASS_HID_25896] = 2071,\n+\t[BNXT_ULP_CLASS_HID_313a2] = 2072,\n+\t[BNXT_ULP_CLASS_HID_314a] = 2073,\n+\t[BNXT_ULP_CLASS_HID_1274a] = 2074,\n+\t[BNXT_ULP_CLASS_HID_25d4a] = 2075,\n+\t[BNXT_ULP_CLASS_HID_31406] = 2076,\n+\t[BNXT_ULP_CLASS_HID_46de] = 2077,\n+\t[BNXT_ULP_CLASS_HID_101ea] = 2078,\n+\t[BNXT_ULP_CLASS_HID_237ea] = 2079,\n+\t[BNXT_ULP_CLASS_HID_32dea] = 2080,\n+\t[BNXT_ULP_CLASS_HID_5ca6] = 2081,\n+\t[BNXT_ULP_CLASS_HID_11772] = 2082,\n+\t[BNXT_ULP_CLASS_HID_20d72] = 2083,\n+\t[BNXT_ULP_CLASS_HID_32372] = 2084,\n+\t[BNXT_ULP_CLASS_HID_06d2] = 2085,\n+\t[BNXT_ULP_CLASS_HID_13cd2] = 2086,\n+\t[BNXT_ULP_CLASS_HID_252d2] = 2087,\n+\t[BNXT_ULP_CLASS_HID_348d2] = 2088,\n+\t[BNXT_ULP_CLASS_HID_1c3e] = 2089,\n+\t[BNXT_ULP_CLASS_HID_1323e] = 2090,\n+\t[BNXT_ULP_CLASS_HID_2283e] = 2091,\n+\t[BNXT_ULP_CLASS_HID_35e3e] = 2092,\n+\t[BNXT_ULP_CLASS_HID_5582] = 2093,\n+\t[BNXT_ULP_CLASS_HID_14b82] = 2094,\n+\t[BNXT_ULP_CLASS_HID_2025e] = 2095,\n+\t[BNXT_ULP_CLASS_HID_3385e] = 2096,\n+\t[BNXT_ULP_CLASS_HID_2b6a] = 2097,\n+\t[BNXT_ULP_CLASS_HID_1416a] = 2098,\n+\t[BNXT_ULP_CLASS_HID_21826] = 2099,\n+\t[BNXT_ULP_CLASS_HID_30e26] = 2100,\n+\t[BNXT_ULP_CLASS_HID_1586] = 2101,\n+\t[BNXT_ULP_CLASS_HID_10b86] = 2102,\n+\t[BNXT_ULP_CLASS_HID_22186] = 2103,\n+\t[BNXT_ULP_CLASS_HID_35786] = 2104,\n+\t[BNXT_ULP_CLASS_HID_167a] = 2105,\n+\t[BNXT_ULP_CLASS_HID_10c7a] = 2106,\n+\t[BNXT_ULP_CLASS_HID_2227a] = 2107,\n+\t[BNXT_ULP_CLASS_HID_3587a] = 2108,\n+\t[BNXT_ULP_CLASS_HID_2fce] = 2109,\n+\t[BNXT_ULP_CLASS_HID_145ce] = 2110,\n+\t[BNXT_ULP_CLASS_HID_21c9a] = 2111,\n+\t[BNXT_ULP_CLASS_HID_3329a] = 2112,\n+\t[BNXT_ULP_CLASS_HID_2556] = 2113,\n+\t[BNXT_ULP_CLASS_HID_15b56] = 2114,\n+\t[BNXT_ULP_CLASS_HID_21262] = 2115,\n+\t[BNXT_ULP_CLASS_HID_30862] = 2116,\n+\t[BNXT_ULP_CLASS_HID_4b36] = 2117,\n+\t[BNXT_ULP_CLASS_HID_105c2] = 2118,\n+\t[BNXT_ULP_CLASS_HID_23bc2] = 2119,\n+\t[BNXT_ULP_CLASS_HID_351c2] = 2120,\n+\t[BNXT_ULP_CLASS_HID_10a6] = 2121,\n+\t[BNXT_ULP_CLASS_HID_106a6] = 2122,\n+\t[BNXT_ULP_CLASS_HID_23ca6] = 2123,\n+\t[BNXT_ULP_CLASS_HID_352a6] = 2124,\n+\t[BNXT_ULP_CLASS_HID_260a] = 2125,\n+\t[BNXT_ULP_CLASS_HID_15c0a] = 2126,\n+\t[BNXT_ULP_CLASS_HID_216c6] = 2127,\n+\t[BNXT_ULP_CLASS_HID_30cc6] = 2128,\n+\t[BNXT_ULP_CLASS_HID_3f92] = 2129,\n+\t[BNXT_ULP_CLASS_HID_15592] = 2130,\n+\t[BNXT_ULP_CLASS_HID_24b92] = 2131,\n+\t[BNXT_ULP_CLASS_HID_302ae] = 2132,\n+\t[BNXT_ULP_CLASS_HID_4572] = 2133,\n+\t[BNXT_ULP_CLASS_HID_11c0e] = 2134,\n+\t[BNXT_ULP_CLASS_HID_2320e] = 2135,\n+\t[BNXT_ULP_CLASS_HID_3280e] = 2136,\n+\t[BNXT_ULP_CLASS_HID_49d6] = 2137,\n+\t[BNXT_ULP_CLASS_HID_100e2] = 2138,\n+\t[BNXT_ULP_CLASS_HID_236e2] = 2139,\n+\t[BNXT_ULP_CLASS_HID_32ce2] = 2140,\n+\t[BNXT_ULP_CLASS_HID_2076] = 2141,\n+\t[BNXT_ULP_CLASS_HID_15676] = 2142,\n+\t[BNXT_ULP_CLASS_HID_21102] = 2143,\n+\t[BNXT_ULP_CLASS_HID_30702] = 2144,\n+\t[BNXT_ULP_CLASS_HID_39de] = 2145,\n+\t[BNXT_ULP_CLASS_HID_12fde] = 2146,\n+\t[BNXT_ULP_CLASS_HID_245de] = 2147,\n+\t[BNXT_ULP_CLASS_HID_31cea] = 2148,\n+\t[BNXT_ULP_CLASS_HID_5fbe] = 2149,\n+\t[BNXT_ULP_CLASS_HID_1164a] = 2150,\n+\t[BNXT_ULP_CLASS_HID_20c4a] = 2151,\n+\t[BNXT_ULP_CLASS_HID_3224a] = 2152,\n+\t[BNXT_ULP_CLASS_HID_34be] = 2153,\n+\t[BNXT_ULP_CLASS_HID_3a72] = 2154,\n+\t[BNXT_ULP_CLASS_HID_09ea] = 2155,\n+\t[BNXT_ULP_CLASS_HID_2912] = 2156,\n+\t[BNXT_ULP_CLASS_HID_03b2] = 2157,\n+\t[BNXT_ULP_CLASS_HID_5f7e] = 2158,\n+\t[BNXT_ULP_CLASS_HID_03a6] = 2159,\n+\t[BNXT_ULP_CLASS_HID_23ce] = 2160,\n+\t[BNXT_ULP_CLASS_HID_1a6e] = 2161,\n+\t[BNXT_ULP_CLASS_HID_593a] = 2162,\n+\t[BNXT_ULP_CLASS_HID_4dce] = 2163,\n+\t[BNXT_ULP_CLASS_HID_0e02] = 2164,\n+\t[BNXT_ULP_CLASS_HID_4796] = 2165,\n+\t[BNXT_ULP_CLASS_HID_246e] = 2166,\n+\t[BNXT_ULP_CLASS_HID_478a] = 2167,\n+\t[BNXT_ULP_CLASS_HID_08fe] = 2168,\n+\t[BNXT_ULP_CLASS_HID_5e52] = 2169,\n+\t[BNXT_ULP_CLASS_HID_3e2a] = 2170,\n+\t[BNXT_ULP_CLASS_HID_5e46] = 2171,\n+\t[BNXT_ULP_CLASS_HID_02ba] = 2172,\n+\t[BNXT_ULP_CLASS_HID_580e] = 2173,\n+\t[BNXT_ULP_CLASS_HID_38e6] = 2174,\n+\t[BNXT_ULP_CLASS_HID_5802] = 2175,\n+\t[BNXT_ULP_CLASS_HID_1d76] = 2176,\n+\t[BNXT_ULP_CLASS_HID_52ca] = 2177,\n+\t[BNXT_ULP_CLASS_HID_32a2] = 2178,\n+\t[BNXT_ULP_CLASS_HID_34f6] = 2179,\n+\t[BNXT_ULP_CLASS_HID_3a3a] = 2180,\n+\t[BNXT_ULP_CLASS_HID_09ca] = 2181,\n+\t[BNXT_ULP_CLASS_HID_0216] = 2182,\n+\t[BNXT_ULP_CLASS_HID_1f62] = 2183,\n+\t[BNXT_ULP_CLASS_HID_1bae] = 2184,\n+\t[BNXT_ULP_CLASS_HID_2932] = 2185,\n+\t[BNXT_ULP_CLASS_HID_227e] = 2186,\n+\t[BNXT_ULP_CLASS_HID_3f4a] = 2187,\n+\t[BNXT_ULP_CLASS_HID_3b96] = 2188,\n+\t[BNXT_ULP_CLASS_HID_0392] = 2189,\n+\t[BNXT_ULP_CLASS_HID_1cde] = 2190,\n+\t[BNXT_ULP_CLASS_HID_192a] = 2191,\n+\t[BNXT_ULP_CLASS_HID_1276] = 2192,\n+\t[BNXT_ULP_CLASS_HID_5f5e] = 2193,\n+\t[BNXT_ULP_CLASS_HID_5baa] = 2194,\n+\t[BNXT_ULP_CLASS_HID_54f6] = 2195,\n+\t[BNXT_ULP_CLASS_HID_51c2] = 2196,\n+\t[BNXT_ULP_CLASS_HID_0386] = 2197,\n+\t[BNXT_ULP_CLASS_HID_1cd2] = 2198,\n+\t[BNXT_ULP_CLASS_HID_191e] = 2199,\n+\t[BNXT_ULP_CLASS_HID_126a] = 2200,\n+\t[BNXT_ULP_CLASS_HID_23ee] = 2201,\n+\t[BNXT_ULP_CLASS_HID_3c3a] = 2202,\n+\t[BNXT_ULP_CLASS_HID_3906] = 2203,\n+\t[BNXT_ULP_CLASS_HID_3252] = 2204,\n+\t[BNXT_ULP_CLASS_HID_1a4e] = 2205,\n+\t[BNXT_ULP_CLASS_HID_169a] = 2206,\n+\t[BNXT_ULP_CLASS_HID_13e6] = 2207,\n+\t[BNXT_ULP_CLASS_HID_4be6] = 2208,\n+\t[BNXT_ULP_CLASS_HID_591a] = 2209,\n+\t[BNXT_ULP_CLASS_HID_5266] = 2210,\n+\t[BNXT_ULP_CLASS_HID_2eb2] = 2211,\n+\t[BNXT_ULP_CLASS_HID_2bfe] = 2212,\n+\t[BNXT_ULP_CLASS_HID_4dee] = 2213,\n+\t[BNXT_ULP_CLASS_HID_463a] = 2214,\n+\t[BNXT_ULP_CLASS_HID_4306] = 2215,\n+\t[BNXT_ULP_CLASS_HID_5c52] = 2216,\n+\t[BNXT_ULP_CLASS_HID_0e22] = 2217,\n+\t[BNXT_ULP_CLASS_HID_0b6e] = 2218,\n+\t[BNXT_ULP_CLASS_HID_07ba] = 2219,\n+\t[BNXT_ULP_CLASS_HID_0086] = 2220,\n+\t[BNXT_ULP_CLASS_HID_47b6] = 2221,\n+\t[BNXT_ULP_CLASS_HID_4082] = 2222,\n+\t[BNXT_ULP_CLASS_HID_5dce] = 2223,\n+\t[BNXT_ULP_CLASS_HID_561a] = 2224,\n+\t[BNXT_ULP_CLASS_HID_244e] = 2225,\n+\t[BNXT_ULP_CLASS_HID_209a] = 2226,\n+\t[BNXT_ULP_CLASS_HID_3de6] = 2227,\n+\t[BNXT_ULP_CLASS_HID_3632] = 2228,\n+\t[BNXT_ULP_CLASS_HID_47aa] = 2229,\n+\t[BNXT_ULP_CLASS_HID_40f6] = 2230,\n+\t[BNXT_ULP_CLASS_HID_5dc2] = 2231,\n+\t[BNXT_ULP_CLASS_HID_560e] = 2232,\n+\t[BNXT_ULP_CLASS_HID_08de] = 2233,\n+\t[BNXT_ULP_CLASS_HID_052a] = 2234,\n+\t[BNXT_ULP_CLASS_HID_1e76] = 2235,\n+\t[BNXT_ULP_CLASS_HID_1b42] = 2236,\n+\t[BNXT_ULP_CLASS_HID_5e72] = 2237,\n+\t[BNXT_ULP_CLASS_HID_5abe] = 2238,\n+\t[BNXT_ULP_CLASS_HID_578a] = 2239,\n+\t[BNXT_ULP_CLASS_HID_50d6] = 2240,\n+\t[BNXT_ULP_CLASS_HID_3e0a] = 2241,\n+\t[BNXT_ULP_CLASS_HID_3b56] = 2242,\n+\t[BNXT_ULP_CLASS_HID_37a2] = 2243,\n+\t[BNXT_ULP_CLASS_HID_30ee] = 2244,\n+\t[BNXT_ULP_CLASS_HID_5e66] = 2245,\n+\t[BNXT_ULP_CLASS_HID_5ab2] = 2246,\n+\t[BNXT_ULP_CLASS_HID_57fe] = 2247,\n+\t[BNXT_ULP_CLASS_HID_50ca] = 2248,\n+\t[BNXT_ULP_CLASS_HID_029a] = 2249,\n+\t[BNXT_ULP_CLASS_HID_1fe6] = 2250,\n+\t[BNXT_ULP_CLASS_HID_1832] = 2251,\n+\t[BNXT_ULP_CLASS_HID_157e] = 2252,\n+\t[BNXT_ULP_CLASS_HID_582e] = 2253,\n+\t[BNXT_ULP_CLASS_HID_557a] = 2254,\n+\t[BNXT_ULP_CLASS_HID_2e46] = 2255,\n+\t[BNXT_ULP_CLASS_HID_2a92] = 2256,\n+\t[BNXT_ULP_CLASS_HID_38c6] = 2257,\n+\t[BNXT_ULP_CLASS_HID_3512] = 2258,\n+\t[BNXT_ULP_CLASS_HID_0e5e] = 2259,\n+\t[BNXT_ULP_CLASS_HID_0aaa] = 2260,\n+\t[BNXT_ULP_CLASS_HID_5822] = 2261,\n+\t[BNXT_ULP_CLASS_HID_556e] = 2262,\n+\t[BNXT_ULP_CLASS_HID_51ba] = 2263,\n+\t[BNXT_ULP_CLASS_HID_2a86] = 2264,\n+\t[BNXT_ULP_CLASS_HID_1d56] = 2265,\n+\t[BNXT_ULP_CLASS_HID_19a2] = 2266,\n+\t[BNXT_ULP_CLASS_HID_12ee] = 2267,\n+\t[BNXT_ULP_CLASS_HID_4aee] = 2268,\n+\t[BNXT_ULP_CLASS_HID_52ea] = 2269,\n+\t[BNXT_ULP_CLASS_HID_2f36] = 2270,\n+\t[BNXT_ULP_CLASS_HID_2802] = 2271,\n+\t[BNXT_ULP_CLASS_HID_254e] = 2272,\n+\t[BNXT_ULP_CLASS_HID_3282] = 2273,\n+\t[BNXT_ULP_CLASS_HID_0fce] = 2274,\n+\t[BNXT_ULP_CLASS_HID_081a] = 2275,\n+\t[BNXT_ULP_CLASS_HID_0566] = 2276,\n+\t[BNXT_ULP_CLASS_HID_34d6] = 2277,\n+\t[BNXT_ULP_CLASS_HID_3a1a] = 2278,\n+\t[BNXT_ULP_CLASS_HID_09aa] = 2279,\n+\t[BNXT_ULP_CLASS_HID_0276] = 2280,\n+\t[BNXT_ULP_CLASS_HID_1f02] = 2281,\n+\t[BNXT_ULP_CLASS_HID_1bce] = 2282,\n+\t[BNXT_ULP_CLASS_HID_2952] = 2283,\n+\t[BNXT_ULP_CLASS_HID_221e] = 2284,\n+\t[BNXT_ULP_CLASS_HID_3f2a] = 2285,\n+\t[BNXT_ULP_CLASS_HID_3bf6] = 2286,\n+\t[BNXT_ULP_CLASS_HID_03f2] = 2287,\n+\t[BNXT_ULP_CLASS_HID_1cbe] = 2288,\n+\t[BNXT_ULP_CLASS_HID_194a] = 2289,\n+\t[BNXT_ULP_CLASS_HID_1216] = 2290,\n+\t[BNXT_ULP_CLASS_HID_5f3e] = 2291,\n+\t[BNXT_ULP_CLASS_HID_5bca] = 2292,\n+\t[BNXT_ULP_CLASS_HID_5496] = 2293,\n+\t[BNXT_ULP_CLASS_HID_51a2] = 2294,\n+\t[BNXT_ULP_CLASS_HID_03e6] = 2295,\n+\t[BNXT_ULP_CLASS_HID_1cb2] = 2296,\n+\t[BNXT_ULP_CLASS_HID_197e] = 2297,\n+\t[BNXT_ULP_CLASS_HID_120a] = 2298,\n+\t[BNXT_ULP_CLASS_HID_238e] = 2299,\n+\t[BNXT_ULP_CLASS_HID_3c5a] = 2300,\n+\t[BNXT_ULP_CLASS_HID_3966] = 2301,\n+\t[BNXT_ULP_CLASS_HID_3232] = 2302,\n+\t[BNXT_ULP_CLASS_HID_1a2e] = 2303,\n+\t[BNXT_ULP_CLASS_HID_16fa] = 2304,\n+\t[BNXT_ULP_CLASS_HID_1386] = 2305,\n+\t[BNXT_ULP_CLASS_HID_4b86] = 2306,\n+\t[BNXT_ULP_CLASS_HID_597a] = 2307,\n+\t[BNXT_ULP_CLASS_HID_5206] = 2308,\n+\t[BNXT_ULP_CLASS_HID_2ed2] = 2309,\n+\t[BNXT_ULP_CLASS_HID_2b9e] = 2310,\n+\t[BNXT_ULP_CLASS_HID_4d8e] = 2311,\n+\t[BNXT_ULP_CLASS_HID_465a] = 2312,\n+\t[BNXT_ULP_CLASS_HID_4366] = 2313,\n+\t[BNXT_ULP_CLASS_HID_5c32] = 2314,\n+\t[BNXT_ULP_CLASS_HID_0e42] = 2315,\n+\t[BNXT_ULP_CLASS_HID_0b0e] = 2316,\n+\t[BNXT_ULP_CLASS_HID_07da] = 2317,\n+\t[BNXT_ULP_CLASS_HID_00e6] = 2318,\n+\t[BNXT_ULP_CLASS_HID_47d6] = 2319,\n+\t[BNXT_ULP_CLASS_HID_40e2] = 2320,\n+\t[BNXT_ULP_CLASS_HID_5dae] = 2321,\n+\t[BNXT_ULP_CLASS_HID_567a] = 2322,\n+\t[BNXT_ULP_CLASS_HID_242e] = 2323,\n+\t[BNXT_ULP_CLASS_HID_20fa] = 2324,\n+\t[BNXT_ULP_CLASS_HID_3d86] = 2325,\n+\t[BNXT_ULP_CLASS_HID_3652] = 2326,\n+\t[BNXT_ULP_CLASS_HID_47ca] = 2327,\n+\t[BNXT_ULP_CLASS_HID_4096] = 2328,\n+\t[BNXT_ULP_CLASS_HID_5da2] = 2329,\n+\t[BNXT_ULP_CLASS_HID_566e] = 2330,\n+\t[BNXT_ULP_CLASS_HID_08be] = 2331,\n+\t[BNXT_ULP_CLASS_HID_054a] = 2332,\n+\t[BNXT_ULP_CLASS_HID_1e16] = 2333,\n+\t[BNXT_ULP_CLASS_HID_1b22] = 2334,\n+\t[BNXT_ULP_CLASS_HID_5e12] = 2335,\n+\t[BNXT_ULP_CLASS_HID_5ade] = 2336,\n+\t[BNXT_ULP_CLASS_HID_57ea] = 2337,\n+\t[BNXT_ULP_CLASS_HID_50b6] = 2338,\n+\t[BNXT_ULP_CLASS_HID_3e6a] = 2339,\n+\t[BNXT_ULP_CLASS_HID_3b36] = 2340,\n+\t[BNXT_ULP_CLASS_HID_37c2] = 2341,\n+\t[BNXT_ULP_CLASS_HID_308e] = 2342,\n+\t[BNXT_ULP_CLASS_HID_5e06] = 2343,\n+\t[BNXT_ULP_CLASS_HID_5ad2] = 2344,\n+\t[BNXT_ULP_CLASS_HID_579e] = 2345,\n+\t[BNXT_ULP_CLASS_HID_50aa] = 2346,\n+\t[BNXT_ULP_CLASS_HID_02fa] = 2347,\n+\t[BNXT_ULP_CLASS_HID_1f86] = 2348,\n+\t[BNXT_ULP_CLASS_HID_1852] = 2349,\n+\t[BNXT_ULP_CLASS_HID_151e] = 2350,\n+\t[BNXT_ULP_CLASS_HID_584e] = 2351,\n+\t[BNXT_ULP_CLASS_HID_551a] = 2352,\n+\t[BNXT_ULP_CLASS_HID_2e26] = 2353,\n+\t[BNXT_ULP_CLASS_HID_2af2] = 2354,\n+\t[BNXT_ULP_CLASS_HID_38a6] = 2355,\n+\t[BNXT_ULP_CLASS_HID_3572] = 2356,\n+\t[BNXT_ULP_CLASS_HID_0e3e] = 2357,\n+\t[BNXT_ULP_CLASS_HID_0aca] = 2358,\n+\t[BNXT_ULP_CLASS_HID_5842] = 2359,\n+\t[BNXT_ULP_CLASS_HID_550e] = 2360,\n+\t[BNXT_ULP_CLASS_HID_51da] = 2361,\n+\t[BNXT_ULP_CLASS_HID_2ae6] = 2362,\n+\t[BNXT_ULP_CLASS_HID_1d36] = 2363,\n+\t[BNXT_ULP_CLASS_HID_19c2] = 2364,\n+\t[BNXT_ULP_CLASS_HID_128e] = 2365,\n+\t[BNXT_ULP_CLASS_HID_4a8e] = 2366,\n+\t[BNXT_ULP_CLASS_HID_528a] = 2367,\n+\t[BNXT_ULP_CLASS_HID_2f56] = 2368,\n+\t[BNXT_ULP_CLASS_HID_2862] = 2369,\n+\t[BNXT_ULP_CLASS_HID_252e] = 2370,\n+\t[BNXT_ULP_CLASS_HID_32e2] = 2371,\n+\t[BNXT_ULP_CLASS_HID_0fae] = 2372,\n+\t[BNXT_ULP_CLASS_HID_087a] = 2373,\n+\t[BNXT_ULP_CLASS_HID_0506] = 2374,\n+\t[BNXT_ULP_CLASS_HID_34b6] = 2375,\n+\t[BNXT_ULP_CLASS_HID_3a7a] = 2376,\n+\t[BNXT_ULP_CLASS_HID_a73c] = 2377,\n+\t[BNXT_ULP_CLASS_HID_a040] = 2378,\n+\t[BNXT_ULP_CLASS_HID_1d640] = 2379,\n+\t[BNXT_ULP_CLASS_HID_1dd3c] = 2380,\n+\t[BNXT_ULP_CLASS_HID_cba0] = 2381,\n+\t[BNXT_ULP_CLASS_HID_c4f4] = 2382,\n+\t[BNXT_ULP_CLASS_HID_19f38] = 2383,\n+\t[BNXT_ULP_CLASS_HID_182f4] = 2384,\n+\t[BNXT_ULP_CLASS_HID_b098] = 2385,\n+\t[BNXT_ULP_CLASS_HID_8dac] = 2386,\n+\t[BNXT_ULP_CLASS_HID_1a3ac] = 2387,\n+\t[BNXT_ULP_CLASS_HID_1a698] = 2388,\n+\t[BNXT_ULP_CLASS_HID_d50c] = 2389,\n+\t[BNXT_ULP_CLASS_HID_ae50] = 2390,\n+\t[BNXT_ULP_CLASS_HID_1c450] = 2391,\n+\t[BNXT_ULP_CLASS_HID_1cb0c] = 2392,\n+\t[BNXT_ULP_CLASS_HID_a1f0] = 2393,\n+\t[BNXT_ULP_CLASS_HID_ba04] = 2394,\n+\t[BNXT_ULP_CLASS_HID_1d004] = 2395,\n+\t[BNXT_ULP_CLASS_HID_1d7f0] = 2396,\n+\t[BNXT_ULP_CLASS_HID_c264] = 2397,\n+\t[BNXT_ULP_CLASS_HID_dea8] = 2398,\n+\t[BNXT_ULP_CLASS_HID_199fc] = 2399,\n+\t[BNXT_ULP_CLASS_HID_19ca8] = 2400,\n+\t[BNXT_ULP_CLASS_HID_8b5c] = 2401,\n+\t[BNXT_ULP_CLASS_HID_8460] = 2402,\n+\t[BNXT_ULP_CLASS_HID_1ba60] = 2403,\n+\t[BNXT_ULP_CLASS_HID_1a15c] = 2404,\n+\t[BNXT_ULP_CLASS_HID_afc0] = 2405,\n+\t[BNXT_ULP_CLASS_HID_a814] = 2406,\n+\t[BNXT_ULP_CLASS_HID_1de14] = 2407,\n+\t[BNXT_ULP_CLASS_HID_1c5c0] = 2408,\n+\t[BNXT_ULP_CLASS_HID_8c2c] = 2409,\n+\t[BNXT_ULP_CLASS_HID_8970] = 2410,\n+\t[BNXT_ULP_CLASS_HID_1bf70] = 2411,\n+\t[BNXT_ULP_CLASS_HID_1a22c] = 2412,\n+\t[BNXT_ULP_CLASS_HID_d0d0] = 2413,\n+\t[BNXT_ULP_CLASS_HID_ade4] = 2414,\n+\t[BNXT_ULP_CLASS_HID_1c3e4] = 2415,\n+\t[BNXT_ULP_CLASS_HID_1c6d0] = 2416,\n+\t[BNXT_ULP_CLASS_HID_9988] = 2417,\n+\t[BNXT_ULP_CLASS_HID_92dc] = 2418,\n+\t[BNXT_ULP_CLASS_HID_188dc] = 2419,\n+\t[BNXT_ULP_CLASS_HID_18f88] = 2420,\n+\t[BNXT_ULP_CLASS_HID_ba3c] = 2421,\n+\t[BNXT_ULP_CLASS_HID_b740] = 2422,\n+\t[BNXT_ULP_CLASS_HID_1ad40] = 2423,\n+\t[BNXT_ULP_CLASS_HID_1d03c] = 2424,\n+\t[BNXT_ULP_CLASS_HID_86e0] = 2425,\n+\t[BNXT_ULP_CLASS_HID_8334] = 2426,\n+\t[BNXT_ULP_CLASS_HID_1b934] = 2427,\n+\t[BNXT_ULP_CLASS_HID_1bce0] = 2428,\n+\t[BNXT_ULP_CLASS_HID_aa94] = 2429,\n+\t[BNXT_ULP_CLASS_HID_a7d8] = 2430,\n+\t[BNXT_ULP_CLASS_HID_1ddd8] = 2431,\n+\t[BNXT_ULP_CLASS_HID_1c094] = 2432,\n+\t[BNXT_ULP_CLASS_HID_904c] = 2433,\n+\t[BNXT_ULP_CLASS_HID_c84c] = 2434,\n+\t[BNXT_ULP_CLASS_HID_18290] = 2435,\n+\t[BNXT_ULP_CLASS_HID_1864c] = 2436,\n+\t[BNXT_ULP_CLASS_HID_b4f0] = 2437,\n+\t[BNXT_ULP_CLASS_HID_b104] = 2438,\n+\t[BNXT_ULP_CLASS_HID_1a704] = 2439,\n+\t[BNXT_ULP_CLASS_HID_1aaf0] = 2440,\n+\t[BNXT_ULP_CLASS_HID_80a4] = 2441,\n+\t[BNXT_ULP_CLASS_HID_9de8] = 2442,\n+\t[BNXT_ULP_CLASS_HID_1b3e8] = 2443,\n+\t[BNXT_ULP_CLASS_HID_1b6a4] = 2444,\n+\t[BNXT_ULP_CLASS_HID_a548] = 2445,\n+\t[BNXT_ULP_CLASS_HID_a19c] = 2446,\n+\t[BNXT_ULP_CLASS_HID_1d79c] = 2447,\n+\t[BNXT_ULP_CLASS_HID_1db48] = 2448,\n+\t[BNXT_ULP_CLASS_HID_9a98] = 2449,\n+\t[BNXT_ULP_CLASS_HID_97ac] = 2450,\n+\t[BNXT_ULP_CLASS_HID_18dac] = 2451,\n+\t[BNXT_ULP_CLASS_HID_1b098] = 2452,\n+\t[BNXT_ULP_CLASS_HID_bf0c] = 2453,\n+\t[BNXT_ULP_CLASS_HID_b850] = 2454,\n+\t[BNXT_ULP_CLASS_HID_1ae50] = 2455,\n+\t[BNXT_ULP_CLASS_HID_1d50c] = 2456,\n+\t[BNXT_ULP_CLASS_HID_34f0] = 2457,\n+\t[BNXT_ULP_CLASS_HID_3a3c] = 2458,\n+\t[BNXT_ULP_CLASS_HID_5ea0] = 2459,\n+\t[BNXT_ULP_CLASS_HID_0798] = 2460,\n+\t[BNXT_ULP_CLASS_HID_280c] = 2461,\n+\t[BNXT_ULP_CLASS_HID_5964] = 2462,\n+\t[BNXT_ULP_CLASS_HID_1e5c] = 2463,\n+\t[BNXT_ULP_CLASS_HID_22c0] = 2464,\n+\t[BNXT_ULP_CLASS_HID_a71c] = 2465,\n+\t[BNXT_ULP_CLASS_HID_a8dc] = 2466,\n+\t[BNXT_ULP_CLASS_HID_ed9c] = 2467,\n+\t[BNXT_ULP_CLASS_HID_ef5c] = 2468,\n+\t[BNXT_ULP_CLASS_HID_a060] = 2469,\n+\t[BNXT_ULP_CLASS_HID_a520] = 2470,\n+\t[BNXT_ULP_CLASS_HID_e6e0] = 2471,\n+\t[BNXT_ULP_CLASS_HID_eba0] = 2472,\n+\t[BNXT_ULP_CLASS_HID_1d660] = 2473,\n+\t[BNXT_ULP_CLASS_HID_1fb20] = 2474,\n+\t[BNXT_ULP_CLASS_HID_1dce0] = 2475,\n+\t[BNXT_ULP_CLASS_HID_1e1a0] = 2476,\n+\t[BNXT_ULP_CLASS_HID_1dd1c] = 2477,\n+\t[BNXT_ULP_CLASS_HID_1fedc] = 2478,\n+\t[BNXT_ULP_CLASS_HID_1c39c] = 2479,\n+\t[BNXT_ULP_CLASS_HID_1e55c] = 2480,\n+\t[BNXT_ULP_CLASS_HID_cb80] = 2481,\n+\t[BNXT_ULP_CLASS_HID_b194] = 2482,\n+\t[BNXT_ULP_CLASS_HID_d354] = 2483,\n+\t[BNXT_ULP_CLASS_HID_f414] = 2484,\n+\t[BNXT_ULP_CLASS_HID_c4d4] = 2485,\n+\t[BNXT_ULP_CLASS_HID_e994] = 2486,\n+\t[BNXT_ULP_CLASS_HID_cb54] = 2487,\n+\t[BNXT_ULP_CLASS_HID_f158] = 2488,\n+\t[BNXT_ULP_CLASS_HID_19f18] = 2489,\n+\t[BNXT_ULP_CLASS_HID_1a0d8] = 2490,\n+\t[BNXT_ULP_CLASS_HID_1c598] = 2491,\n+\t[BNXT_ULP_CLASS_HID_1e758] = 2492,\n+\t[BNXT_ULP_CLASS_HID_182d4] = 2493,\n+\t[BNXT_ULP_CLASS_HID_1a794] = 2494,\n+\t[BNXT_ULP_CLASS_HID_1c954] = 2495,\n+\t[BNXT_ULP_CLASS_HID_1ea14] = 2496,\n+\t[BNXT_ULP_CLASS_HID_b0b8] = 2497,\n+\t[BNXT_ULP_CLASS_HID_b278] = 2498,\n+\t[BNXT_ULP_CLASS_HID_f738] = 2499,\n+\t[BNXT_ULP_CLASS_HID_f8f8] = 2500,\n+\t[BNXT_ULP_CLASS_HID_8d8c] = 2501,\n+\t[BNXT_ULP_CLASS_HID_af4c] = 2502,\n+\t[BNXT_ULP_CLASS_HID_f00c] = 2503,\n+\t[BNXT_ULP_CLASS_HID_f5cc] = 2504,\n+\t[BNXT_ULP_CLASS_HID_1a38c] = 2505,\n+\t[BNXT_ULP_CLASS_HID_1a54c] = 2506,\n+\t[BNXT_ULP_CLASS_HID_1e60c] = 2507,\n+\t[BNXT_ULP_CLASS_HID_1ebcc] = 2508,\n+\t[BNXT_ULP_CLASS_HID_1a6b8] = 2509,\n+\t[BNXT_ULP_CLASS_HID_1a878] = 2510,\n+\t[BNXT_ULP_CLASS_HID_1ed38] = 2511,\n+\t[BNXT_ULP_CLASS_HID_1eef8] = 2512,\n+\t[BNXT_ULP_CLASS_HID_d52c] = 2513,\n+\t[BNXT_ULP_CLASS_HID_f6ec] = 2514,\n+\t[BNXT_ULP_CLASS_HID_dbac] = 2515,\n+\t[BNXT_ULP_CLASS_HID_fd6c] = 2516,\n+\t[BNXT_ULP_CLASS_HID_ae70] = 2517,\n+\t[BNXT_ULP_CLASS_HID_f330] = 2518,\n+\t[BNXT_ULP_CLASS_HID_d4f0] = 2519,\n+\t[BNXT_ULP_CLASS_HID_f9b0] = 2520,\n+\t[BNXT_ULP_CLASS_HID_1c470] = 2521,\n+\t[BNXT_ULP_CLASS_HID_1e930] = 2522,\n+\t[BNXT_ULP_CLASS_HID_1caf0] = 2523,\n+\t[BNXT_ULP_CLASS_HID_1f084] = 2524,\n+\t[BNXT_ULP_CLASS_HID_1cb2c] = 2525,\n+\t[BNXT_ULP_CLASS_HID_1b130] = 2526,\n+\t[BNXT_ULP_CLASS_HID_1d2f0] = 2527,\n+\t[BNXT_ULP_CLASS_HID_1f7b0] = 2528,\n+\t[BNXT_ULP_CLASS_HID_a1d0] = 2529,\n+\t[BNXT_ULP_CLASS_HID_a290] = 2530,\n+\t[BNXT_ULP_CLASS_HID_e450] = 2531,\n+\t[BNXT_ULP_CLASS_HID_e910] = 2532,\n+\t[BNXT_ULP_CLASS_HID_ba24] = 2533,\n+\t[BNXT_ULP_CLASS_HID_bfe4] = 2534,\n+\t[BNXT_ULP_CLASS_HID_e0a4] = 2535,\n+\t[BNXT_ULP_CLASS_HID_e264] = 2536,\n+\t[BNXT_ULP_CLASS_HID_1d024] = 2537,\n+\t[BNXT_ULP_CLASS_HID_1f5e4] = 2538,\n+\t[BNXT_ULP_CLASS_HID_1d6a4] = 2539,\n+\t[BNXT_ULP_CLASS_HID_1f864] = 2540,\n+\t[BNXT_ULP_CLASS_HID_1d7d0] = 2541,\n+\t[BNXT_ULP_CLASS_HID_1f890] = 2542,\n+\t[BNXT_ULP_CLASS_HID_1da50] = 2543,\n+\t[BNXT_ULP_CLASS_HID_1ff10] = 2544,\n+\t[BNXT_ULP_CLASS_HID_c244] = 2545,\n+\t[BNXT_ULP_CLASS_HID_e704] = 2546,\n+\t[BNXT_ULP_CLASS_HID_c8c4] = 2547,\n+\t[BNXT_ULP_CLASS_HID_ed84] = 2548,\n+\t[BNXT_ULP_CLASS_HID_de88] = 2549,\n+\t[BNXT_ULP_CLASS_HID_e048] = 2550,\n+\t[BNXT_ULP_CLASS_HID_c508] = 2551,\n+\t[BNXT_ULP_CLASS_HID_e6c8] = 2552,\n+\t[BNXT_ULP_CLASS_HID_199dc] = 2553,\n+\t[BNXT_ULP_CLASS_HID_1ba9c] = 2554,\n+\t[BNXT_ULP_CLASS_HID_1dc5c] = 2555,\n+\t[BNXT_ULP_CLASS_HID_1e11c] = 2556,\n+\t[BNXT_ULP_CLASS_HID_19c88] = 2557,\n+\t[BNXT_ULP_CLASS_HID_1be48] = 2558,\n+\t[BNXT_ULP_CLASS_HID_1c308] = 2559,\n+\t[BNXT_ULP_CLASS_HID_1e4c8] = 2560,\n+\t[BNXT_ULP_CLASS_HID_8b7c] = 2561,\n+\t[BNXT_ULP_CLASS_HID_ac3c] = 2562,\n+\t[BNXT_ULP_CLASS_HID_f1fc] = 2563,\n+\t[BNXT_ULP_CLASS_HID_f2bc] = 2564,\n+\t[BNXT_ULP_CLASS_HID_8440] = 2565,\n+\t[BNXT_ULP_CLASS_HID_a900] = 2566,\n+\t[BNXT_ULP_CLASS_HID_cac0] = 2567,\n+\t[BNXT_ULP_CLASS_HID_ef80] = 2568,\n+\t[BNXT_ULP_CLASS_HID_1ba40] = 2569,\n+\t[BNXT_ULP_CLASS_HID_1bf00] = 2570,\n+\t[BNXT_ULP_CLASS_HID_1e0c0] = 2571,\n+\t[BNXT_ULP_CLASS_HID_1e580] = 2572,\n+\t[BNXT_ULP_CLASS_HID_1a17c] = 2573,\n+\t[BNXT_ULP_CLASS_HID_1a23c] = 2574,\n+\t[BNXT_ULP_CLASS_HID_1e7fc] = 2575,\n+\t[BNXT_ULP_CLASS_HID_1e8bc] = 2576,\n+\t[BNXT_ULP_CLASS_HID_afe0] = 2577,\n+\t[BNXT_ULP_CLASS_HID_f0a0] = 2578,\n+\t[BNXT_ULP_CLASS_HID_d260] = 2579,\n+\t[BNXT_ULP_CLASS_HID_f720] = 2580,\n+\t[BNXT_ULP_CLASS_HID_a834] = 2581,\n+\t[BNXT_ULP_CLASS_HID_adf4] = 2582,\n+\t[BNXT_ULP_CLASS_HID_eeb4] = 2583,\n+\t[BNXT_ULP_CLASS_HID_f074] = 2584,\n+\t[BNXT_ULP_CLASS_HID_1de34] = 2585,\n+\t[BNXT_ULP_CLASS_HID_1e3f4] = 2586,\n+\t[BNXT_ULP_CLASS_HID_1c4b4] = 2587,\n+\t[BNXT_ULP_CLASS_HID_1e674] = 2588,\n+\t[BNXT_ULP_CLASS_HID_1c5e0] = 2589,\n+\t[BNXT_ULP_CLASS_HID_1e6a0] = 2590,\n+\t[BNXT_ULP_CLASS_HID_1c860] = 2591,\n+\t[BNXT_ULP_CLASS_HID_1ed20] = 2592,\n+\t[BNXT_ULP_CLASS_HID_8c0c] = 2593,\n+\t[BNXT_ULP_CLASS_HID_b1cc] = 2594,\n+\t[BNXT_ULP_CLASS_HID_f28c] = 2595,\n+\t[BNXT_ULP_CLASS_HID_f44c] = 2596,\n+\t[BNXT_ULP_CLASS_HID_8950] = 2597,\n+\t[BNXT_ULP_CLASS_HID_aa10] = 2598,\n+\t[BNXT_ULP_CLASS_HID_cfd0] = 2599,\n+\t[BNXT_ULP_CLASS_HID_f090] = 2600,\n+\t[BNXT_ULP_CLASS_HID_1bf50] = 2601,\n+\t[BNXT_ULP_CLASS_HID_1a010] = 2602,\n+\t[BNXT_ULP_CLASS_HID_1e5d0] = 2603,\n+\t[BNXT_ULP_CLASS_HID_1e690] = 2604,\n+\t[BNXT_ULP_CLASS_HID_1a20c] = 2605,\n+\t[BNXT_ULP_CLASS_HID_1a7cc] = 2606,\n+\t[BNXT_ULP_CLASS_HID_1e88c] = 2607,\n+\t[BNXT_ULP_CLASS_HID_1ea4c] = 2608,\n+\t[BNXT_ULP_CLASS_HID_d0f0] = 2609,\n+\t[BNXT_ULP_CLASS_HID_f5b0] = 2610,\n+\t[BNXT_ULP_CLASS_HID_d770] = 2611,\n+\t[BNXT_ULP_CLASS_HID_f830] = 2612,\n+\t[BNXT_ULP_CLASS_HID_adc4] = 2613,\n+\t[BNXT_ULP_CLASS_HID_ae84] = 2614,\n+\t[BNXT_ULP_CLASS_HID_d044] = 2615,\n+\t[BNXT_ULP_CLASS_HID_f504] = 2616,\n+\t[BNXT_ULP_CLASS_HID_1c3c4] = 2617,\n+\t[BNXT_ULP_CLASS_HID_1e484] = 2618,\n+\t[BNXT_ULP_CLASS_HID_1c644] = 2619,\n+\t[BNXT_ULP_CLASS_HID_1eb04] = 2620,\n+\t[BNXT_ULP_CLASS_HID_1c6f0] = 2621,\n+\t[BNXT_ULP_CLASS_HID_1ebb0] = 2622,\n+\t[BNXT_ULP_CLASS_HID_1cd70] = 2623,\n+\t[BNXT_ULP_CLASS_HID_1f304] = 2624,\n+\t[BNXT_ULP_CLASS_HID_99a8] = 2625,\n+\t[BNXT_ULP_CLASS_HID_bb68] = 2626,\n+\t[BNXT_ULP_CLASS_HID_dc28] = 2627,\n+\t[BNXT_ULP_CLASS_HID_e1e8] = 2628,\n+\t[BNXT_ULP_CLASS_HID_92fc] = 2629,\n+\t[BNXT_ULP_CLASS_HID_b7bc] = 2630,\n+\t[BNXT_ULP_CLASS_HID_d97c] = 2631,\n+\t[BNXT_ULP_CLASS_HID_fa3c] = 2632,\n+\t[BNXT_ULP_CLASS_HID_188fc] = 2633,\n+\t[BNXT_ULP_CLASS_HID_1adbc] = 2634,\n+\t[BNXT_ULP_CLASS_HID_1cf7c] = 2635,\n+\t[BNXT_ULP_CLASS_HID_1f03c] = 2636,\n+\t[BNXT_ULP_CLASS_HID_18fa8] = 2637,\n+\t[BNXT_ULP_CLASS_HID_1b168] = 2638,\n+\t[BNXT_ULP_CLASS_HID_1f228] = 2639,\n+\t[BNXT_ULP_CLASS_HID_1f7e8] = 2640,\n+\t[BNXT_ULP_CLASS_HID_ba1c] = 2641,\n+\t[BNXT_ULP_CLASS_HID_bfdc] = 2642,\n+\t[BNXT_ULP_CLASS_HID_e09c] = 2643,\n+\t[BNXT_ULP_CLASS_HID_e25c] = 2644,\n+\t[BNXT_ULP_CLASS_HID_b760] = 2645,\n+\t[BNXT_ULP_CLASS_HID_b820] = 2646,\n+\t[BNXT_ULP_CLASS_HID_fde0] = 2647,\n+\t[BNXT_ULP_CLASS_HID_fea0] = 2648,\n+\t[BNXT_ULP_CLASS_HID_1ad60] = 2649,\n+\t[BNXT_ULP_CLASS_HID_1ae20] = 2650,\n+\t[BNXT_ULP_CLASS_HID_1d3e0] = 2651,\n+\t[BNXT_ULP_CLASS_HID_1f4a0] = 2652,\n+\t[BNXT_ULP_CLASS_HID_1d01c] = 2653,\n+\t[BNXT_ULP_CLASS_HID_1f5dc] = 2654,\n+\t[BNXT_ULP_CLASS_HID_1d69c] = 2655,\n+\t[BNXT_ULP_CLASS_HID_1f85c] = 2656,\n+\t[BNXT_ULP_CLASS_HID_86c0] = 2657,\n+\t[BNXT_ULP_CLASS_HID_ab80] = 2658,\n+\t[BNXT_ULP_CLASS_HID_cd40] = 2659,\n+\t[BNXT_ULP_CLASS_HID_ee00] = 2660,\n+\t[BNXT_ULP_CLASS_HID_8314] = 2661,\n+\t[BNXT_ULP_CLASS_HID_a4d4] = 2662,\n+\t[BNXT_ULP_CLASS_HID_c994] = 2663,\n+\t[BNXT_ULP_CLASS_HID_eb54] = 2664,\n+\t[BNXT_ULP_CLASS_HID_1b914] = 2665,\n+\t[BNXT_ULP_CLASS_HID_1bad4] = 2666,\n+\t[BNXT_ULP_CLASS_HID_1ff94] = 2667,\n+\t[BNXT_ULP_CLASS_HID_1e154] = 2668,\n+\t[BNXT_ULP_CLASS_HID_1bcc0] = 2669,\n+\t[BNXT_ULP_CLASS_HID_1a180] = 2670,\n+\t[BNXT_ULP_CLASS_HID_1e340] = 2671,\n+\t[BNXT_ULP_CLASS_HID_1e400] = 2672,\n+\t[BNXT_ULP_CLASS_HID_aab4] = 2673,\n+\t[BNXT_ULP_CLASS_HID_ac74] = 2674,\n+\t[BNXT_ULP_CLASS_HID_d134] = 2675,\n+\t[BNXT_ULP_CLASS_HID_f2f4] = 2676,\n+\t[BNXT_ULP_CLASS_HID_a7f8] = 2677,\n+\t[BNXT_ULP_CLASS_HID_a8b8] = 2678,\n+\t[BNXT_ULP_CLASS_HID_ea78] = 2679,\n+\t[BNXT_ULP_CLASS_HID_ef38] = 2680,\n+\t[BNXT_ULP_CLASS_HID_1ddf8] = 2681,\n+\t[BNXT_ULP_CLASS_HID_1feb8] = 2682,\n+\t[BNXT_ULP_CLASS_HID_1c078] = 2683,\n+\t[BNXT_ULP_CLASS_HID_1e538] = 2684,\n+\t[BNXT_ULP_CLASS_HID_1c0b4] = 2685,\n+\t[BNXT_ULP_CLASS_HID_1e274] = 2686,\n+\t[BNXT_ULP_CLASS_HID_1c734] = 2687,\n+\t[BNXT_ULP_CLASS_HID_1e8f4] = 2688,\n+\t[BNXT_ULP_CLASS_HID_906c] = 2689,\n+\t[BNXT_ULP_CLASS_HID_b52c] = 2690,\n+\t[BNXT_ULP_CLASS_HID_d6ec] = 2691,\n+\t[BNXT_ULP_CLASS_HID_fbac] = 2692,\n+\t[BNXT_ULP_CLASS_HID_c86c] = 2693,\n+\t[BNXT_ULP_CLASS_HID_ed2c] = 2694,\n+\t[BNXT_ULP_CLASS_HID_d330] = 2695,\n+\t[BNXT_ULP_CLASS_HID_f4f0] = 2696,\n+\t[BNXT_ULP_CLASS_HID_182b0] = 2697,\n+\t[BNXT_ULP_CLASS_HID_1a470] = 2698,\n+\t[BNXT_ULP_CLASS_HID_1c930] = 2699,\n+\t[BNXT_ULP_CLASS_HID_1eaf0] = 2700,\n+\t[BNXT_ULP_CLASS_HID_1866c] = 2701,\n+\t[BNXT_ULP_CLASS_HID_1ab2c] = 2702,\n+\t[BNXT_ULP_CLASS_HID_1ccec] = 2703,\n+\t[BNXT_ULP_CLASS_HID_1f1ac] = 2704,\n+\t[BNXT_ULP_CLASS_HID_b4d0] = 2705,\n+\t[BNXT_ULP_CLASS_HID_b990] = 2706,\n+\t[BNXT_ULP_CLASS_HID_fb50] = 2707,\n+\t[BNXT_ULP_CLASS_HID_fc10] = 2708,\n+\t[BNXT_ULP_CLASS_HID_b124] = 2709,\n+\t[BNXT_ULP_CLASS_HID_b2e4] = 2710,\n+\t[BNXT_ULP_CLASS_HID_f7a4] = 2711,\n+\t[BNXT_ULP_CLASS_HID_f964] = 2712,\n+\t[BNXT_ULP_CLASS_HID_1a724] = 2713,\n+\t[BNXT_ULP_CLASS_HID_1a8e4] = 2714,\n+\t[BNXT_ULP_CLASS_HID_1eda4] = 2715,\n+\t[BNXT_ULP_CLASS_HID_1ef64] = 2716,\n+\t[BNXT_ULP_CLASS_HID_1aad0] = 2717,\n+\t[BNXT_ULP_CLASS_HID_1af90] = 2718,\n+\t[BNXT_ULP_CLASS_HID_1d150] = 2719,\n+\t[BNXT_ULP_CLASS_HID_1f210] = 2720,\n+\t[BNXT_ULP_CLASS_HID_8084] = 2721,\n+\t[BNXT_ULP_CLASS_HID_a244] = 2722,\n+\t[BNXT_ULP_CLASS_HID_c704] = 2723,\n+\t[BNXT_ULP_CLASS_HID_e8c4] = 2724,\n+\t[BNXT_ULP_CLASS_HID_9dc8] = 2725,\n+\t[BNXT_ULP_CLASS_HID_be88] = 2726,\n+\t[BNXT_ULP_CLASS_HID_c048] = 2727,\n+\t[BNXT_ULP_CLASS_HID_e508] = 2728,\n+\t[BNXT_ULP_CLASS_HID_1b3c8] = 2729,\n+\t[BNXT_ULP_CLASS_HID_1b488] = 2730,\n+\t[BNXT_ULP_CLASS_HID_1f648] = 2731,\n+\t[BNXT_ULP_CLASS_HID_1fb08] = 2732,\n+\t[BNXT_ULP_CLASS_HID_1b684] = 2733,\n+\t[BNXT_ULP_CLASS_HID_1b844] = 2734,\n+\t[BNXT_ULP_CLASS_HID_1fd04] = 2735,\n+\t[BNXT_ULP_CLASS_HID_1fec4] = 2736,\n+\t[BNXT_ULP_CLASS_HID_a568] = 2737,\n+\t[BNXT_ULP_CLASS_HID_a628] = 2738,\n+\t[BNXT_ULP_CLASS_HID_ebe8] = 2739,\n+\t[BNXT_ULP_CLASS_HID_eca8] = 2740,\n+\t[BNXT_ULP_CLASS_HID_a1bc] = 2741,\n+\t[BNXT_ULP_CLASS_HID_a37c] = 2742,\n+\t[BNXT_ULP_CLASS_HID_e43c] = 2743,\n+\t[BNXT_ULP_CLASS_HID_e9fc] = 2744,\n+\t[BNXT_ULP_CLASS_HID_1d7bc] = 2745,\n+\t[BNXT_ULP_CLASS_HID_1f97c] = 2746,\n+\t[BNXT_ULP_CLASS_HID_1da3c] = 2747,\n+\t[BNXT_ULP_CLASS_HID_1fffc] = 2748,\n+\t[BNXT_ULP_CLASS_HID_1db68] = 2749,\n+\t[BNXT_ULP_CLASS_HID_1fc28] = 2750,\n+\t[BNXT_ULP_CLASS_HID_1c1e8] = 2751,\n+\t[BNXT_ULP_CLASS_HID_1e2a8] = 2752,\n+\t[BNXT_ULP_CLASS_HID_9ab8] = 2753,\n+\t[BNXT_ULP_CLASS_HID_bc78] = 2754,\n+\t[BNXT_ULP_CLASS_HID_c138] = 2755,\n+\t[BNXT_ULP_CLASS_HID_e2f8] = 2756,\n+\t[BNXT_ULP_CLASS_HID_978c] = 2757,\n+\t[BNXT_ULP_CLASS_HID_b94c] = 2758,\n+\t[BNXT_ULP_CLASS_HID_da0c] = 2759,\n+\t[BNXT_ULP_CLASS_HID_ffcc] = 2760,\n+\t[BNXT_ULP_CLASS_HID_18d8c] = 2761,\n+\t[BNXT_ULP_CLASS_HID_1af4c] = 2762,\n+\t[BNXT_ULP_CLASS_HID_1f00c] = 2763,\n+\t[BNXT_ULP_CLASS_HID_1f5cc] = 2764,\n+\t[BNXT_ULP_CLASS_HID_1b0b8] = 2765,\n+\t[BNXT_ULP_CLASS_HID_1b278] = 2766,\n+\t[BNXT_ULP_CLASS_HID_1f738] = 2767,\n+\t[BNXT_ULP_CLASS_HID_1f8f8] = 2768,\n+\t[BNXT_ULP_CLASS_HID_bf2c] = 2769,\n+\t[BNXT_ULP_CLASS_HID_a0ec] = 2770,\n+\t[BNXT_ULP_CLASS_HID_e5ac] = 2771,\n+\t[BNXT_ULP_CLASS_HID_e76c] = 2772,\n+\t[BNXT_ULP_CLASS_HID_b870] = 2773,\n+\t[BNXT_ULP_CLASS_HID_bd30] = 2774,\n+\t[BNXT_ULP_CLASS_HID_fef0] = 2775,\n+\t[BNXT_ULP_CLASS_HID_e3b0] = 2776,\n+\t[BNXT_ULP_CLASS_HID_1ae70] = 2777,\n+\t[BNXT_ULP_CLASS_HID_1f330] = 2778,\n+\t[BNXT_ULP_CLASS_HID_1d4f0] = 2779,\n+\t[BNXT_ULP_CLASS_HID_1f9b0] = 2780,\n+\t[BNXT_ULP_CLASS_HID_1d52c] = 2781,\n+\t[BNXT_ULP_CLASS_HID_1f6ec] = 2782,\n+\t[BNXT_ULP_CLASS_HID_1dbac] = 2783,\n+\t[BNXT_ULP_CLASS_HID_1fd6c] = 2784,\n+\t[BNXT_ULP_CLASS_HID_34d0] = 2785,\n+\t[BNXT_ULP_CLASS_HID_3a1c] = 2786,\n+\t[BNXT_ULP_CLASS_HID_5e80] = 2787,\n+\t[BNXT_ULP_CLASS_HID_07b8] = 2788,\n+\t[BNXT_ULP_CLASS_HID_282c] = 2789,\n+\t[BNXT_ULP_CLASS_HID_5944] = 2790,\n+\t[BNXT_ULP_CLASS_HID_1e7c] = 2791,\n+\t[BNXT_ULP_CLASS_HID_22e0] = 2792,\n+\t[BNXT_ULP_CLASS_HID_a77c] = 2793,\n+\t[BNXT_ULP_CLASS_HID_a8bc] = 2794,\n+\t[BNXT_ULP_CLASS_HID_edfc] = 2795,\n+\t[BNXT_ULP_CLASS_HID_ef3c] = 2796,\n+\t[BNXT_ULP_CLASS_HID_a000] = 2797,\n+\t[BNXT_ULP_CLASS_HID_a540] = 2798,\n+\t[BNXT_ULP_CLASS_HID_e680] = 2799,\n+\t[BNXT_ULP_CLASS_HID_ebc0] = 2800,\n+\t[BNXT_ULP_CLASS_HID_1d600] = 2801,\n+\t[BNXT_ULP_CLASS_HID_1fb40] = 2802,\n+\t[BNXT_ULP_CLASS_HID_1dc80] = 2803,\n+\t[BNXT_ULP_CLASS_HID_1e1c0] = 2804,\n+\t[BNXT_ULP_CLASS_HID_1dd7c] = 2805,\n+\t[BNXT_ULP_CLASS_HID_1febc] = 2806,\n+\t[BNXT_ULP_CLASS_HID_1c3fc] = 2807,\n+\t[BNXT_ULP_CLASS_HID_1e53c] = 2808,\n+\t[BNXT_ULP_CLASS_HID_cbe0] = 2809,\n+\t[BNXT_ULP_CLASS_HID_b1f4] = 2810,\n+\t[BNXT_ULP_CLASS_HID_d334] = 2811,\n+\t[BNXT_ULP_CLASS_HID_f474] = 2812,\n+\t[BNXT_ULP_CLASS_HID_c4b4] = 2813,\n+\t[BNXT_ULP_CLASS_HID_e9f4] = 2814,\n+\t[BNXT_ULP_CLASS_HID_cb34] = 2815,\n+\t[BNXT_ULP_CLASS_HID_f138] = 2816,\n+\t[BNXT_ULP_CLASS_HID_19f78] = 2817,\n+\t[BNXT_ULP_CLASS_HID_1a0b8] = 2818,\n+\t[BNXT_ULP_CLASS_HID_1c5f8] = 2819,\n+\t[BNXT_ULP_CLASS_HID_1e738] = 2820,\n+\t[BNXT_ULP_CLASS_HID_182b4] = 2821,\n+\t[BNXT_ULP_CLASS_HID_1a7f4] = 2822,\n+\t[BNXT_ULP_CLASS_HID_1c934] = 2823,\n+\t[BNXT_ULP_CLASS_HID_1ea74] = 2824,\n+\t[BNXT_ULP_CLASS_HID_b0d8] = 2825,\n+\t[BNXT_ULP_CLASS_HID_b218] = 2826,\n+\t[BNXT_ULP_CLASS_HID_f758] = 2827,\n+\t[BNXT_ULP_CLASS_HID_f898] = 2828,\n+\t[BNXT_ULP_CLASS_HID_8dec] = 2829,\n+\t[BNXT_ULP_CLASS_HID_af2c] = 2830,\n+\t[BNXT_ULP_CLASS_HID_f06c] = 2831,\n+\t[BNXT_ULP_CLASS_HID_f5ac] = 2832,\n+\t[BNXT_ULP_CLASS_HID_1a3ec] = 2833,\n+\t[BNXT_ULP_CLASS_HID_1a52c] = 2834,\n+\t[BNXT_ULP_CLASS_HID_1e66c] = 2835,\n+\t[BNXT_ULP_CLASS_HID_1ebac] = 2836,\n+\t[BNXT_ULP_CLASS_HID_1a6d8] = 2837,\n+\t[BNXT_ULP_CLASS_HID_1a818] = 2838,\n+\t[BNXT_ULP_CLASS_HID_1ed58] = 2839,\n+\t[BNXT_ULP_CLASS_HID_1ee98] = 2840,\n+\t[BNXT_ULP_CLASS_HID_d54c] = 2841,\n+\t[BNXT_ULP_CLASS_HID_f68c] = 2842,\n+\t[BNXT_ULP_CLASS_HID_dbcc] = 2843,\n+\t[BNXT_ULP_CLASS_HID_fd0c] = 2844,\n+\t[BNXT_ULP_CLASS_HID_ae10] = 2845,\n+\t[BNXT_ULP_CLASS_HID_f350] = 2846,\n+\t[BNXT_ULP_CLASS_HID_d490] = 2847,\n+\t[BNXT_ULP_CLASS_HID_f9d0] = 2848,\n+\t[BNXT_ULP_CLASS_HID_1c410] = 2849,\n+\t[BNXT_ULP_CLASS_HID_1e950] = 2850,\n+\t[BNXT_ULP_CLASS_HID_1ca90] = 2851,\n+\t[BNXT_ULP_CLASS_HID_1f0e4] = 2852,\n+\t[BNXT_ULP_CLASS_HID_1cb4c] = 2853,\n+\t[BNXT_ULP_CLASS_HID_1b150] = 2854,\n+\t[BNXT_ULP_CLASS_HID_1d290] = 2855,\n+\t[BNXT_ULP_CLASS_HID_1f7d0] = 2856,\n+\t[BNXT_ULP_CLASS_HID_a1b0] = 2857,\n+\t[BNXT_ULP_CLASS_HID_a2f0] = 2858,\n+\t[BNXT_ULP_CLASS_HID_e430] = 2859,\n+\t[BNXT_ULP_CLASS_HID_e970] = 2860,\n+\t[BNXT_ULP_CLASS_HID_ba44] = 2861,\n+\t[BNXT_ULP_CLASS_HID_bf84] = 2862,\n+\t[BNXT_ULP_CLASS_HID_e0c4] = 2863,\n+\t[BNXT_ULP_CLASS_HID_e204] = 2864,\n+\t[BNXT_ULP_CLASS_HID_1d044] = 2865,\n+\t[BNXT_ULP_CLASS_HID_1f584] = 2866,\n+\t[BNXT_ULP_CLASS_HID_1d6c4] = 2867,\n+\t[BNXT_ULP_CLASS_HID_1f804] = 2868,\n+\t[BNXT_ULP_CLASS_HID_1d7b0] = 2869,\n+\t[BNXT_ULP_CLASS_HID_1f8f0] = 2870,\n+\t[BNXT_ULP_CLASS_HID_1da30] = 2871,\n+\t[BNXT_ULP_CLASS_HID_1ff70] = 2872,\n+\t[BNXT_ULP_CLASS_HID_c224] = 2873,\n+\t[BNXT_ULP_CLASS_HID_e764] = 2874,\n+\t[BNXT_ULP_CLASS_HID_c8a4] = 2875,\n+\t[BNXT_ULP_CLASS_HID_ede4] = 2876,\n+\t[BNXT_ULP_CLASS_HID_dee8] = 2877,\n+\t[BNXT_ULP_CLASS_HID_e028] = 2878,\n+\t[BNXT_ULP_CLASS_HID_c568] = 2879,\n+\t[BNXT_ULP_CLASS_HID_e6a8] = 2880,\n+\t[BNXT_ULP_CLASS_HID_199bc] = 2881,\n+\t[BNXT_ULP_CLASS_HID_1bafc] = 2882,\n+\t[BNXT_ULP_CLASS_HID_1dc3c] = 2883,\n+\t[BNXT_ULP_CLASS_HID_1e17c] = 2884,\n+\t[BNXT_ULP_CLASS_HID_19ce8] = 2885,\n+\t[BNXT_ULP_CLASS_HID_1be28] = 2886,\n+\t[BNXT_ULP_CLASS_HID_1c368] = 2887,\n+\t[BNXT_ULP_CLASS_HID_1e4a8] = 2888,\n+\t[BNXT_ULP_CLASS_HID_8b1c] = 2889,\n+\t[BNXT_ULP_CLASS_HID_ac5c] = 2890,\n+\t[BNXT_ULP_CLASS_HID_f19c] = 2891,\n+\t[BNXT_ULP_CLASS_HID_f2dc] = 2892,\n+\t[BNXT_ULP_CLASS_HID_8420] = 2893,\n+\t[BNXT_ULP_CLASS_HID_a960] = 2894,\n+\t[BNXT_ULP_CLASS_HID_caa0] = 2895,\n+\t[BNXT_ULP_CLASS_HID_efe0] = 2896,\n+\t[BNXT_ULP_CLASS_HID_1ba20] = 2897,\n+\t[BNXT_ULP_CLASS_HID_1bf60] = 2898,\n+\t[BNXT_ULP_CLASS_HID_1e0a0] = 2899,\n+\t[BNXT_ULP_CLASS_HID_1e5e0] = 2900,\n+\t[BNXT_ULP_CLASS_HID_1a11c] = 2901,\n+\t[BNXT_ULP_CLASS_HID_1a25c] = 2902,\n+\t[BNXT_ULP_CLASS_HID_1e79c] = 2903,\n+\t[BNXT_ULP_CLASS_HID_1e8dc] = 2904,\n+\t[BNXT_ULP_CLASS_HID_af80] = 2905,\n+\t[BNXT_ULP_CLASS_HID_f0c0] = 2906,\n+\t[BNXT_ULP_CLASS_HID_d200] = 2907,\n+\t[BNXT_ULP_CLASS_HID_f740] = 2908,\n+\t[BNXT_ULP_CLASS_HID_a854] = 2909,\n+\t[BNXT_ULP_CLASS_HID_ad94] = 2910,\n+\t[BNXT_ULP_CLASS_HID_eed4] = 2911,\n+\t[BNXT_ULP_CLASS_HID_f014] = 2912,\n+\t[BNXT_ULP_CLASS_HID_1de54] = 2913,\n+\t[BNXT_ULP_CLASS_HID_1e394] = 2914,\n+\t[BNXT_ULP_CLASS_HID_1c4d4] = 2915,\n+\t[BNXT_ULP_CLASS_HID_1e614] = 2916,\n+\t[BNXT_ULP_CLASS_HID_1c580] = 2917,\n+\t[BNXT_ULP_CLASS_HID_1e6c0] = 2918,\n+\t[BNXT_ULP_CLASS_HID_1c800] = 2919,\n+\t[BNXT_ULP_CLASS_HID_1ed40] = 2920,\n+\t[BNXT_ULP_CLASS_HID_8c6c] = 2921,\n+\t[BNXT_ULP_CLASS_HID_b1ac] = 2922,\n+\t[BNXT_ULP_CLASS_HID_f2ec] = 2923,\n+\t[BNXT_ULP_CLASS_HID_f42c] = 2924,\n+\t[BNXT_ULP_CLASS_HID_8930] = 2925,\n+\t[BNXT_ULP_CLASS_HID_aa70] = 2926,\n+\t[BNXT_ULP_CLASS_HID_cfb0] = 2927,\n+\t[BNXT_ULP_CLASS_HID_f0f0] = 2928,\n+\t[BNXT_ULP_CLASS_HID_1bf30] = 2929,\n+\t[BNXT_ULP_CLASS_HID_1a070] = 2930,\n+\t[BNXT_ULP_CLASS_HID_1e5b0] = 2931,\n+\t[BNXT_ULP_CLASS_HID_1e6f0] = 2932,\n+\t[BNXT_ULP_CLASS_HID_1a26c] = 2933,\n+\t[BNXT_ULP_CLASS_HID_1a7ac] = 2934,\n+\t[BNXT_ULP_CLASS_HID_1e8ec] = 2935,\n+\t[BNXT_ULP_CLASS_HID_1ea2c] = 2936,\n+\t[BNXT_ULP_CLASS_HID_d090] = 2937,\n+\t[BNXT_ULP_CLASS_HID_f5d0] = 2938,\n+\t[BNXT_ULP_CLASS_HID_d710] = 2939,\n+\t[BNXT_ULP_CLASS_HID_f850] = 2940,\n+\t[BNXT_ULP_CLASS_HID_ada4] = 2941,\n+\t[BNXT_ULP_CLASS_HID_aee4] = 2942,\n+\t[BNXT_ULP_CLASS_HID_d024] = 2943,\n+\t[BNXT_ULP_CLASS_HID_f564] = 2944,\n+\t[BNXT_ULP_CLASS_HID_1c3a4] = 2945,\n+\t[BNXT_ULP_CLASS_HID_1e4e4] = 2946,\n+\t[BNXT_ULP_CLASS_HID_1c624] = 2947,\n+\t[BNXT_ULP_CLASS_HID_1eb64] = 2948,\n+\t[BNXT_ULP_CLASS_HID_1c690] = 2949,\n+\t[BNXT_ULP_CLASS_HID_1ebd0] = 2950,\n+\t[BNXT_ULP_CLASS_HID_1cd10] = 2951,\n+\t[BNXT_ULP_CLASS_HID_1f364] = 2952,\n+\t[BNXT_ULP_CLASS_HID_99c8] = 2953,\n+\t[BNXT_ULP_CLASS_HID_bb08] = 2954,\n+\t[BNXT_ULP_CLASS_HID_dc48] = 2955,\n+\t[BNXT_ULP_CLASS_HID_e188] = 2956,\n+\t[BNXT_ULP_CLASS_HID_929c] = 2957,\n+\t[BNXT_ULP_CLASS_HID_b7dc] = 2958,\n+\t[BNXT_ULP_CLASS_HID_d91c] = 2959,\n+\t[BNXT_ULP_CLASS_HID_fa5c] = 2960,\n+\t[BNXT_ULP_CLASS_HID_1889c] = 2961,\n+\t[BNXT_ULP_CLASS_HID_1addc] = 2962,\n+\t[BNXT_ULP_CLASS_HID_1cf1c] = 2963,\n+\t[BNXT_ULP_CLASS_HID_1f05c] = 2964,\n+\t[BNXT_ULP_CLASS_HID_18fc8] = 2965,\n+\t[BNXT_ULP_CLASS_HID_1b108] = 2966,\n+\t[BNXT_ULP_CLASS_HID_1f248] = 2967,\n+\t[BNXT_ULP_CLASS_HID_1f788] = 2968,\n+\t[BNXT_ULP_CLASS_HID_ba7c] = 2969,\n+\t[BNXT_ULP_CLASS_HID_bfbc] = 2970,\n+\t[BNXT_ULP_CLASS_HID_e0fc] = 2971,\n+\t[BNXT_ULP_CLASS_HID_e23c] = 2972,\n+\t[BNXT_ULP_CLASS_HID_b700] = 2973,\n+\t[BNXT_ULP_CLASS_HID_b840] = 2974,\n+\t[BNXT_ULP_CLASS_HID_fd80] = 2975,\n+\t[BNXT_ULP_CLASS_HID_fec0] = 2976,\n+\t[BNXT_ULP_CLASS_HID_1ad00] = 2977,\n+\t[BNXT_ULP_CLASS_HID_1ae40] = 2978,\n+\t[BNXT_ULP_CLASS_HID_1d380] = 2979,\n+\t[BNXT_ULP_CLASS_HID_1f4c0] = 2980,\n+\t[BNXT_ULP_CLASS_HID_1d07c] = 2981,\n+\t[BNXT_ULP_CLASS_HID_1f5bc] = 2982,\n+\t[BNXT_ULP_CLASS_HID_1d6fc] = 2983,\n+\t[BNXT_ULP_CLASS_HID_1f83c] = 2984,\n+\t[BNXT_ULP_CLASS_HID_86a0] = 2985,\n+\t[BNXT_ULP_CLASS_HID_abe0] = 2986,\n+\t[BNXT_ULP_CLASS_HID_cd20] = 2987,\n+\t[BNXT_ULP_CLASS_HID_ee60] = 2988,\n+\t[BNXT_ULP_CLASS_HID_8374] = 2989,\n+\t[BNXT_ULP_CLASS_HID_a4b4] = 2990,\n+\t[BNXT_ULP_CLASS_HID_c9f4] = 2991,\n+\t[BNXT_ULP_CLASS_HID_eb34] = 2992,\n+\t[BNXT_ULP_CLASS_HID_1b974] = 2993,\n+\t[BNXT_ULP_CLASS_HID_1bab4] = 2994,\n+\t[BNXT_ULP_CLASS_HID_1fff4] = 2995,\n+\t[BNXT_ULP_CLASS_HID_1e134] = 2996,\n+\t[BNXT_ULP_CLASS_HID_1bca0] = 2997,\n+\t[BNXT_ULP_CLASS_HID_1a1e0] = 2998,\n+\t[BNXT_ULP_CLASS_HID_1e320] = 2999,\n+\t[BNXT_ULP_CLASS_HID_1e460] = 3000,\n+\t[BNXT_ULP_CLASS_HID_aad4] = 3001,\n+\t[BNXT_ULP_CLASS_HID_ac14] = 3002,\n+\t[BNXT_ULP_CLASS_HID_d154] = 3003,\n+\t[BNXT_ULP_CLASS_HID_f294] = 3004,\n+\t[BNXT_ULP_CLASS_HID_a798] = 3005,\n+\t[BNXT_ULP_CLASS_HID_a8d8] = 3006,\n+\t[BNXT_ULP_CLASS_HID_ea18] = 3007,\n+\t[BNXT_ULP_CLASS_HID_ef58] = 3008,\n+\t[BNXT_ULP_CLASS_HID_1dd98] = 3009,\n+\t[BNXT_ULP_CLASS_HID_1fed8] = 3010,\n+\t[BNXT_ULP_CLASS_HID_1c018] = 3011,\n+\t[BNXT_ULP_CLASS_HID_1e558] = 3012,\n+\t[BNXT_ULP_CLASS_HID_1c0d4] = 3013,\n+\t[BNXT_ULP_CLASS_HID_1e214] = 3014,\n+\t[BNXT_ULP_CLASS_HID_1c754] = 3015,\n+\t[BNXT_ULP_CLASS_HID_1e894] = 3016,\n+\t[BNXT_ULP_CLASS_HID_900c] = 3017,\n+\t[BNXT_ULP_CLASS_HID_b54c] = 3018,\n+\t[BNXT_ULP_CLASS_HID_d68c] = 3019,\n+\t[BNXT_ULP_CLASS_HID_fbcc] = 3020,\n+\t[BNXT_ULP_CLASS_HID_c80c] = 3021,\n+\t[BNXT_ULP_CLASS_HID_ed4c] = 3022,\n+\t[BNXT_ULP_CLASS_HID_d350] = 3023,\n+\t[BNXT_ULP_CLASS_HID_f490] = 3024,\n+\t[BNXT_ULP_CLASS_HID_182d0] = 3025,\n+\t[BNXT_ULP_CLASS_HID_1a410] = 3026,\n+\t[BNXT_ULP_CLASS_HID_1c950] = 3027,\n+\t[BNXT_ULP_CLASS_HID_1ea90] = 3028,\n+\t[BNXT_ULP_CLASS_HID_1860c] = 3029,\n+\t[BNXT_ULP_CLASS_HID_1ab4c] = 3030,\n+\t[BNXT_ULP_CLASS_HID_1cc8c] = 3031,\n+\t[BNXT_ULP_CLASS_HID_1f1cc] = 3032,\n+\t[BNXT_ULP_CLASS_HID_b4b0] = 3033,\n+\t[BNXT_ULP_CLASS_HID_b9f0] = 3034,\n+\t[BNXT_ULP_CLASS_HID_fb30] = 3035,\n+\t[BNXT_ULP_CLASS_HID_fc70] = 3036,\n+\t[BNXT_ULP_CLASS_HID_b144] = 3037,\n+\t[BNXT_ULP_CLASS_HID_b284] = 3038,\n+\t[BNXT_ULP_CLASS_HID_f7c4] = 3039,\n+\t[BNXT_ULP_CLASS_HID_f904] = 3040,\n+\t[BNXT_ULP_CLASS_HID_1a744] = 3041,\n+\t[BNXT_ULP_CLASS_HID_1a884] = 3042,\n+\t[BNXT_ULP_CLASS_HID_1edc4] = 3043,\n+\t[BNXT_ULP_CLASS_HID_1ef04] = 3044,\n+\t[BNXT_ULP_CLASS_HID_1aab0] = 3045,\n+\t[BNXT_ULP_CLASS_HID_1aff0] = 3046,\n+\t[BNXT_ULP_CLASS_HID_1d130] = 3047,\n+\t[BNXT_ULP_CLASS_HID_1f270] = 3048,\n+\t[BNXT_ULP_CLASS_HID_80e4] = 3049,\n+\t[BNXT_ULP_CLASS_HID_a224] = 3050,\n+\t[BNXT_ULP_CLASS_HID_c764] = 3051,\n+\t[BNXT_ULP_CLASS_HID_e8a4] = 3052,\n+\t[BNXT_ULP_CLASS_HID_9da8] = 3053,\n+\t[BNXT_ULP_CLASS_HID_bee8] = 3054,\n+\t[BNXT_ULP_CLASS_HID_c028] = 3055,\n+\t[BNXT_ULP_CLASS_HID_e568] = 3056,\n+\t[BNXT_ULP_CLASS_HID_1b3a8] = 3057,\n+\t[BNXT_ULP_CLASS_HID_1b4e8] = 3058,\n+\t[BNXT_ULP_CLASS_HID_1f628] = 3059,\n+\t[BNXT_ULP_CLASS_HID_1fb68] = 3060,\n+\t[BNXT_ULP_CLASS_HID_1b6e4] = 3061,\n+\t[BNXT_ULP_CLASS_HID_1b824] = 3062,\n+\t[BNXT_ULP_CLASS_HID_1fd64] = 3063,\n+\t[BNXT_ULP_CLASS_HID_1fea4] = 3064,\n+\t[BNXT_ULP_CLASS_HID_a508] = 3065,\n+\t[BNXT_ULP_CLASS_HID_a648] = 3066,\n+\t[BNXT_ULP_CLASS_HID_eb88] = 3067,\n+\t[BNXT_ULP_CLASS_HID_ecc8] = 3068,\n+\t[BNXT_ULP_CLASS_HID_a1dc] = 3069,\n+\t[BNXT_ULP_CLASS_HID_a31c] = 3070,\n+\t[BNXT_ULP_CLASS_HID_e45c] = 3071,\n+\t[BNXT_ULP_CLASS_HID_e99c] = 3072,\n+\t[BNXT_ULP_CLASS_HID_1d7dc] = 3073,\n+\t[BNXT_ULP_CLASS_HID_1f91c] = 3074,\n+\t[BNXT_ULP_CLASS_HID_1da5c] = 3075,\n+\t[BNXT_ULP_CLASS_HID_1ff9c] = 3076,\n+\t[BNXT_ULP_CLASS_HID_1db08] = 3077,\n+\t[BNXT_ULP_CLASS_HID_1fc48] = 3078,\n+\t[BNXT_ULP_CLASS_HID_1c188] = 3079,\n+\t[BNXT_ULP_CLASS_HID_1e2c8] = 3080,\n+\t[BNXT_ULP_CLASS_HID_9ad8] = 3081,\n+\t[BNXT_ULP_CLASS_HID_bc18] = 3082,\n+\t[BNXT_ULP_CLASS_HID_c158] = 3083,\n+\t[BNXT_ULP_CLASS_HID_e298] = 3084,\n+\t[BNXT_ULP_CLASS_HID_97ec] = 3085,\n+\t[BNXT_ULP_CLASS_HID_b92c] = 3086,\n+\t[BNXT_ULP_CLASS_HID_da6c] = 3087,\n+\t[BNXT_ULP_CLASS_HID_ffac] = 3088,\n+\t[BNXT_ULP_CLASS_HID_18dec] = 3089,\n+\t[BNXT_ULP_CLASS_HID_1af2c] = 3090,\n+\t[BNXT_ULP_CLASS_HID_1f06c] = 3091,\n+\t[BNXT_ULP_CLASS_HID_1f5ac] = 3092,\n+\t[BNXT_ULP_CLASS_HID_1b0d8] = 3093,\n+\t[BNXT_ULP_CLASS_HID_1b218] = 3094,\n+\t[BNXT_ULP_CLASS_HID_1f758] = 3095,\n+\t[BNXT_ULP_CLASS_HID_1f898] = 3096,\n+\t[BNXT_ULP_CLASS_HID_bf4c] = 3097,\n+\t[BNXT_ULP_CLASS_HID_a08c] = 3098,\n+\t[BNXT_ULP_CLASS_HID_e5cc] = 3099,\n+\t[BNXT_ULP_CLASS_HID_e70c] = 3100,\n+\t[BNXT_ULP_CLASS_HID_b810] = 3101,\n+\t[BNXT_ULP_CLASS_HID_bd50] = 3102,\n+\t[BNXT_ULP_CLASS_HID_fe90] = 3103,\n+\t[BNXT_ULP_CLASS_HID_e3d0] = 3104,\n+\t[BNXT_ULP_CLASS_HID_1ae10] = 3105,\n+\t[BNXT_ULP_CLASS_HID_1f350] = 3106,\n+\t[BNXT_ULP_CLASS_HID_1d490] = 3107,\n+\t[BNXT_ULP_CLASS_HID_1f9d0] = 3108,\n+\t[BNXT_ULP_CLASS_HID_1d54c] = 3109,\n+\t[BNXT_ULP_CLASS_HID_1f68c] = 3110,\n+\t[BNXT_ULP_CLASS_HID_1dbcc] = 3111,\n+\t[BNXT_ULP_CLASS_HID_1fd0c] = 3112,\n+\t[BNXT_ULP_CLASS_HID_34b0] = 3113,\n+\t[BNXT_ULP_CLASS_HID_3a7c] = 3114,\n+\t[BNXT_ULP_CLASS_HID_5ee0] = 3115,\n+\t[BNXT_ULP_CLASS_HID_07d8] = 3116,\n+\t[BNXT_ULP_CLASS_HID_284c] = 3117,\n+\t[BNXT_ULP_CLASS_HID_5924] = 3118,\n+\t[BNXT_ULP_CLASS_HID_1e1c] = 3119,\n+\t[BNXT_ULP_CLASS_HID_2280] = 3120,\n+\t[BNXT_ULP_CLASS_HID_24604] = 3121,\n+\t[BNXT_ULP_CLASS_HID_255d4] = 3122,\n+\t[BNXT_ULP_CLASS_HID_22e08] = 3123,\n+\t[BNXT_ULP_CLASS_HID_24378] = 3124,\n+\t[BNXT_ULP_CLASS_HID_20fcc] = 3125,\n+\t[BNXT_ULP_CLASS_HID_21a9c] = 3126,\n+\t[BNXT_ULP_CLASS_HID_217d0] = 3127,\n+\t[BNXT_ULP_CLASS_HID_20800] = 3128,\n+\t[BNXT_ULP_CLASS_HID_253a0] = 3129,\n+\t[BNXT_ULP_CLASS_HID_23f70] = 3130,\n+\t[BNXT_ULP_CLASS_HID_23ba4] = 3131,\n+\t[BNXT_ULP_CLASS_HID_22c94] = 3132,\n+\t[BNXT_ULP_CLASS_HID_21968] = 3133,\n+\t[BNXT_ULP_CLASS_HID_243c4] = 3134,\n+\t[BNXT_ULP_CLASS_HID_25c38] = 3135,\n+\t[BNXT_ULP_CLASS_HID_2125c] = 3136,\n+\t[BNXT_ULP_CLASS_HID_240c8] = 3137,\n+\t[BNXT_ULP_CLASS_HID_22f98] = 3138,\n+\t[BNXT_ULP_CLASS_HID_228cc] = 3139,\n+\t[BNXT_ULP_CLASS_HID_25d3c] = 3140,\n+\t[BNXT_ULP_CLASS_HID_20990] = 3141,\n+\t[BNXT_ULP_CLASS_HID_214a0] = 3142,\n+\t[BNXT_ULP_CLASS_HID_21194] = 3143,\n+\t[BNXT_ULP_CLASS_HID_202c4] = 3144,\n+\t[BNXT_ULP_CLASS_HID_22a64] = 3145,\n+\t[BNXT_ULP_CLASS_HID_23934] = 3146,\n+\t[BNXT_ULP_CLASS_HID_23268] = 3147,\n+\t[BNXT_ULP_CLASS_HID_22758] = 3148,\n+\t[BNXT_ULP_CLASS_HID_2132c] = 3149,\n+\t[BNXT_ULP_CLASS_HID_25d88] = 3150,\n+\t[BNXT_ULP_CLASS_HID_256fc] = 3151,\n+\t[BNXT_ULP_CLASS_HID_24b2c] = 3152,\n+\t[BNXT_ULP_CLASS_HID_22f14] = 3153,\n+\t[BNXT_ULP_CLASS_HID_23a24] = 3154,\n+\t[BNXT_ULP_CLASS_HID_23718] = 3155,\n+\t[BNXT_ULP_CLASS_HID_22848] = 3156,\n+\t[BNXT_ULP_CLASS_HID_214dc] = 3157,\n+\t[BNXT_ULP_CLASS_HID_25eb8] = 3158,\n+\t[BNXT_ULP_CLASS_HID_25bec] = 3159,\n+\t[BNXT_ULP_CLASS_HID_21110] = 3160,\n+\t[BNXT_ULP_CLASS_HID_238b0] = 3161,\n+\t[BNXT_ULP_CLASS_HID_20440] = 3162,\n+\t[BNXT_ULP_CLASS_HID_200b4] = 3163,\n+\t[BNXT_ULP_CLASS_HID_235e4] = 3164,\n+\t[BNXT_ULP_CLASS_HID_25d04] = 3165,\n+\t[BNXT_ULP_CLASS_HID_228d4] = 3166,\n+\t[BNXT_ULP_CLASS_HID_22508] = 3167,\n+\t[BNXT_ULP_CLASS_HID_25678] = 3168,\n+\t[BNXT_ULP_CLASS_HID_229d8] = 3169,\n+\t[BNXT_ULP_CLASS_HID_234e8] = 3170,\n+\t[BNXT_ULP_CLASS_HID_231dc] = 3171,\n+\t[BNXT_ULP_CLASS_HID_2220c] = 3172,\n+\t[BNXT_ULP_CLASS_HID_24dac] = 3173,\n+\t[BNXT_ULP_CLASS_HID_2597c] = 3174,\n+\t[BNXT_ULP_CLASS_HID_255b0] = 3175,\n+\t[BNXT_ULP_CLASS_HID_246e0] = 3176,\n+\t[BNXT_ULP_CLASS_HID_23374] = 3177,\n+\t[BNXT_ULP_CLASS_HID_21e04] = 3178,\n+\t[BNXT_ULP_CLASS_HID_21b78] = 3179,\n+\t[BNXT_ULP_CLASS_HID_20fa8] = 3180,\n+\t[BNXT_ULP_CLASS_HID_257c8] = 3181,\n+\t[BNXT_ULP_CLASS_HID_22298] = 3182,\n+\t[BNXT_ULP_CLASS_HID_23fcc] = 3183,\n+\t[BNXT_ULP_CLASS_HID_2503c] = 3184,\n+\t[BNXT_ULP_CLASS_HID_2239c] = 3185,\n+\t[BNXT_ULP_CLASS_HID_20eac] = 3186,\n+\t[BNXT_ULP_CLASS_HID_20be0] = 3187,\n+\t[BNXT_ULP_CLASS_HID_23cd0] = 3188,\n+\t[BNXT_ULP_CLASS_HID_24470] = 3189,\n+\t[BNXT_ULP_CLASS_HID_25300] = 3190,\n+\t[BNXT_ULP_CLASS_HID_22c74] = 3191,\n+\t[BNXT_ULP_CLASS_HID_240a4] = 3192,\n+\t[BNXT_ULP_CLASS_HID_23da0] = 3193,\n+\t[BNXT_ULP_CLASS_HID_20970] = 3194,\n+\t[BNXT_ULP_CLASS_HID_205a4] = 3195,\n+\t[BNXT_ULP_CLASS_HID_23694] = 3196,\n+\t[BNXT_ULP_CLASS_HID_25e34] = 3197,\n+\t[BNXT_ULP_CLASS_HID_22dc4] = 3198,\n+\t[BNXT_ULP_CLASS_HID_22638] = 3199,\n+\t[BNXT_ULP_CLASS_HID_25b68] = 3200,\n+\t[BNXT_ULP_CLASS_HID_34c8] = 3201,\n+\t[BNXT_ULP_CLASS_HID_3a04] = 3202,\n+\t[BNXT_ULP_CLASS_HID_5e98] = 3203,\n+\t[BNXT_ULP_CLASS_HID_07a0] = 3204,\n+\t[BNXT_ULP_CLASS_HID_2834] = 3205,\n+\t[BNXT_ULP_CLASS_HID_595c] = 3206,\n+\t[BNXT_ULP_CLASS_HID_1e64] = 3207,\n+\t[BNXT_ULP_CLASS_HID_22f8] = 3208,\n+\t[BNXT_ULP_CLASS_HID_24664] = 3209,\n+\t[BNXT_ULP_CLASS_HID_29418] = 3210,\n+\t[BNXT_ULP_CLASS_HID_30118] = 3211,\n+\t[BNXT_ULP_CLASS_HID_38a18] = 3212,\n+\t[BNXT_ULP_CLASS_HID_255b4] = 3213,\n+\t[BNXT_ULP_CLASS_HID_2deb4] = 3214,\n+\t[BNXT_ULP_CLASS_HID_34bb4] = 3215,\n+\t[BNXT_ULP_CLASS_HID_39968] = 3216,\n+\t[BNXT_ULP_CLASS_HID_22e68] = 3217,\n+\t[BNXT_ULP_CLASS_HID_2db68] = 3218,\n+\t[BNXT_ULP_CLASS_HID_34468] = 3219,\n+\t[BNXT_ULP_CLASS_HID_3921c] = 3220,\n+\t[BNXT_ULP_CLASS_HID_24318] = 3221,\n+\t[BNXT_ULP_CLASS_HID_290cc] = 3222,\n+\t[BNXT_ULP_CLASS_HID_31dcc] = 3223,\n+\t[BNXT_ULP_CLASS_HID_386cc] = 3224,\n+\t[BNXT_ULP_CLASS_HID_20fac] = 3225,\n+\t[BNXT_ULP_CLASS_HID_2b8ac] = 3226,\n+\t[BNXT_ULP_CLASS_HID_325ac] = 3227,\n+\t[BNXT_ULP_CLASS_HID_3aeac] = 3228,\n+\t[BNXT_ULP_CLASS_HID_21afc] = 3229,\n+\t[BNXT_ULP_CLASS_HID_287fc] = 3230,\n+\t[BNXT_ULP_CLASS_HID_330fc] = 3231,\n+\t[BNXT_ULP_CLASS_HID_3bdfc] = 3232,\n+\t[BNXT_ULP_CLASS_HID_217b0] = 3233,\n+\t[BNXT_ULP_CLASS_HID_280b0] = 3234,\n+\t[BNXT_ULP_CLASS_HID_30db0] = 3235,\n+\t[BNXT_ULP_CLASS_HID_3b6b0] = 3236,\n+\t[BNXT_ULP_CLASS_HID_20860] = 3237,\n+\t[BNXT_ULP_CLASS_HID_2b560] = 3238,\n+\t[BNXT_ULP_CLASS_HID_33e60] = 3239,\n+\t[BNXT_ULP_CLASS_HID_3ab60] = 3240,\n+\t[BNXT_ULP_CLASS_HID_253c0] = 3241,\n+\t[BNXT_ULP_CLASS_HID_2dcc0] = 3242,\n+\t[BNXT_ULP_CLASS_HID_349c0] = 3243,\n+\t[BNXT_ULP_CLASS_HID_397f4] = 3244,\n+\t[BNXT_ULP_CLASS_HID_23f10] = 3245,\n+\t[BNXT_ULP_CLASS_HID_2a810] = 3246,\n+\t[BNXT_ULP_CLASS_HID_35510] = 3247,\n+\t[BNXT_ULP_CLASS_HID_3de10] = 3248,\n+\t[BNXT_ULP_CLASS_HID_23bc4] = 3249,\n+\t[BNXT_ULP_CLASS_HID_2a4c4] = 3250,\n+\t[BNXT_ULP_CLASS_HID_351c4] = 3251,\n+\t[BNXT_ULP_CLASS_HID_3dac4] = 3252,\n+\t[BNXT_ULP_CLASS_HID_22cf4] = 3253,\n+\t[BNXT_ULP_CLASS_HID_2d9f4] = 3254,\n+\t[BNXT_ULP_CLASS_HID_342f4] = 3255,\n+\t[BNXT_ULP_CLASS_HID_390a8] = 3256,\n+\t[BNXT_ULP_CLASS_HID_21908] = 3257,\n+\t[BNXT_ULP_CLASS_HID_28208] = 3258,\n+\t[BNXT_ULP_CLASS_HID_30f08] = 3259,\n+\t[BNXT_ULP_CLASS_HID_3b808] = 3260,\n+\t[BNXT_ULP_CLASS_HID_243a4] = 3261,\n+\t[BNXT_ULP_CLASS_HID_29158] = 3262,\n+\t[BNXT_ULP_CLASS_HID_31a58] = 3263,\n+\t[BNXT_ULP_CLASS_HID_38758] = 3264,\n+\t[BNXT_ULP_CLASS_HID_25c58] = 3265,\n+\t[BNXT_ULP_CLASS_HID_2c958] = 3266,\n+\t[BNXT_ULP_CLASS_HID_3170c] = 3267,\n+\t[BNXT_ULP_CLASS_HID_3800c] = 3268,\n+\t[BNXT_ULP_CLASS_HID_2123c] = 3269,\n+\t[BNXT_ULP_CLASS_HID_29f3c] = 3270,\n+\t[BNXT_ULP_CLASS_HID_3083c] = 3271,\n+\t[BNXT_ULP_CLASS_HID_3b53c] = 3272,\n+\t[BNXT_ULP_CLASS_HID_240a8] = 3273,\n+\t[BNXT_ULP_CLASS_HID_2cda8] = 3274,\n+\t[BNXT_ULP_CLASS_HID_31b5c] = 3275,\n+\t[BNXT_ULP_CLASS_HID_3845c] = 3276,\n+\t[BNXT_ULP_CLASS_HID_22ff8] = 3277,\n+\t[BNXT_ULP_CLASS_HID_2d8f8] = 3278,\n+\t[BNXT_ULP_CLASS_HID_345f8] = 3279,\n+\t[BNXT_ULP_CLASS_HID_393ac] = 3280,\n+\t[BNXT_ULP_CLASS_HID_228ac] = 3281,\n+\t[BNXT_ULP_CLASS_HID_2d5ac] = 3282,\n+\t[BNXT_ULP_CLASS_HID_35eac] = 3283,\n+\t[BNXT_ULP_CLASS_HID_3cbac] = 3284,\n+\t[BNXT_ULP_CLASS_HID_25d5c] = 3285,\n+\t[BNXT_ULP_CLASS_HID_2c65c] = 3286,\n+\t[BNXT_ULP_CLASS_HID_31410] = 3287,\n+\t[BNXT_ULP_CLASS_HID_38110] = 3288,\n+\t[BNXT_ULP_CLASS_HID_209f0] = 3289,\n+\t[BNXT_ULP_CLASS_HID_2b2f0] = 3290,\n+\t[BNXT_ULP_CLASS_HID_33ff0] = 3291,\n+\t[BNXT_ULP_CLASS_HID_3a8f0] = 3292,\n+\t[BNXT_ULP_CLASS_HID_214c0] = 3293,\n+\t[BNXT_ULP_CLASS_HID_281c0] = 3294,\n+\t[BNXT_ULP_CLASS_HID_30ac0] = 3295,\n+\t[BNXT_ULP_CLASS_HID_3b7c0] = 3296,\n+\t[BNXT_ULP_CLASS_HID_211f4] = 3297,\n+\t[BNXT_ULP_CLASS_HID_29af4] = 3298,\n+\t[BNXT_ULP_CLASS_HID_307f4] = 3299,\n+\t[BNXT_ULP_CLASS_HID_3b0f4] = 3300,\n+\t[BNXT_ULP_CLASS_HID_202a4] = 3301,\n+\t[BNXT_ULP_CLASS_HID_28fa4] = 3302,\n+\t[BNXT_ULP_CLASS_HID_338a4] = 3303,\n+\t[BNXT_ULP_CLASS_HID_3a5a4] = 3304,\n+\t[BNXT_ULP_CLASS_HID_22a04] = 3305,\n+\t[BNXT_ULP_CLASS_HID_2d704] = 3306,\n+\t[BNXT_ULP_CLASS_HID_34004] = 3307,\n+\t[BNXT_ULP_CLASS_HID_3cd04] = 3308,\n+\t[BNXT_ULP_CLASS_HID_23954] = 3309,\n+\t[BNXT_ULP_CLASS_HID_2a254] = 3310,\n+\t[BNXT_ULP_CLASS_HID_32f54] = 3311,\n+\t[BNXT_ULP_CLASS_HID_3d854] = 3312,\n+\t[BNXT_ULP_CLASS_HID_23208] = 3313,\n+\t[BNXT_ULP_CLASS_HID_2bf08] = 3314,\n+\t[BNXT_ULP_CLASS_HID_32808] = 3315,\n+\t[BNXT_ULP_CLASS_HID_3d508] = 3316,\n+\t[BNXT_ULP_CLASS_HID_22738] = 3317,\n+\t[BNXT_ULP_CLASS_HID_2d038] = 3318,\n+\t[BNXT_ULP_CLASS_HID_35d38] = 3319,\n+\t[BNXT_ULP_CLASS_HID_3c638] = 3320,\n+\t[BNXT_ULP_CLASS_HID_2134c] = 3321,\n+\t[BNXT_ULP_CLASS_HID_29c4c] = 3322,\n+\t[BNXT_ULP_CLASS_HID_3094c] = 3323,\n+\t[BNXT_ULP_CLASS_HID_3b24c] = 3324,\n+\t[BNXT_ULP_CLASS_HID_25de8] = 3325,\n+\t[BNXT_ULP_CLASS_HID_2c6e8] = 3326,\n+\t[BNXT_ULP_CLASS_HID_3149c] = 3327,\n+\t[BNXT_ULP_CLASS_HID_3819c] = 3328,\n+\t[BNXT_ULP_CLASS_HID_2569c] = 3329,\n+\t[BNXT_ULP_CLASS_HID_2c39c] = 3330,\n+\t[BNXT_ULP_CLASS_HID_31150] = 3331,\n+\t[BNXT_ULP_CLASS_HID_39a50] = 3332,\n+\t[BNXT_ULP_CLASS_HID_24b4c] = 3333,\n+\t[BNXT_ULP_CLASS_HID_29900] = 3334,\n+\t[BNXT_ULP_CLASS_HID_30200] = 3335,\n+\t[BNXT_ULP_CLASS_HID_38f00] = 3336,\n+\t[BNXT_ULP_CLASS_HID_22f74] = 3337,\n+\t[BNXT_ULP_CLASS_HID_2d874] = 3338,\n+\t[BNXT_ULP_CLASS_HID_34574] = 3339,\n+\t[BNXT_ULP_CLASS_HID_39328] = 3340,\n+\t[BNXT_ULP_CLASS_HID_23a44] = 3341,\n+\t[BNXT_ULP_CLASS_HID_2a744] = 3342,\n+\t[BNXT_ULP_CLASS_HID_35044] = 3343,\n+\t[BNXT_ULP_CLASS_HID_3dd44] = 3344,\n+\t[BNXT_ULP_CLASS_HID_23778] = 3345,\n+\t[BNXT_ULP_CLASS_HID_2a078] = 3346,\n+\t[BNXT_ULP_CLASS_HID_32d78] = 3347,\n+\t[BNXT_ULP_CLASS_HID_3d678] = 3348,\n+\t[BNXT_ULP_CLASS_HID_22828] = 3349,\n+\t[BNXT_ULP_CLASS_HID_2d528] = 3350,\n+\t[BNXT_ULP_CLASS_HID_35e28] = 3351,\n+\t[BNXT_ULP_CLASS_HID_3cb28] = 3352,\n+\t[BNXT_ULP_CLASS_HID_214bc] = 3353,\n+\t[BNXT_ULP_CLASS_HID_281bc] = 3354,\n+\t[BNXT_ULP_CLASS_HID_30abc] = 3355,\n+\t[BNXT_ULP_CLASS_HID_3b7bc] = 3356,\n+\t[BNXT_ULP_CLASS_HID_25ed8] = 3357,\n+\t[BNXT_ULP_CLASS_HID_2cbd8] = 3358,\n+\t[BNXT_ULP_CLASS_HID_3198c] = 3359,\n+\t[BNXT_ULP_CLASS_HID_3828c] = 3360,\n+\t[BNXT_ULP_CLASS_HID_25b8c] = 3361,\n+\t[BNXT_ULP_CLASS_HID_2c48c] = 3362,\n+\t[BNXT_ULP_CLASS_HID_31240] = 3363,\n+\t[BNXT_ULP_CLASS_HID_39f40] = 3364,\n+\t[BNXT_ULP_CLASS_HID_21170] = 3365,\n+\t[BNXT_ULP_CLASS_HID_29a70] = 3366,\n+\t[BNXT_ULP_CLASS_HID_30770] = 3367,\n+\t[BNXT_ULP_CLASS_HID_3b070] = 3368,\n+\t[BNXT_ULP_CLASS_HID_238d0] = 3369,\n+\t[BNXT_ULP_CLASS_HID_2a5d0] = 3370,\n+\t[BNXT_ULP_CLASS_HID_32ed0] = 3371,\n+\t[BNXT_ULP_CLASS_HID_3dbd0] = 3372,\n+\t[BNXT_ULP_CLASS_HID_20420] = 3373,\n+\t[BNXT_ULP_CLASS_HID_2b120] = 3374,\n+\t[BNXT_ULP_CLASS_HID_33a20] = 3375,\n+\t[BNXT_ULP_CLASS_HID_3a720] = 3376,\n+\t[BNXT_ULP_CLASS_HID_200d4] = 3377,\n+\t[BNXT_ULP_CLASS_HID_28dd4] = 3378,\n+\t[BNXT_ULP_CLASS_HID_336d4] = 3379,\n+\t[BNXT_ULP_CLASS_HID_3a3d4] = 3380,\n+\t[BNXT_ULP_CLASS_HID_23584] = 3381,\n+\t[BNXT_ULP_CLASS_HID_2be84] = 3382,\n+\t[BNXT_ULP_CLASS_HID_32b84] = 3383,\n+\t[BNXT_ULP_CLASS_HID_3d484] = 3384,\n+\t[BNXT_ULP_CLASS_HID_25d64] = 3385,\n+\t[BNXT_ULP_CLASS_HID_2c664] = 3386,\n+\t[BNXT_ULP_CLASS_HID_31418] = 3387,\n+\t[BNXT_ULP_CLASS_HID_38118] = 3388,\n+\t[BNXT_ULP_CLASS_HID_228b4] = 3389,\n+\t[BNXT_ULP_CLASS_HID_2d5b4] = 3390,\n+\t[BNXT_ULP_CLASS_HID_35eb4] = 3391,\n+\t[BNXT_ULP_CLASS_HID_3cbb4] = 3392,\n+\t[BNXT_ULP_CLASS_HID_22568] = 3393,\n+\t[BNXT_ULP_CLASS_HID_2ae68] = 3394,\n+\t[BNXT_ULP_CLASS_HID_35b68] = 3395,\n+\t[BNXT_ULP_CLASS_HID_3c468] = 3396,\n+\t[BNXT_ULP_CLASS_HID_25618] = 3397,\n+\t[BNXT_ULP_CLASS_HID_2c318] = 3398,\n+\t[BNXT_ULP_CLASS_HID_310cc] = 3399,\n+\t[BNXT_ULP_CLASS_HID_39dcc] = 3400,\n+\t[BNXT_ULP_CLASS_HID_229b8] = 3401,\n+\t[BNXT_ULP_CLASS_HID_2d2b8] = 3402,\n+\t[BNXT_ULP_CLASS_HID_35fb8] = 3403,\n+\t[BNXT_ULP_CLASS_HID_3c8b8] = 3404,\n+\t[BNXT_ULP_CLASS_HID_23488] = 3405,\n+\t[BNXT_ULP_CLASS_HID_2a188] = 3406,\n+\t[BNXT_ULP_CLASS_HID_32a88] = 3407,\n+\t[BNXT_ULP_CLASS_HID_3d788] = 3408,\n+\t[BNXT_ULP_CLASS_HID_231bc] = 3409,\n+\t[BNXT_ULP_CLASS_HID_2babc] = 3410,\n+\t[BNXT_ULP_CLASS_HID_327bc] = 3411,\n+\t[BNXT_ULP_CLASS_HID_3d0bc] = 3412,\n+\t[BNXT_ULP_CLASS_HID_2226c] = 3413,\n+\t[BNXT_ULP_CLASS_HID_2af6c] = 3414,\n+\t[BNXT_ULP_CLASS_HID_3586c] = 3415,\n+\t[BNXT_ULP_CLASS_HID_3c56c] = 3416,\n+\t[BNXT_ULP_CLASS_HID_24dcc] = 3417,\n+\t[BNXT_ULP_CLASS_HID_29b80] = 3418,\n+\t[BNXT_ULP_CLASS_HID_30480] = 3419,\n+\t[BNXT_ULP_CLASS_HID_3b180] = 3420,\n+\t[BNXT_ULP_CLASS_HID_2591c] = 3421,\n+\t[BNXT_ULP_CLASS_HID_2c21c] = 3422,\n+\t[BNXT_ULP_CLASS_HID_313d0] = 3423,\n+\t[BNXT_ULP_CLASS_HID_39cd0] = 3424,\n+\t[BNXT_ULP_CLASS_HID_255d0] = 3425,\n+\t[BNXT_ULP_CLASS_HID_2ded0] = 3426,\n+\t[BNXT_ULP_CLASS_HID_34bd0] = 3427,\n+\t[BNXT_ULP_CLASS_HID_39984] = 3428,\n+\t[BNXT_ULP_CLASS_HID_24680] = 3429,\n+\t[BNXT_ULP_CLASS_HID_294b4] = 3430,\n+\t[BNXT_ULP_CLASS_HID_301b4] = 3431,\n+\t[BNXT_ULP_CLASS_HID_38ab4] = 3432,\n+\t[BNXT_ULP_CLASS_HID_23314] = 3433,\n+\t[BNXT_ULP_CLASS_HID_2bc14] = 3434,\n+\t[BNXT_ULP_CLASS_HID_32914] = 3435,\n+\t[BNXT_ULP_CLASS_HID_3d214] = 3436,\n+\t[BNXT_ULP_CLASS_HID_21e64] = 3437,\n+\t[BNXT_ULP_CLASS_HID_28b64] = 3438,\n+\t[BNXT_ULP_CLASS_HID_33464] = 3439,\n+\t[BNXT_ULP_CLASS_HID_3a164] = 3440,\n+\t[BNXT_ULP_CLASS_HID_21b18] = 3441,\n+\t[BNXT_ULP_CLASS_HID_28418] = 3442,\n+\t[BNXT_ULP_CLASS_HID_33118] = 3443,\n+\t[BNXT_ULP_CLASS_HID_3ba18] = 3444,\n+\t[BNXT_ULP_CLASS_HID_20fc8] = 3445,\n+\t[BNXT_ULP_CLASS_HID_2b8c8] = 3446,\n+\t[BNXT_ULP_CLASS_HID_325c8] = 3447,\n+\t[BNXT_ULP_CLASS_HID_3aec8] = 3448,\n+\t[BNXT_ULP_CLASS_HID_257a8] = 3449,\n+\t[BNXT_ULP_CLASS_HID_2c0a8] = 3450,\n+\t[BNXT_ULP_CLASS_HID_34da8] = 3451,\n+\t[BNXT_ULP_CLASS_HID_39b5c] = 3452,\n+\t[BNXT_ULP_CLASS_HID_222f8] = 3453,\n+\t[BNXT_ULP_CLASS_HID_2aff8] = 3454,\n+\t[BNXT_ULP_CLASS_HID_358f8] = 3455,\n+\t[BNXT_ULP_CLASS_HID_3c5f8] = 3456,\n+\t[BNXT_ULP_CLASS_HID_23fac] = 3457,\n+\t[BNXT_ULP_CLASS_HID_2a8ac] = 3458,\n+\t[BNXT_ULP_CLASS_HID_355ac] = 3459,\n+\t[BNXT_ULP_CLASS_HID_3deac] = 3460,\n+\t[BNXT_ULP_CLASS_HID_2505c] = 3461,\n+\t[BNXT_ULP_CLASS_HID_2dd5c] = 3462,\n+\t[BNXT_ULP_CLASS_HID_3465c] = 3463,\n+\t[BNXT_ULP_CLASS_HID_39410] = 3464,\n+\t[BNXT_ULP_CLASS_HID_223fc] = 3465,\n+\t[BNXT_ULP_CLASS_HID_2acfc] = 3466,\n+\t[BNXT_ULP_CLASS_HID_359fc] = 3467,\n+\t[BNXT_ULP_CLASS_HID_3c2fc] = 3468,\n+\t[BNXT_ULP_CLASS_HID_20ecc] = 3469,\n+\t[BNXT_ULP_CLASS_HID_2bbcc] = 3470,\n+\t[BNXT_ULP_CLASS_HID_324cc] = 3471,\n+\t[BNXT_ULP_CLASS_HID_3d1cc] = 3472,\n+\t[BNXT_ULP_CLASS_HID_20b80] = 3473,\n+\t[BNXT_ULP_CLASS_HID_2b480] = 3474,\n+\t[BNXT_ULP_CLASS_HID_32180] = 3475,\n+\t[BNXT_ULP_CLASS_HID_3aa80] = 3476,\n+\t[BNXT_ULP_CLASS_HID_23cb0] = 3477,\n+\t[BNXT_ULP_CLASS_HID_2a9b0] = 3478,\n+\t[BNXT_ULP_CLASS_HID_352b0] = 3479,\n+\t[BNXT_ULP_CLASS_HID_3dfb0] = 3480,\n+\t[BNXT_ULP_CLASS_HID_24410] = 3481,\n+\t[BNXT_ULP_CLASS_HID_295c4] = 3482,\n+\t[BNXT_ULP_CLASS_HID_31ec4] = 3483,\n+\t[BNXT_ULP_CLASS_HID_38bc4] = 3484,\n+\t[BNXT_ULP_CLASS_HID_25360] = 3485,\n+\t[BNXT_ULP_CLASS_HID_2dc60] = 3486,\n+\t[BNXT_ULP_CLASS_HID_34960] = 3487,\n+\t[BNXT_ULP_CLASS_HID_39714] = 3488,\n+\t[BNXT_ULP_CLASS_HID_22c14] = 3489,\n+\t[BNXT_ULP_CLASS_HID_2d914] = 3490,\n+\t[BNXT_ULP_CLASS_HID_34214] = 3491,\n+\t[BNXT_ULP_CLASS_HID_393c8] = 3492,\n+\t[BNXT_ULP_CLASS_HID_240c4] = 3493,\n+\t[BNXT_ULP_CLASS_HID_2cdc4] = 3494,\n+\t[BNXT_ULP_CLASS_HID_31bf8] = 3495,\n+\t[BNXT_ULP_CLASS_HID_384f8] = 3496,\n+\t[BNXT_ULP_CLASS_HID_23dc0] = 3497,\n+\t[BNXT_ULP_CLASS_HID_2a6c0] = 3498,\n+\t[BNXT_ULP_CLASS_HID_353c0] = 3499,\n+\t[BNXT_ULP_CLASS_HID_3dcc0] = 3500,\n+\t[BNXT_ULP_CLASS_HID_20910] = 3501,\n+\t[BNXT_ULP_CLASS_HID_2b210] = 3502,\n+\t[BNXT_ULP_CLASS_HID_33f10] = 3503,\n+\t[BNXT_ULP_CLASS_HID_3a810] = 3504,\n+\t[BNXT_ULP_CLASS_HID_205c4] = 3505,\n+\t[BNXT_ULP_CLASS_HID_28ec4] = 3506,\n+\t[BNXT_ULP_CLASS_HID_33bc4] = 3507,\n+\t[BNXT_ULP_CLASS_HID_3a4c4] = 3508,\n+\t[BNXT_ULP_CLASS_HID_236f4] = 3509,\n+\t[BNXT_ULP_CLASS_HID_2a3f4] = 3510,\n+\t[BNXT_ULP_CLASS_HID_32cf4] = 3511,\n+\t[BNXT_ULP_CLASS_HID_3d9f4] = 3512,\n+\t[BNXT_ULP_CLASS_HID_25e54] = 3513,\n+\t[BNXT_ULP_CLASS_HID_2cb54] = 3514,\n+\t[BNXT_ULP_CLASS_HID_31908] = 3515,\n+\t[BNXT_ULP_CLASS_HID_38208] = 3516,\n+\t[BNXT_ULP_CLASS_HID_22da4] = 3517,\n+\t[BNXT_ULP_CLASS_HID_2d6a4] = 3518,\n+\t[BNXT_ULP_CLASS_HID_343a4] = 3519,\n+\t[BNXT_ULP_CLASS_HID_39158] = 3520,\n+\t[BNXT_ULP_CLASS_HID_22658] = 3521,\n+\t[BNXT_ULP_CLASS_HID_2d358] = 3522,\n+\t[BNXT_ULP_CLASS_HID_35c58] = 3523,\n+\t[BNXT_ULP_CLASS_HID_3c958] = 3524,\n+\t[BNXT_ULP_CLASS_HID_25b08] = 3525,\n+\t[BNXT_ULP_CLASS_HID_2c408] = 3526,\n+\t[BNXT_ULP_CLASS_HID_3123c] = 3527,\n+\t[BNXT_ULP_CLASS_HID_39f3c] = 3528,\n+\t[BNXT_ULP_CLASS_HID_34a8] = 3529,\n+\t[BNXT_ULP_CLASS_HID_3a64] = 3530,\n+\t[BNXT_ULP_CLASS_HID_5ef8] = 3531,\n+\t[BNXT_ULP_CLASS_HID_07c0] = 3532,\n+\t[BNXT_ULP_CLASS_HID_2854] = 3533,\n+\t[BNXT_ULP_CLASS_HID_593c] = 3534,\n+\t[BNXT_ULP_CLASS_HID_1e04] = 3535,\n+\t[BNXT_ULP_CLASS_HID_2298] = 3536,\n+\t[BNXT_ULP_CLASS_HID_24644] = 3537,\n+\t[BNXT_ULP_CLASS_HID_29438] = 3538,\n+\t[BNXT_ULP_CLASS_HID_30138] = 3539,\n+\t[BNXT_ULP_CLASS_HID_38a38] = 3540,\n+\t[BNXT_ULP_CLASS_HID_25594] = 3541,\n+\t[BNXT_ULP_CLASS_HID_2de94] = 3542,\n+\t[BNXT_ULP_CLASS_HID_34b94] = 3543,\n+\t[BNXT_ULP_CLASS_HID_39948] = 3544,\n+\t[BNXT_ULP_CLASS_HID_22e48] = 3545,\n+\t[BNXT_ULP_CLASS_HID_2db48] = 3546,\n+\t[BNXT_ULP_CLASS_HID_34448] = 3547,\n+\t[BNXT_ULP_CLASS_HID_3923c] = 3548,\n+\t[BNXT_ULP_CLASS_HID_24338] = 3549,\n+\t[BNXT_ULP_CLASS_HID_290ec] = 3550,\n+\t[BNXT_ULP_CLASS_HID_31dec] = 3551,\n+\t[BNXT_ULP_CLASS_HID_386ec] = 3552,\n+\t[BNXT_ULP_CLASS_HID_20f8c] = 3553,\n+\t[BNXT_ULP_CLASS_HID_2b88c] = 3554,\n+\t[BNXT_ULP_CLASS_HID_3258c] = 3555,\n+\t[BNXT_ULP_CLASS_HID_3ae8c] = 3556,\n+\t[BNXT_ULP_CLASS_HID_21adc] = 3557,\n+\t[BNXT_ULP_CLASS_HID_287dc] = 3558,\n+\t[BNXT_ULP_CLASS_HID_330dc] = 3559,\n+\t[BNXT_ULP_CLASS_HID_3bddc] = 3560,\n+\t[BNXT_ULP_CLASS_HID_21790] = 3561,\n+\t[BNXT_ULP_CLASS_HID_28090] = 3562,\n+\t[BNXT_ULP_CLASS_HID_30d90] = 3563,\n+\t[BNXT_ULP_CLASS_HID_3b690] = 3564,\n+\t[BNXT_ULP_CLASS_HID_20840] = 3565,\n+\t[BNXT_ULP_CLASS_HID_2b540] = 3566,\n+\t[BNXT_ULP_CLASS_HID_33e40] = 3567,\n+\t[BNXT_ULP_CLASS_HID_3ab40] = 3568,\n+\t[BNXT_ULP_CLASS_HID_253e0] = 3569,\n+\t[BNXT_ULP_CLASS_HID_2dce0] = 3570,\n+\t[BNXT_ULP_CLASS_HID_349e0] = 3571,\n+\t[BNXT_ULP_CLASS_HID_397d4] = 3572,\n+\t[BNXT_ULP_CLASS_HID_23f30] = 3573,\n+\t[BNXT_ULP_CLASS_HID_2a830] = 3574,\n+\t[BNXT_ULP_CLASS_HID_35530] = 3575,\n+\t[BNXT_ULP_CLASS_HID_3de30] = 3576,\n+\t[BNXT_ULP_CLASS_HID_23be4] = 3577,\n+\t[BNXT_ULP_CLASS_HID_2a4e4] = 3578,\n+\t[BNXT_ULP_CLASS_HID_351e4] = 3579,\n+\t[BNXT_ULP_CLASS_HID_3dae4] = 3580,\n+\t[BNXT_ULP_CLASS_HID_22cd4] = 3581,\n+\t[BNXT_ULP_CLASS_HID_2d9d4] = 3582,\n+\t[BNXT_ULP_CLASS_HID_342d4] = 3583,\n+\t[BNXT_ULP_CLASS_HID_39088] = 3584,\n+\t[BNXT_ULP_CLASS_HID_21928] = 3585,\n+\t[BNXT_ULP_CLASS_HID_28228] = 3586,\n+\t[BNXT_ULP_CLASS_HID_30f28] = 3587,\n+\t[BNXT_ULP_CLASS_HID_3b828] = 3588,\n+\t[BNXT_ULP_CLASS_HID_24384] = 3589,\n+\t[BNXT_ULP_CLASS_HID_29178] = 3590,\n+\t[BNXT_ULP_CLASS_HID_31a78] = 3591,\n+\t[BNXT_ULP_CLASS_HID_38778] = 3592,\n+\t[BNXT_ULP_CLASS_HID_25c78] = 3593,\n+\t[BNXT_ULP_CLASS_HID_2c978] = 3594,\n+\t[BNXT_ULP_CLASS_HID_3172c] = 3595,\n+\t[BNXT_ULP_CLASS_HID_3802c] = 3596,\n+\t[BNXT_ULP_CLASS_HID_2121c] = 3597,\n+\t[BNXT_ULP_CLASS_HID_29f1c] = 3598,\n+\t[BNXT_ULP_CLASS_HID_3081c] = 3599,\n+\t[BNXT_ULP_CLASS_HID_3b51c] = 3600,\n+\t[BNXT_ULP_CLASS_HID_24088] = 3601,\n+\t[BNXT_ULP_CLASS_HID_2cd88] = 3602,\n+\t[BNXT_ULP_CLASS_HID_31b7c] = 3603,\n+\t[BNXT_ULP_CLASS_HID_3847c] = 3604,\n+\t[BNXT_ULP_CLASS_HID_22fd8] = 3605,\n+\t[BNXT_ULP_CLASS_HID_2d8d8] = 3606,\n+\t[BNXT_ULP_CLASS_HID_345d8] = 3607,\n+\t[BNXT_ULP_CLASS_HID_3938c] = 3608,\n+\t[BNXT_ULP_CLASS_HID_2288c] = 3609,\n+\t[BNXT_ULP_CLASS_HID_2d58c] = 3610,\n+\t[BNXT_ULP_CLASS_HID_35e8c] = 3611,\n+\t[BNXT_ULP_CLASS_HID_3cb8c] = 3612,\n+\t[BNXT_ULP_CLASS_HID_25d7c] = 3613,\n+\t[BNXT_ULP_CLASS_HID_2c67c] = 3614,\n+\t[BNXT_ULP_CLASS_HID_31430] = 3615,\n+\t[BNXT_ULP_CLASS_HID_38130] = 3616,\n+\t[BNXT_ULP_CLASS_HID_209d0] = 3617,\n+\t[BNXT_ULP_CLASS_HID_2b2d0] = 3618,\n+\t[BNXT_ULP_CLASS_HID_33fd0] = 3619,\n+\t[BNXT_ULP_CLASS_HID_3a8d0] = 3620,\n+\t[BNXT_ULP_CLASS_HID_214e0] = 3621,\n+\t[BNXT_ULP_CLASS_HID_281e0] = 3622,\n+\t[BNXT_ULP_CLASS_HID_30ae0] = 3623,\n+\t[BNXT_ULP_CLASS_HID_3b7e0] = 3624,\n+\t[BNXT_ULP_CLASS_HID_211d4] = 3625,\n+\t[BNXT_ULP_CLASS_HID_29ad4] = 3626,\n+\t[BNXT_ULP_CLASS_HID_307d4] = 3627,\n+\t[BNXT_ULP_CLASS_HID_3b0d4] = 3628,\n+\t[BNXT_ULP_CLASS_HID_20284] = 3629,\n+\t[BNXT_ULP_CLASS_HID_28f84] = 3630,\n+\t[BNXT_ULP_CLASS_HID_33884] = 3631,\n+\t[BNXT_ULP_CLASS_HID_3a584] = 3632,\n+\t[BNXT_ULP_CLASS_HID_22a24] = 3633,\n+\t[BNXT_ULP_CLASS_HID_2d724] = 3634,\n+\t[BNXT_ULP_CLASS_HID_34024] = 3635,\n+\t[BNXT_ULP_CLASS_HID_3cd24] = 3636,\n+\t[BNXT_ULP_CLASS_HID_23974] = 3637,\n+\t[BNXT_ULP_CLASS_HID_2a274] = 3638,\n+\t[BNXT_ULP_CLASS_HID_32f74] = 3639,\n+\t[BNXT_ULP_CLASS_HID_3d874] = 3640,\n+\t[BNXT_ULP_CLASS_HID_23228] = 3641,\n+\t[BNXT_ULP_CLASS_HID_2bf28] = 3642,\n+\t[BNXT_ULP_CLASS_HID_32828] = 3643,\n+\t[BNXT_ULP_CLASS_HID_3d528] = 3644,\n+\t[BNXT_ULP_CLASS_HID_22718] = 3645,\n+\t[BNXT_ULP_CLASS_HID_2d018] = 3646,\n+\t[BNXT_ULP_CLASS_HID_35d18] = 3647,\n+\t[BNXT_ULP_CLASS_HID_3c618] = 3648,\n+\t[BNXT_ULP_CLASS_HID_2136c] = 3649,\n+\t[BNXT_ULP_CLASS_HID_29c6c] = 3650,\n+\t[BNXT_ULP_CLASS_HID_3096c] = 3651,\n+\t[BNXT_ULP_CLASS_HID_3b26c] = 3652,\n+\t[BNXT_ULP_CLASS_HID_25dc8] = 3653,\n+\t[BNXT_ULP_CLASS_HID_2c6c8] = 3654,\n+\t[BNXT_ULP_CLASS_HID_314bc] = 3655,\n+\t[BNXT_ULP_CLASS_HID_381bc] = 3656,\n+\t[BNXT_ULP_CLASS_HID_256bc] = 3657,\n+\t[BNXT_ULP_CLASS_HID_2c3bc] = 3658,\n+\t[BNXT_ULP_CLASS_HID_31170] = 3659,\n+\t[BNXT_ULP_CLASS_HID_39a70] = 3660,\n+\t[BNXT_ULP_CLASS_HID_24b6c] = 3661,\n+\t[BNXT_ULP_CLASS_HID_29920] = 3662,\n+\t[BNXT_ULP_CLASS_HID_30220] = 3663,\n+\t[BNXT_ULP_CLASS_HID_38f20] = 3664,\n+\t[BNXT_ULP_CLASS_HID_22f54] = 3665,\n+\t[BNXT_ULP_CLASS_HID_2d854] = 3666,\n+\t[BNXT_ULP_CLASS_HID_34554] = 3667,\n+\t[BNXT_ULP_CLASS_HID_39308] = 3668,\n+\t[BNXT_ULP_CLASS_HID_23a64] = 3669,\n+\t[BNXT_ULP_CLASS_HID_2a764] = 3670,\n+\t[BNXT_ULP_CLASS_HID_35064] = 3671,\n+\t[BNXT_ULP_CLASS_HID_3dd64] = 3672,\n+\t[BNXT_ULP_CLASS_HID_23758] = 3673,\n+\t[BNXT_ULP_CLASS_HID_2a058] = 3674,\n+\t[BNXT_ULP_CLASS_HID_32d58] = 3675,\n+\t[BNXT_ULP_CLASS_HID_3d658] = 3676,\n+\t[BNXT_ULP_CLASS_HID_22808] = 3677,\n+\t[BNXT_ULP_CLASS_HID_2d508] = 3678,\n+\t[BNXT_ULP_CLASS_HID_35e08] = 3679,\n+\t[BNXT_ULP_CLASS_HID_3cb08] = 3680,\n+\t[BNXT_ULP_CLASS_HID_2149c] = 3681,\n+\t[BNXT_ULP_CLASS_HID_2819c] = 3682,\n+\t[BNXT_ULP_CLASS_HID_30a9c] = 3683,\n+\t[BNXT_ULP_CLASS_HID_3b79c] = 3684,\n+\t[BNXT_ULP_CLASS_HID_25ef8] = 3685,\n+\t[BNXT_ULP_CLASS_HID_2cbf8] = 3686,\n+\t[BNXT_ULP_CLASS_HID_319ac] = 3687,\n+\t[BNXT_ULP_CLASS_HID_382ac] = 3688,\n+\t[BNXT_ULP_CLASS_HID_25bac] = 3689,\n+\t[BNXT_ULP_CLASS_HID_2c4ac] = 3690,\n+\t[BNXT_ULP_CLASS_HID_31260] = 3691,\n+\t[BNXT_ULP_CLASS_HID_39f60] = 3692,\n+\t[BNXT_ULP_CLASS_HID_21150] = 3693,\n+\t[BNXT_ULP_CLASS_HID_29a50] = 3694,\n+\t[BNXT_ULP_CLASS_HID_30750] = 3695,\n+\t[BNXT_ULP_CLASS_HID_3b050] = 3696,\n+\t[BNXT_ULP_CLASS_HID_238f0] = 3697,\n+\t[BNXT_ULP_CLASS_HID_2a5f0] = 3698,\n+\t[BNXT_ULP_CLASS_HID_32ef0] = 3699,\n+\t[BNXT_ULP_CLASS_HID_3dbf0] = 3700,\n+\t[BNXT_ULP_CLASS_HID_20400] = 3701,\n+\t[BNXT_ULP_CLASS_HID_2b100] = 3702,\n+\t[BNXT_ULP_CLASS_HID_33a00] = 3703,\n+\t[BNXT_ULP_CLASS_HID_3a700] = 3704,\n+\t[BNXT_ULP_CLASS_HID_200f4] = 3705,\n+\t[BNXT_ULP_CLASS_HID_28df4] = 3706,\n+\t[BNXT_ULP_CLASS_HID_336f4] = 3707,\n+\t[BNXT_ULP_CLASS_HID_3a3f4] = 3708,\n+\t[BNXT_ULP_CLASS_HID_235a4] = 3709,\n+\t[BNXT_ULP_CLASS_HID_2bea4] = 3710,\n+\t[BNXT_ULP_CLASS_HID_32ba4] = 3711,\n+\t[BNXT_ULP_CLASS_HID_3d4a4] = 3712,\n+\t[BNXT_ULP_CLASS_HID_25d44] = 3713,\n+\t[BNXT_ULP_CLASS_HID_2c644] = 3714,\n+\t[BNXT_ULP_CLASS_HID_31438] = 3715,\n+\t[BNXT_ULP_CLASS_HID_38138] = 3716,\n+\t[BNXT_ULP_CLASS_HID_22894] = 3717,\n+\t[BNXT_ULP_CLASS_HID_2d594] = 3718,\n+\t[BNXT_ULP_CLASS_HID_35e94] = 3719,\n+\t[BNXT_ULP_CLASS_HID_3cb94] = 3720,\n+\t[BNXT_ULP_CLASS_HID_22548] = 3721,\n+\t[BNXT_ULP_CLASS_HID_2ae48] = 3722,\n+\t[BNXT_ULP_CLASS_HID_35b48] = 3723,\n+\t[BNXT_ULP_CLASS_HID_3c448] = 3724,\n+\t[BNXT_ULP_CLASS_HID_25638] = 3725,\n+\t[BNXT_ULP_CLASS_HID_2c338] = 3726,\n+\t[BNXT_ULP_CLASS_HID_310ec] = 3727,\n+\t[BNXT_ULP_CLASS_HID_39dec] = 3728,\n+\t[BNXT_ULP_CLASS_HID_22998] = 3729,\n+\t[BNXT_ULP_CLASS_HID_2d298] = 3730,\n+\t[BNXT_ULP_CLASS_HID_35f98] = 3731,\n+\t[BNXT_ULP_CLASS_HID_3c898] = 3732,\n+\t[BNXT_ULP_CLASS_HID_234a8] = 3733,\n+\t[BNXT_ULP_CLASS_HID_2a1a8] = 3734,\n+\t[BNXT_ULP_CLASS_HID_32aa8] = 3735,\n+\t[BNXT_ULP_CLASS_HID_3d7a8] = 3736,\n+\t[BNXT_ULP_CLASS_HID_2319c] = 3737,\n+\t[BNXT_ULP_CLASS_HID_2ba9c] = 3738,\n+\t[BNXT_ULP_CLASS_HID_3279c] = 3739,\n+\t[BNXT_ULP_CLASS_HID_3d09c] = 3740,\n+\t[BNXT_ULP_CLASS_HID_2224c] = 3741,\n+\t[BNXT_ULP_CLASS_HID_2af4c] = 3742,\n+\t[BNXT_ULP_CLASS_HID_3584c] = 3743,\n+\t[BNXT_ULP_CLASS_HID_3c54c] = 3744,\n+\t[BNXT_ULP_CLASS_HID_24dec] = 3745,\n+\t[BNXT_ULP_CLASS_HID_29ba0] = 3746,\n+\t[BNXT_ULP_CLASS_HID_304a0] = 3747,\n+\t[BNXT_ULP_CLASS_HID_3b1a0] = 3748,\n+\t[BNXT_ULP_CLASS_HID_2593c] = 3749,\n+\t[BNXT_ULP_CLASS_HID_2c23c] = 3750,\n+\t[BNXT_ULP_CLASS_HID_313f0] = 3751,\n+\t[BNXT_ULP_CLASS_HID_39cf0] = 3752,\n+\t[BNXT_ULP_CLASS_HID_255f0] = 3753,\n+\t[BNXT_ULP_CLASS_HID_2def0] = 3754,\n+\t[BNXT_ULP_CLASS_HID_34bf0] = 3755,\n+\t[BNXT_ULP_CLASS_HID_399a4] = 3756,\n+\t[BNXT_ULP_CLASS_HID_246a0] = 3757,\n+\t[BNXT_ULP_CLASS_HID_29494] = 3758,\n+\t[BNXT_ULP_CLASS_HID_30194] = 3759,\n+\t[BNXT_ULP_CLASS_HID_38a94] = 3760,\n+\t[BNXT_ULP_CLASS_HID_23334] = 3761,\n+\t[BNXT_ULP_CLASS_HID_2bc34] = 3762,\n+\t[BNXT_ULP_CLASS_HID_32934] = 3763,\n+\t[BNXT_ULP_CLASS_HID_3d234] = 3764,\n+\t[BNXT_ULP_CLASS_HID_21e44] = 3765,\n+\t[BNXT_ULP_CLASS_HID_28b44] = 3766,\n+\t[BNXT_ULP_CLASS_HID_33444] = 3767,\n+\t[BNXT_ULP_CLASS_HID_3a144] = 3768,\n+\t[BNXT_ULP_CLASS_HID_21b38] = 3769,\n+\t[BNXT_ULP_CLASS_HID_28438] = 3770,\n+\t[BNXT_ULP_CLASS_HID_33138] = 3771,\n+\t[BNXT_ULP_CLASS_HID_3ba38] = 3772,\n+\t[BNXT_ULP_CLASS_HID_20fe8] = 3773,\n+\t[BNXT_ULP_CLASS_HID_2b8e8] = 3774,\n+\t[BNXT_ULP_CLASS_HID_325e8] = 3775,\n+\t[BNXT_ULP_CLASS_HID_3aee8] = 3776,\n+\t[BNXT_ULP_CLASS_HID_25788] = 3777,\n+\t[BNXT_ULP_CLASS_HID_2c088] = 3778,\n+\t[BNXT_ULP_CLASS_HID_34d88] = 3779,\n+\t[BNXT_ULP_CLASS_HID_39b7c] = 3780,\n+\t[BNXT_ULP_CLASS_HID_222d8] = 3781,\n+\t[BNXT_ULP_CLASS_HID_2afd8] = 3782,\n+\t[BNXT_ULP_CLASS_HID_358d8] = 3783,\n+\t[BNXT_ULP_CLASS_HID_3c5d8] = 3784,\n+\t[BNXT_ULP_CLASS_HID_23f8c] = 3785,\n+\t[BNXT_ULP_CLASS_HID_2a88c] = 3786,\n+\t[BNXT_ULP_CLASS_HID_3558c] = 3787,\n+\t[BNXT_ULP_CLASS_HID_3de8c] = 3788,\n+\t[BNXT_ULP_CLASS_HID_2507c] = 3789,\n+\t[BNXT_ULP_CLASS_HID_2dd7c] = 3790,\n+\t[BNXT_ULP_CLASS_HID_3467c] = 3791,\n+\t[BNXT_ULP_CLASS_HID_39430] = 3792,\n+\t[BNXT_ULP_CLASS_HID_223dc] = 3793,\n+\t[BNXT_ULP_CLASS_HID_2acdc] = 3794,\n+\t[BNXT_ULP_CLASS_HID_359dc] = 3795,\n+\t[BNXT_ULP_CLASS_HID_3c2dc] = 3796,\n+\t[BNXT_ULP_CLASS_HID_20eec] = 3797,\n+\t[BNXT_ULP_CLASS_HID_2bbec] = 3798,\n+\t[BNXT_ULP_CLASS_HID_324ec] = 3799,\n+\t[BNXT_ULP_CLASS_HID_3d1ec] = 3800,\n+\t[BNXT_ULP_CLASS_HID_20ba0] = 3801,\n+\t[BNXT_ULP_CLASS_HID_2b4a0] = 3802,\n+\t[BNXT_ULP_CLASS_HID_321a0] = 3803,\n+\t[BNXT_ULP_CLASS_HID_3aaa0] = 3804,\n+\t[BNXT_ULP_CLASS_HID_23c90] = 3805,\n+\t[BNXT_ULP_CLASS_HID_2a990] = 3806,\n+\t[BNXT_ULP_CLASS_HID_35290] = 3807,\n+\t[BNXT_ULP_CLASS_HID_3df90] = 3808,\n+\t[BNXT_ULP_CLASS_HID_24430] = 3809,\n+\t[BNXT_ULP_CLASS_HID_295e4] = 3810,\n+\t[BNXT_ULP_CLASS_HID_31ee4] = 3811,\n+\t[BNXT_ULP_CLASS_HID_38be4] = 3812,\n+\t[BNXT_ULP_CLASS_HID_25340] = 3813,\n+\t[BNXT_ULP_CLASS_HID_2dc40] = 3814,\n+\t[BNXT_ULP_CLASS_HID_34940] = 3815,\n+\t[BNXT_ULP_CLASS_HID_39734] = 3816,\n+\t[BNXT_ULP_CLASS_HID_22c34] = 3817,\n+\t[BNXT_ULP_CLASS_HID_2d934] = 3818,\n+\t[BNXT_ULP_CLASS_HID_34234] = 3819,\n+\t[BNXT_ULP_CLASS_HID_393e8] = 3820,\n+\t[BNXT_ULP_CLASS_HID_240e4] = 3821,\n+\t[BNXT_ULP_CLASS_HID_2cde4] = 3822,\n+\t[BNXT_ULP_CLASS_HID_31bd8] = 3823,\n+\t[BNXT_ULP_CLASS_HID_384d8] = 3824,\n+\t[BNXT_ULP_CLASS_HID_23de0] = 3825,\n+\t[BNXT_ULP_CLASS_HID_2a6e0] = 3826,\n+\t[BNXT_ULP_CLASS_HID_353e0] = 3827,\n+\t[BNXT_ULP_CLASS_HID_3dce0] = 3828,\n+\t[BNXT_ULP_CLASS_HID_20930] = 3829,\n+\t[BNXT_ULP_CLASS_HID_2b230] = 3830,\n+\t[BNXT_ULP_CLASS_HID_33f30] = 3831,\n+\t[BNXT_ULP_CLASS_HID_3a830] = 3832,\n+\t[BNXT_ULP_CLASS_HID_205e4] = 3833,\n+\t[BNXT_ULP_CLASS_HID_28ee4] = 3834,\n+\t[BNXT_ULP_CLASS_HID_33be4] = 3835,\n+\t[BNXT_ULP_CLASS_HID_3a4e4] = 3836,\n+\t[BNXT_ULP_CLASS_HID_236d4] = 3837,\n+\t[BNXT_ULP_CLASS_HID_2a3d4] = 3838,\n+\t[BNXT_ULP_CLASS_HID_32cd4] = 3839,\n+\t[BNXT_ULP_CLASS_HID_3d9d4] = 3840,\n+\t[BNXT_ULP_CLASS_HID_25e74] = 3841,\n+\t[BNXT_ULP_CLASS_HID_2cb74] = 3842,\n+\t[BNXT_ULP_CLASS_HID_31928] = 3843,\n+\t[BNXT_ULP_CLASS_HID_38228] = 3844,\n+\t[BNXT_ULP_CLASS_HID_22d84] = 3845,\n+\t[BNXT_ULP_CLASS_HID_2d684] = 3846,\n+\t[BNXT_ULP_CLASS_HID_34384] = 3847,\n+\t[BNXT_ULP_CLASS_HID_39178] = 3848,\n+\t[BNXT_ULP_CLASS_HID_22678] = 3849,\n+\t[BNXT_ULP_CLASS_HID_2d378] = 3850,\n+\t[BNXT_ULP_CLASS_HID_35c78] = 3851,\n+\t[BNXT_ULP_CLASS_HID_3c978] = 3852,\n+\t[BNXT_ULP_CLASS_HID_25b28] = 3853,\n+\t[BNXT_ULP_CLASS_HID_2c428] = 3854,\n+\t[BNXT_ULP_CLASS_HID_3121c] = 3855,\n+\t[BNXT_ULP_CLASS_HID_39f1c] = 3856,\n+\t[BNXT_ULP_CLASS_HID_3488] = 3857,\n+\t[BNXT_ULP_CLASS_HID_3a44] = 3858,\n+\t[BNXT_ULP_CLASS_HID_5ed8] = 3859,\n+\t[BNXT_ULP_CLASS_HID_07e0] = 3860,\n+\t[BNXT_ULP_CLASS_HID_2874] = 3861,\n+\t[BNXT_ULP_CLASS_HID_591c] = 3862,\n+\t[BNXT_ULP_CLASS_HID_1e24] = 3863,\n+\t[BNXT_ULP_CLASS_HID_22b8] = 3864\n };\n \n /* Array for the proto matcher list */\n struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t[1] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005c,\n+\t.class_hid = BNXT_ULP_CLASS_HID_26d1,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 0,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[2] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0003,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0071,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 1,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[3] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0132,\n+\t.class_hid = BNXT_ULP_CLASS_HID_53a5,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 1,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[4] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00e1,\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d49,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n-\t.flow_sig_id = 1,\n+\t.flow_sig_id = 2,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[5] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0044,\n+\t.class_hid = BNXT_ULP_CLASS_HID_2095,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 1,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 2,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[6] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_001b,\n+\t.class_hid = BNXT_ULP_CLASS_HID_5701,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 2,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[7] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_012a,\n+\t.class_hid = BNXT_ULP_CLASS_HID_4d79,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 2,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[8] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00f9,\n+\t.class_hid = BNXT_ULP_CLASS_HID_170d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 2,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[9] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_018d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a69,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 2,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[10] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00a7,\n+\t.class_hid = BNXT_ULP_CLASS_HID_50c5,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 3,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[11] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_006f,\n+\t.class_hid = BNXT_ULP_CLASS_HID_473d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 3,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[12] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0181,\n+\t.class_hid = BNXT_ULP_CLASS_HID_10c1,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 2,\n-\t.flow_sig_id = 3,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 4,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[13] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0195,\n+\t.class_hid = BNXT_ULP_CLASS_HID_142d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n-\t.flow_sig_id = 3,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 4,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[14] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00bf,\n+\t.class_hid = BNXT_ULP_CLASS_HID_4a99,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 4,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[15] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0077,\n+\t.class_hid = BNXT_ULP_CLASS_HID_40f1,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 4,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[16] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0199,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0a85,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 3,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 4,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[17] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_009a,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0179,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 4,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[18] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0192,\n+\t.class_hid = BNXT_ULP_CLASS_HID_37d5,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 5,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[19] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01e2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e4d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 5,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[20] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00fa,\n+\t.class_hid = BNXT_ULP_CLASS_HID_54ad,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 6,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[21] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0165,\n+\t.class_hid = BNXT_ULP_CLASS_HID_5809,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 4,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 6,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[22] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0042,\n+\t.class_hid = BNXT_ULP_CLASS_HID_31a9,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 6,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[23] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00cd,\n+\t.class_hid = BNXT_ULP_CLASS_HID_2801,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 6,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[24] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01aa,\n+\t.class_hid = BNXT_ULP_CLASS_HID_4e61,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 6,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[25] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0178,\n+\t.class_hid = BNXT_ULP_CLASS_HID_2561,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 6,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[26] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0070,\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bad,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 7,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[27] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00f3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_26f1,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 7,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[28] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01d8,\n+\t.class_hid = BNXT_ULP_CLASS_HID_13cf1,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 7,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[29] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005b,\n+\t.class_hid = BNXT_ULP_CLASS_HID_252f1,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 8,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[30] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0153,\n+\t.class_hid = BNXT_ULP_CLASS_HID_30c25,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 9,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[31] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01a3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0051,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 10,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[32] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00bb,\n+\t.class_hid = BNXT_ULP_CLASS_HID_11651,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 4,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 10,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[33] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0082,\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c51,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 10,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[34] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_018a,\n+\t.class_hid = BNXT_ULP_CLASS_HID_34251,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 10,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[35] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01fa,\n+\t.class_hid = BNXT_ULP_CLASS_HID_5385,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 10,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[36] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00e2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_10cc9,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 10,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[37] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_017d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_222c9,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 5,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 11,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[38] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005a,\n+\t.class_hid = BNXT_ULP_CLASS_HID_338c9,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 12,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[39] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d5,\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d69,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[40] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01b2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_13369,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[41] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0160,\n+\t.class_hid = BNXT_ULP_CLASS_HID_24969,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[42] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0068,\n+\t.class_hid = BNXT_ULP_CLASS_HID_3025d,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[43] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00eb,\n+\t.class_hid = BNXT_ULP_CLASS_HID_20b5,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[44] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01c0,\n+\t.class_hid = BNXT_ULP_CLASS_HID_136b5,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[45] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0043,\n+\t.class_hid = BNXT_ULP_CLASS_HID_24cb5,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[46] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_014b,\n+\t.class_hid = BNXT_ULP_CLASS_HID_305f9,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[47] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01bb,\n+\t.class_hid = BNXT_ULP_CLASS_HID_5721,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[48] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00a3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_11015,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 5,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n-\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[49] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00cb,\n+\t.class_hid = BNXT_ULP_CLASS_HID_22615,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[50] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00b4,\n+\t.class_hid = BNXT_ULP_CLASS_HID_33c15,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 6,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[51] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4d59,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[52] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1068d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[53] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21c8d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[54] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3328d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[55] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_172d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[56] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12d2d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[57] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2432d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[58] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3592d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[59] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a49,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[60] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13049,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 13,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[61] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24649,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 14,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[62] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35c49,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 15,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[63] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_50e5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 16,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[64] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10a29,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 16,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[65] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22029,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 16,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[66] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33629,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 16,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[67] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_471d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 16,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[68] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10041,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 16,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[69] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21641,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 17,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[70] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32c41,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 18,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[71] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10e1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[72] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_126e1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[73] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ce1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[74] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_352e1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[75] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_140d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[76] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12a0d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[77] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2400d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[78] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3560d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[79] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4ab9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[80] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_103ed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[81] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_219ed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[82] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32fed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[83] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_40d1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[84] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_156d1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[85] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21005,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[86] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32605,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[87] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0aa5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[88] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_120a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[89] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[90] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34ca5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[91] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0159,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[92] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11759,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 19,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[93] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22d59,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 20,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[94] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34359,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 21,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[95] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_37f5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 22,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[96] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_14df5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 22,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[97] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20739,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 22,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[98] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31d39,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 22,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[99] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e6d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 22,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[100] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1446d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 22,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[101] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25a6d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 23,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[102] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31351,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 24,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[103] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_548d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[104] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10df1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[105] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_223f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[106] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_339f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[107] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5829,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[108] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1111d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[109] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2271d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[110] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33d1d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[111] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3189,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[112] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_14789,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[113] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_200fd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[114] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_316fd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[115] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2821,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[116] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13e21,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[117] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25421,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[118] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30d15,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[119] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4e41,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[120] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_107b5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[121] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21db5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[122] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_333b5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[123] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2541,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[124] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b8d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[125] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2691,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[126] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13c91,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 25,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[127] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25291,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 26,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[128] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30c45,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 27,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[129] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0031,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 28,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[130] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11631,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 28,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[131] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c31,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 28,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[132] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34231,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 28,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[133] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_53e5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 28,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[134] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10ca9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 28,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[135] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_222a9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 29,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[136] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_338a9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 30,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[137] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d09,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[138] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13309,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[139] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24909,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[140] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3023d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[141] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[142] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_136d5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[143] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24cd5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[144] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30599,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[145] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5741,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[146] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11075,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[147] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22675,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[148] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33c75,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[149] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4d39,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[150] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_106ed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[151] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21ced,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[152] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_332ed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[153] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_174d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[154] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12d4d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[155] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2434d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[156] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3594d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[157] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a29,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[158] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13029,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 31,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[159] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24629,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 32,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[160] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35c29,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 33,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[161] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5085,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 34,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[162] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10a49,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 34,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[163] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22049,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 34,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[164] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33649,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 34,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[165] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_477d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 34,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[166] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10021,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 34,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[167] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21621,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 35,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[168] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32c21,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 36,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[169] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1081,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[170] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12681,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[171] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23c81,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[172] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35281,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[173] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_146d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[174] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12a6d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[175] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2406d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[176] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3566d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[177] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4ad9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[178] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1038d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[179] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2198d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[180] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32f8d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[181] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_40b1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[182] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_156b1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[183] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21065,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[184] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32665,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[185] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0ac5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[186] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_120c5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[187] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236c5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[188] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34cc5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[189] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0139,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[190] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11739,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 37,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[191] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22d39,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 38,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[192] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34339,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 39,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[193] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3795,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 40,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[194] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_14d95,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 40,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[195] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20759,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 40,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[196] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31d59,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 40,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[197] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e0d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 40,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[198] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1440d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 40,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[199] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25a0d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 41,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[200] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31331,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 42,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[201] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_54ed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[202] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10d91,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[203] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22391,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[204] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33991,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[205] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5849,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[206] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1117d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[207] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2277d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[208] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33d7d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[209] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[210] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_147e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[211] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2009d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[212] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3169d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[213] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2841,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[214] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13e41,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[215] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25441,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[216] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30d75,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[217] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4e21,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[218] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_107d5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[219] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21dd5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[220] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_333d5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[221] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2521,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[222] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[223] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1865,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 43,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[224] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_389d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 44,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[225] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_123d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 44,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[226] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4ef1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 45,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[227] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1229,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 45,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[228] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3241,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 45,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[229] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0be1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 45,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[230] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48b5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 45,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[231] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0bed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 45,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[232] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c05,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 46,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[233] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 46,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[234] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4279,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 47,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[235] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05d1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 47,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[236] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25c9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 47,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[237] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5c55,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 47,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[238] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c3d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 47,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[239] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4fc9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 47,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[240] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1335,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 48,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[241] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4981,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 48,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[242] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2969,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[243] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_498d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[244] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0cf9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[245] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4345,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[246] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_232d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[247] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2579,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[248] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bb5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[249] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1845,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[250] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1399,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 49,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[251] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0eed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 50,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[252] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0a21,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 51,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[253] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38bd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 52,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[254] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 52,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[255] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ec5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 52,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[256] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a19,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 52,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[257] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_121d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 52,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[258] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0d51,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 52,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[259] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_08a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 53,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[260] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03f9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 54,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[261] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4ed1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[262] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4a25,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[263] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4579,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[264] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_404d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[265] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1209,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[266] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0d5d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[267] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0891,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[268] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03e5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[269] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3261,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[270] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2db5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[271] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2889,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[272] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23dd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[273] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0bc1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[274] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0715,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[275] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0269,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[276] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5a69,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[277] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4895,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[278] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_43e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[279] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f3d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[280] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a71,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[281] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0bcd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[282] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0701,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 55,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[283] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0255,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 56,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[284] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5a55,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 57,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[285] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c25,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 58,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[286] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2779,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 58,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[287] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_224d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 58,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[288] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d81,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 58,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[289] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0585,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 58,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[290] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00d9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 58,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[291] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_58d9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 59,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[292] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_542d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 60,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[293] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4259,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[294] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dad,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[295] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38e1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[296] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3435,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[297] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[298] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00c5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[299] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_58c5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[300] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5419,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[301] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[302] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_213d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[303] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c71,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[304] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1745,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[305] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5c75,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[306] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5749,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[307] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_529d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[308] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4dd1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[309] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c1d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[310] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3751,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[311] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[312] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2df9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[313] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4fe9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[314] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b3d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 61,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[315] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4671,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 62,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[316] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4145,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 63,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[317] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1315,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 64,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[318] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e69,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 64,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[319] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_09bd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 64,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[320] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_04f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 64,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[321] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_49a1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 64,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[322] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_44f5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 64,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[323] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3fc9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 65,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[324] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b1d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 66,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[325] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2949,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[326] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_249d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[327] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[328] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b25,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[329] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_49ad,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[330] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_44e1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[331] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4035,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[332] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b09,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[333] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0cd9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[334] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_082d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[335] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0361,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[336] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5b61,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[337] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4365,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[338] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3eb9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[339] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_398d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[340] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34c1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[341] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_230d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[342] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e41,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[343] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1995,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[344] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_14e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[345] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2559,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[346] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b95,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[347] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1825,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[348] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13f9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 67,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[349] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e8d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 68,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[350] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0a41,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 69,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[351] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38dd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 70,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[352] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3391,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 70,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[353] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ea5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 70,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[354] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a79,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 70,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[355] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_127d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 70,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[356] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0d31,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 70,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[357] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_08c5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 71,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[358] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0399,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 72,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[359] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4eb1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[360] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4a45,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[361] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4519,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[362] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_402d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[363] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1269,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[364] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0d3d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[365] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_08f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[366] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0385,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[367] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3201,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[368] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dd5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[369] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[370] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23bd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[371] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0ba1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[372] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0775,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[373] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0209,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[374] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5a09,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[375] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48f5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[376] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4389,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[377] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f5d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[378] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a11,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[379] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0bad,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[380] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0761,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 73,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[381] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0235,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 74,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[382] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5a35,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 75,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[383] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c45,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 76,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[384] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2719,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 76,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[385] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_222d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 76,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[386] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1de1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 76,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[387] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05e5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 76,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[388] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00b9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 76,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[389] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_58b9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 77,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[390] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_544d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 78,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[391] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4239,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[392] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dcd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[393] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3881,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[394] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3455,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[395] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0591,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[396] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[397] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_58a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[398] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5479,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[399] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2589,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[400] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_215d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[401] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c11,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[402] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1725,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[403] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5c15,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[404] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5729,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[405] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_52fd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[406] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4db1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[407] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c7d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[408] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3731,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[409] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32c5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[410] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d99,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[411] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f89,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[412] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b5d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 79,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[413] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4611,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 80,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[414] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4125,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 81,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[415] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1375,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 82,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[416] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e09,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 82,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[417] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_09dd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 82,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[418] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0491,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 82,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[419] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_49c1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 82,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[420] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4495,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 82,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[421] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3fa9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 83,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[422] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b7d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 84,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[423] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2929,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[424] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24fd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[425] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[426] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b45,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[427] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_49cd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[428] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4481,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[429] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4055,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[430] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b69,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[431] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0cb9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[432] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_084d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[433] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0301,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[434] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5b01,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[435] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4305,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[436] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ed9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[437] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39ed,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[438] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34a1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[439] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[440] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e21,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[441] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19f5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[442] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1489,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[443] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2539,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[444] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bf5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[445] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b6af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[446] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[447] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[448] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ccaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[449] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[450] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d567,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[451] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18eab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[452] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19367,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[453] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a10b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 85,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[454] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9c3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 86,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[455] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b23f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 86,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[456] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b70b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[457] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c49f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[458] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bfc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[459] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d5c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[460] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1da9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[461] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b063,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[462] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ab97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[463] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c197,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[464] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c663,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[465] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d3f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[466] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[467] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1886f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[468] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18d3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[469] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9acf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[470] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_95f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[471] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1abf3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[472] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b0cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[473] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_be53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[474] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b987,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[475] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cf87,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[476] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d453,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[477] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[478] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a56b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[479] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bb6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[480] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c027,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[481] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cdcb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[482] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c8ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[483] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18223,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[484] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_186ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[485] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9483,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 87,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[486] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8fb7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 88,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[487] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a5b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 88,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[488] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aa83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[489] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b817,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[490] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b35b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[491] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c95b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[492] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ce17,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[493] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a3fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[494] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9f2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[495] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b52f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[496] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b9fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[497] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c78f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[498] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c2b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[499] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d8b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[500] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_180b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[501] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8e47,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[502] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_898b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[503] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19f8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[504] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a447,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[505] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[506] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ad1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[507] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c31f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[508] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[509] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9137,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[510] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[511] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a27b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[512] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a737,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[513] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[514] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b00f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[515] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c60f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[516] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cadb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[517] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[518] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_863f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[519] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19c3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[520] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a10b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[521] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[522] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a9c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[523] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bfc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[524] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c49f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[525] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2563,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[526] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2baf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[527] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[528] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_160b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 89,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[529] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_399f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[530] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[531] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0fcf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[532] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3353,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[533] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b68f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[534] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b94f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[535] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[536] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fecf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[537] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[538] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[539] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f773,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[540] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[541] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[542] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eab3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[543] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[544] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f033,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[545] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cc8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[546] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef4f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[547] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d20f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[548] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f4cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[549] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[550] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a007,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[551] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c2c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[552] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e587,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[553] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d547,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[554] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f807,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[555] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dac7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[556] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e0cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[557] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18e8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[558] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b14b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[559] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d40b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[560] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f6cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[561] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19347,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[562] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b607,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[563] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d8c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[564] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb87,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[565] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a12b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[566] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a3eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 90,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[567] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 91,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[568] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e96b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 92,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[569] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9c1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 93,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[570] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bedf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 93,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[571] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e19f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 93,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[572] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e45f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 93,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[573] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b21f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 93,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[574] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b4df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 93,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[575] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f79f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 94,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[576] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fa5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 95,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[577] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b72b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[578] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b9eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[579] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fcab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[580] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[581] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c4bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[582] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e77f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[583] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ca3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[584] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ecff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[585] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bfe3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[586] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e2a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[587] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c563,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[588] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e823,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[589] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d5e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[590] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f8a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[591] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1db63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[592] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e117,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[593] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dabf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[594] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a0a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[595] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c363,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[596] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e623,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[597] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b043,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[598] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b303,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[599] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[600] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f883,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[601] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_abb7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[602] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae77,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[603] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f137,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[604] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f3f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[605] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c1b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[606] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e477,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[607] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c737,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[608] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e9f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[609] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c643,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[610] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e903,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[611] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cbc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[612] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ee83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[613] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d3d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[614] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f697,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[615] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d957,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[616] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc17,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[617] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[618] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f1db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[619] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d49b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[620] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f75b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[621] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1884f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[622] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ab0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[623] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cdcf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[624] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f08f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[625] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18d1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[626] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1afdb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[627] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d29b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[628] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f55b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[629] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9aef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[630] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bdaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[631] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e06f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[632] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e32f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[633] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_95d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[634] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b893,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[635] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_db53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[636] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fe13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[637] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1abd3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[638] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ae93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[639] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f153,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[640] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f413,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[641] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b0ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[642] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b3af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[643] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f66f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[644] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f92f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[645] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_be73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[646] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e133,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[647] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c3f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[648] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[649] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b9a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[650] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bc67,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[651] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ff27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[652] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e1e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[653] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cfa7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[654] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f267,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[655] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d527,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[656] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f7e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[657] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d473,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[658] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f733,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[659] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d9f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[660] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fcb3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[661] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[662] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_acc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[663] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef87,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[664] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f247,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[665] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a54b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[666] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a80b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[667] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eacb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[668] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[669] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bb4b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[670] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1be0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[671] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c0cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[672] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e38b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[673] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c007,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[674] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e2c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[675] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c587,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[676] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e847,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[677] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cdeb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[678] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f0ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[679] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d36b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[680] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f62b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[681] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c8df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[682] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eb9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[683] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ce5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[684] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f11f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[685] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18203,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[686] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a4c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[687] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c783,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[688] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea43,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[689] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_186df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[690] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a99f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[691] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cc5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[692] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[693] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_94a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[694] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b763,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 96,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[695] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da23,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 97,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[696] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fce3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 98,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[697] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8f97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 99,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[698] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b257,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 99,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[699] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d517,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 99,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[700] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f7d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 99,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[701] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a597,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 99,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[702] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a857,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 99,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[703] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eb17,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 100,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[704] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1edd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 101,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[705] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aaa3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[706] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ad63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[707] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f023,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[708] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f2e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[709] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b837,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[710] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_baf7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[711] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fdb7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[712] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e077,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[713] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b37b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[714] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b63b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[715] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f8fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[716] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fbbb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[717] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c97b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[718] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ec3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[719] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cefb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[720] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f1bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[721] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ce37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[722] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f0f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[723] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d3b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[724] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f677,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[725] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a3db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[726] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a69b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[727] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e95b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[728] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ec1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[729] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9f0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[730] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[731] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e48f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[732] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e74f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[733] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b50f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[734] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b7cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[735] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fa8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[736] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd4f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[737] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b9db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[738] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bc9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[739] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff5b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[740] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e21b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[741] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c7af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[742] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ea6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[743] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cd2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[744] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_efef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[745] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c293,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[746] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e553,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[747] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c813,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[748] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ead3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[749] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d893,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[750] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[751] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c147,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[752] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e407,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[753] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18093,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[754] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a353,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[755] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c613,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[756] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[757] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8e67,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[758] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b127,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[759] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d3e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[760] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f6a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[761] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_89ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[762] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[763] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf2b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[764] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f1eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[765] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19fab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[766] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a26b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[767] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e52b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[768] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e7eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[769] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a467,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[770] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a727,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[771] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e9e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[772] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eca7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[773] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[774] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b48b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[775] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f74b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[776] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[777] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ad3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[778] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_afff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[779] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[780] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f57f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[781] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c33f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[782] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e5ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[783] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c8bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[784] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eb7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[785] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[786] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[787] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd4b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[788] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f00b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[789] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9117,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[790] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b3d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[791] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d697,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[792] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f957,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[793] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c5b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[794] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[795] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d1db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[796] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f49b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[797] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a25b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[798] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a51b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[799] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e7db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[800] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[801] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a717,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[802] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a9d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[803] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ec97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[804] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[805] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[806] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b7bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[807] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[808] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fd3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[809] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b02f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[810] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b2ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[811] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[812] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f86f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[813] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c62f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[814] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[815] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cbaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[816] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ee6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[817] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cafb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[818] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1edbb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[819] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d07b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[820] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f33b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[821] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b2b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[822] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_adeb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[823] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d0ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[824] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f36b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[825] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_861f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[826] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a8df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[827] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cb9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[828] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[829] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19c1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[830] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bedf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[831] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e19f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[832] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e45f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[833] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a12b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[834] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a3eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[835] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e6ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[836] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e96b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[837] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aebf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[838] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b17f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[839] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f43f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[840] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f6ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[841] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a9e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[842] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aca3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[843] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[844] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f223,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[845] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bfe3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[846] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e2a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[847] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c563,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[848] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e823,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[849] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c4bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[850] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e77f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[851] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ca3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[852] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ecff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[853] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2543,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[854] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[855] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[856] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_162b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[857] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[858] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[859] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0fef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[860] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3373,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[861] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b6ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[862] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b92f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[863] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[864] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_feaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[865] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b193,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[866] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[867] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f713,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[868] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[869] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c793,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[870] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ead3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[871] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[872] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f053,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[873] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ccef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[874] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[875] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d26f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[876] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f4af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[877] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[878] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a067,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[879] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c2a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[880] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e5e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[881] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d527,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[882] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f867,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[883] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_daa7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[884] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e0ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[885] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18eeb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[886] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b12b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[887] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d46b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[888] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f6ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[889] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19327,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[890] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b667,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[891] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d8a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[892] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fbe7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[893] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a14b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[894] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a38b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 102,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[895] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 103,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[896] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e90b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 104,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[897] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9c7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 105,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[898] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bebf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 105,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[899] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e1ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 105,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[900] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e43f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 105,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[901] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b27f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 105,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[902] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b4bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 105,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[903] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f7ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 106,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[904] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fa3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 107,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[905] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b74b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[906] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b98b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[907] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fccb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[908] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[909] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c4df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[910] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e71f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[911] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ca5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[912] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ec9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[913] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bf83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[914] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e2c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[915] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c503,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[916] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e843,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[917] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d583,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[918] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f8c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[919] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1db03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[920] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e177,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[921] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dadf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[922] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a0c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[923] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c303,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[924] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e643,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[925] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b023,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[926] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b363,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[927] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[928] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f8e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[929] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_abd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[930] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae17,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[931] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f157,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[932] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f397,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[933] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c1d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[934] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e417,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[935] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c757,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[936] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e997,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[937] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c623,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[938] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e963,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[939] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cba3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[940] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eee3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[941] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d3b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[942] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f6f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[943] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d937,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[944] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc77,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[945] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[946] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f1bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[947] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d4fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[948] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f73b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[949] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1882f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[950] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ab6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[951] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cdaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[952] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f0ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[953] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18d7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[954] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1afbb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[955] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d2fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[956] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f53b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[957] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9a8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[958] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bdcf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[959] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e00f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[960] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e34f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[961] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_95b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[962] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b8f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[963] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_db33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[964] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fe73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[965] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1abb3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[966] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aef3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[967] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f133,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[968] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f473,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[969] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b08f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[970] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b3cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[971] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f60f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[972] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f94f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[973] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_be13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[974] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e153,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[975] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c393,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[976] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[977] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b9c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[978] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bc07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[979] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ff47,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[980] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e187,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[981] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cfc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[982] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f207,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[983] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d547,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[984] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f787,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[985] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d413,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[986] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f753,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[987] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d993,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[988] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fcd3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[989] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa67,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[990] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aca7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[991] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_efe7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[992] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f227,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[993] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a52b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[994] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a86b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[995] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eaab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[996] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_edeb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[997] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bb2b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[998] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1be6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[999] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c0ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1000] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e3eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1001] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c067,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1002] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e2a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1003] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c5e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1004] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e827,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1005] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cd8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1006] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f0cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1007] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d30b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1008] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f64b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1009] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c8bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1010] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ebff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1011] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ce3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1012] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f17f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1013] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18263,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1014] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a4a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1015] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1016] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea23,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1017] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_186bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1018] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a9ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1019] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cc3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1020] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1021] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_94c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1022] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b703,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 108,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1023] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da43,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 109,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1024] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 110,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1025] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8ff7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 111,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1026] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b237,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 111,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1027] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d577,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 111,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1028] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f7b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 111,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1029] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a5f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 111,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1030] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a837,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 111,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1031] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eb77,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 112,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1032] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1edb7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 113,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1033] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aac3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1034] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ad03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1035] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f043,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1036] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f283,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1037] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b857,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1038] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1039] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fdd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1040] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e017,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1041] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b31b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1042] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b65b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1043] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f89b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1044] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fbdb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1045] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c91b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1046] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ec5b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1047] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ce9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1048] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f1db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1049] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ce57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1050] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f097,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1051] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d3d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1052] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f617,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1053] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a3bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1054] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a6fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1055] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e93b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1056] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ec7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1057] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9f6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1058] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1059] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e4ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1060] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e72f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1061] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b56f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1062] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b7af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1063] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1faef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1064] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1065] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b9bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1066] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bcfb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1067] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1068] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e27b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1069] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c7cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1070] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ea0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1071] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cd4f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1072] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1073] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c2f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1074] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e533,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1075] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c873,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1076] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eab3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1077] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d8f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1078] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1079] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c127,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1080] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e467,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1081] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_180f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1082] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a333,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1083] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c673,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1084] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1085] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8e07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1086] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b147,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1087] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d387,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1088] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f6c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1089] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_89cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1090] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1091] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cf4b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1092] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f18b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1093] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19fcb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1094] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a20b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1095] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e54b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1096] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e78b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1097] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a407,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1098] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a747,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1099] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e987,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1100] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ecc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1101] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1102] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1103] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f72b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1104] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1105] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ad5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1106] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1107] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1108] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f51f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1109] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c35f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1110] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e59f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1111] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c8df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1112] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eb1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1113] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1114] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eaeb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1115] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd2b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1116] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f06b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1117] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9177,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1118] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b3b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1119] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d6f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1120] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f937,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1121] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1122] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1123] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d1bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1124] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f4fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1125] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a23b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1126] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a57b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1127] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e7bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1128] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eafb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1129] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a777,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1130] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a9b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1131] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ecf7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1132] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1133] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b49b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1134] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b7db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1135] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1136] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fd5b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1137] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b04f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1138] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b28f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1139] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1140] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f80f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1141] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c64f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1142] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e88f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1143] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cbcf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1144] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ee0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1145] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ca9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1146] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eddb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1147] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d01b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1148] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f35b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1149] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b4b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1150] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ad8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1151] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d0cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1152] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f30b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1153] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_867f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1154] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a8bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1155] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cbff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1156] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1157] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19c7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1158] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bebf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1159] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e1ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1160] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e43f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1161] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a14b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1162] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a38b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1163] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e6cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1164] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e90b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1165] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aedf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1166] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b11f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1167] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f45f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1168] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f69f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1169] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a983,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1170] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_acc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1171] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1172] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f243,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1173] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bf83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1174] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e2c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1175] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c503,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1176] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e843,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1177] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c4df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1178] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e71f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1179] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ca5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1180] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ec9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1181] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2523,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1182] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1183] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1184] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_164b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1185] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1186] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1187] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0f8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1188] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3313,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1189] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_257b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1190] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24467,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1191] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23fbb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1192] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1193] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21e7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1194] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20b2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1195] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20663,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1196] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_219b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1197] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24213,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 114,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1198] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ec3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 115,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1199] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a17,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 115,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1200] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23d27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1201] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_208db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1202] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25277,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1203] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24d8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1204] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_203ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1205] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2517b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1206] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23e2b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1207] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2397f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1208] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24c8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1209] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21823,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1210] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20513,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1211] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20027,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1212] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21377,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1213] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23bd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1214] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22887,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1215] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_223db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1216] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1217] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2029f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1218] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24c3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1219] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2474f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1220] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25a9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1221] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1222] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_237ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1223] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23323,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1224] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24673,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1225] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_211e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1226] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25b83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1227] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_256d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1228] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1229] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2359b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 116,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1230] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2224b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 117,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1231] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21d9f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 117,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1232] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_230af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1233] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2590f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1234] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_245ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1235] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24133,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1236] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25443,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1237] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_244e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1238] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_231d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1239] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ce7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1240] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24037,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1241] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20bab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1242] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25547,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1243] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2509b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1244] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_206ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1245] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1246] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21c0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1247] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21743,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1248] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1249] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1250] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23fa3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1251] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23af7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1252] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24e07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1253] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2322f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1254] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21f1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1255] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21a53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1256] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22d63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1257] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1258] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_242b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1259] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23dc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1260] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25117,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1261] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1262] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_218c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1263] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21417,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1264] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22727,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1265] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24f87,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1266] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23c77,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1267] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2378b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1268] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24adb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1269] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_257b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1270] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bb7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1271] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f2b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1272] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1613,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1273] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3987,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1274] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1275] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0fd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1276] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_334b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1277] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25797,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1278] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_285eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1279] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_310eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1280] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39beb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1281] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24447,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1282] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cf47,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1283] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35a47,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1284] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3889b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1285] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23f9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1286] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ca9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1287] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3559b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1288] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_383ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1289] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1290] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2813f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1291] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30c3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1292] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3973f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1293] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21e5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1294] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a95f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1295] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3345f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1296] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bf5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1297] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20b0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1298] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2960f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1299] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3210f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1300] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ac0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1301] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20643,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1302] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29143,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1303] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31c43,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1304] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a743,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1305] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21993,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1306] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a493,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1307] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32f93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1308] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ba93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1309] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24233,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1310] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cd33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 118,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1311] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35833,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 119,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1312] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38607,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 120,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1313] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ee3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 121,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1314] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b9e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 121,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1315] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_344e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 121,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1316] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cfe3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 121,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1317] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 121,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1318] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b537,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 121,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1319] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34037,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 122,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1320] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cb37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 123,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1321] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23d07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1322] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c807,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1323] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35307,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1324] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3815b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1325] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_208fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1326] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_293fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1327] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31efb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1328] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a9fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1329] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25257,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1330] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_280ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1331] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30bab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1332] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_396ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1333] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24dab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1334] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d8ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1335] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_306ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1336] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_391ff,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1337] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_203cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1338] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28ecf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1339] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_319cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1340] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a4cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1341] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2515b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1342] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dc5b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1343] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30aaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1344] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_395af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1345] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23e0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1346] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c90b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1347] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3540b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1348] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3825f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1349] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2395f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1350] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c45f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1351] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34f5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1352] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3da5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1353] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24caf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1354] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d7af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1355] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_305e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1356] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_390e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1357] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21803,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1358] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a303,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1359] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32e03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1360] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b903,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1361] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20533,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1362] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29033,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1363] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31b33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1364] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a633,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1365] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20007,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1366] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28b07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1367] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31607,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1368] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a107,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1369] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21357,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1370] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29e57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1371] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32957,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1372] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b457,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1373] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23bf7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1374] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c6f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1375] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_351f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1376] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dcf7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1377] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_228a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1378] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b3a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1379] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33ea7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1380] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c9a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1381] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_223fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1382] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2aefb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1383] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_339fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1384] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c4fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1385] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1386] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c1cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1387] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34ccb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1388] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d7cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1389] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_202bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1390] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28dbf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1391] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_318bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1392] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a3bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1393] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24c1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1394] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d71b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1395] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3056f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1396] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3906f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1397] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2476f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1398] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d26f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1399] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_300a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1400] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38ba3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1401] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25abf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1402] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_288f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1403] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_313f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1404] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39ef3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1405] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1406] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d61f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1407] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30453,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1408] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38f53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1409] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_237cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1410] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c2cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1411] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34dcf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1412] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d8cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1413] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23303,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1414] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2be03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1415] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34903,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1416] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d403,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1417] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24653,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1418] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d153,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1419] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35c53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1420] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38aa7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1421] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_211c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1422] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29cc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1423] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_327c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1424] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b2c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1425] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25ba3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1426] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_289f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1427] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_314f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1428] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39ff7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1429] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_256f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1430] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_284cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1431] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30fcb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1432] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39acb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1433] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1434] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2981b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1435] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3231b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1436] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ae1b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1437] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_235bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1438] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c0bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 124,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1439] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34bbb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 125,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1440] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d6bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 126,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1441] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2226b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 127,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1442] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ad6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 127,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1443] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3386b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 127,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1444] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c36b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 127,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1445] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21dbf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 127,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1446] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a8bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 127,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1447] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_333bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 128,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1448] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bebf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 129,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1449] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2308f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1450] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bb8f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1451] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3468f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1452] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d18f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1453] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2592f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1454] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28763,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1455] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31263,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1456] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39d63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1457] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_245df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1458] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d0df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1459] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35bdf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1460] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38a13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1461] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24113,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1462] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cc13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1463] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35713,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1464] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38567,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1465] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25463,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1466] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_282b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1467] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30db7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1468] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_398b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1469] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_244c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1470] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cfc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1471] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35ac3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1472] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38917,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1473] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_231f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1474] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bcf3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1475] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_347f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1476] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d2f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1477] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22cc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1478] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b7c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1479] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_342c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1480] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cdc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1481] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24017,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1482] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cb17,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1483] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35617,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1484] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3846b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1485] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20b8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1486] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2968b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1487] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3218b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1488] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ac8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1489] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25567,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1490] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_283bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1491] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30ebb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1492] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_399bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1493] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_250bb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1494] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dbbb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1495] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3098f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1496] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3948f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1497] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_206df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1498] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_291df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1499] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31cdf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1500] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a7df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1501] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1502] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ba7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1503] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3457f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1504] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d07f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1505] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21c2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1506] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a72f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1507] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3322f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1508] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bd2f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1509] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21763,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1510] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a263,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1511] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32d63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1512] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b863,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1513] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ab3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1514] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b5b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1515] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_340b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1516] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cbb3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1517] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1518] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28127,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1519] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30c27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1520] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39727,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1521] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23f83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1522] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ca83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1523] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35583,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1524] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_383d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1525] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ad7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1526] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c5d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1527] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_350d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1528] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dbd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1529] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24e27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1530] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d927,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1531] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3077b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1532] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3927b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1533] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2320f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1534] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bd0f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1535] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3480f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1536] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d30f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1537] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21f3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1538] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2aa3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1539] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3353f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1540] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c03f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1541] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21a73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1542] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a573,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1543] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33073,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1544] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bb73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1545] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22d43,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1546] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b843,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1547] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34343,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1548] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ce43,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1549] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1550] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28437,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1551] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30f37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1552] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39a37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1553] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24293,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1554] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cd93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1555] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35893,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1556] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_386e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1557] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23de7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1558] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c8e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1559] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_353e7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1560] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3823b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1561] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25137,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1562] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dc37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1563] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30a0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1564] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3950b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1565] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1566] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b733,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1567] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34233,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1568] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cd33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1569] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_218e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1570] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a3e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1571] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ee3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1572] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b9e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1573] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21437,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1574] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29f37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1575] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32a37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1576] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b537,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1577] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22707,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1578] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b207,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1579] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33d07,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1580] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c807,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1581] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24fa7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1582] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2daa7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1583] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_308fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1584] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_393fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1585] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23c57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1586] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c757,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1587] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35257,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1588] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_380ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1589] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_237ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1590] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c2ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1591] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34dab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1592] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d8ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1593] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24afb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1594] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d5fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1595] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_303cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1596] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38ecf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1597] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1598] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1599] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1600] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1633,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1601] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1602] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1603] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0ff7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1604] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_336b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1605] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_257f7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1606] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2858b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1607] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3108b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1608] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39b8b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1609] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24427,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1610] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cf27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1611] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35a27,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1612] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_388fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1613] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ffb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1614] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cafb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1615] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_355fb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1616] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3838f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1617] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2528b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1618] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2815f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1619] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30c5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1620] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3975f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1621] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21e3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1622] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a93f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1623] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3343f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1624] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bf3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1625] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20b6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1626] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2966f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1627] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3216f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1628] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ac6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1629] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20623,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1630] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29123,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1631] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31c23,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1632] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a723,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1633] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_219f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1634] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a4f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1635] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ff3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1636] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3baf3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1637] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24253,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1638] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cd53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 130,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1639] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35853,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 131,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1640] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38667,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 132,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1641] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22e83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 133,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1642] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b983,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 133,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1643] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34483,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 133,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1644] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cf83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 133,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1645] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 133,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1646] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b557,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 133,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1647] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34057,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 134,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1648] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cb57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 135,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1649] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23d67,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1650] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c867,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1651] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35367,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1652] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3813b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1653] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2089b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1654] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2939b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1655] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31e9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1656] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a99b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1657] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25237,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1658] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_280cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1659] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30bcb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1660] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_396cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1661] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24dcb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1662] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d8cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1663] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3069f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1664] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3919f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1665] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_203af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1666] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28eaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1667] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_319af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1668] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a4af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1669] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2513b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1670] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dc3b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1671] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30acf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1672] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_395cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1673] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23e6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1674] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c96b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1675] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3546b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1676] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3823f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1677] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2393f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1678] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c43f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1679] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34f3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1680] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3da3f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1681] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24ccf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1682] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d7cf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1683] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30583,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1684] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39083,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1685] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21863,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1686] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a363,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1687] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32e63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1688] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b963,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1689] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20553,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1690] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29053,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1691] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31b53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1692] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a653,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1693] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20067,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1694] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28b67,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1695] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31667,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1696] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a167,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1697] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21337,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1698] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29e37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1699] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32937,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1700] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b437,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1701] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23b97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1702] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c697,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1703] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35197,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1704] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dc97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1705] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_228c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1706] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b3c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1707] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33ec7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1708] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c9c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1709] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2239b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1710] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ae9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1711] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3399b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1712] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c49b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1713] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1714] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c1ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1715] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34cab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1716] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d7ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1717] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_202df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1718] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28ddf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1719] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_318df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1720] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a3df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1721] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24c7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1722] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d77b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1723] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3050f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1724] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3900f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1725] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2470f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1726] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d20f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1727] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_300c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1728] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38bc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1729] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25adf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1730] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28893,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1731] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31393,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1732] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39e93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1733] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b7f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1734] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d67f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1735] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30433,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1736] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38f33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1737] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_237af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1738] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c2af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1739] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34daf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1740] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d8af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1741] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23363,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1742] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2be63,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1743] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34963,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1744] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d463,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1745] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24633,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1746] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d133,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1747] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35c33,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1748] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38ac7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1749] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_211a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1750] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29ca7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1751] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_327a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1752] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b2a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1753] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25bc3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1754] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28997,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1755] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31497,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1756] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39f97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1757] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25697,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1758] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_284ab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1759] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30fab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1760] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39aab,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1761] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1762] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2987b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1763] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3237b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1764] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ae7b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1765] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_235db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1766] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c0db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 136,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1767] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34bdb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 137,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1768] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d6db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 138,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1769] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2220b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 139,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1770] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ad0b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 139,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1771] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3380b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 139,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1772] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c30b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 139,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1773] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21ddf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 139,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1774] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a8df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 139,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1775] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_333df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 140,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1776] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bedf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 141,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1777] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_230ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1778] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bbef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1779] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_346ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1780] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d1ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1781] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2594f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1782] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28703,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1783] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31203,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1784] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39d03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1785] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_245bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1786] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d0bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1787] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35bbf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1788] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38a73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1789] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24173,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1790] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cc73,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1791] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35773,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1792] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38507,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1793] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25403,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1794] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_282d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1795] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30dd7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1796] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_398d7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1797] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_244a3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1798] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cfa3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1799] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35aa3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1800] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38977,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1801] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23193,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1802] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bc93,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1803] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34793,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1804] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d293,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1805] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ca7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1806] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b7a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1807] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_342a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1808] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cda7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1809] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24077,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1810] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cb77,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1811] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35677,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1812] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3840b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1813] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20beb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1814] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_296eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1815] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_321eb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1816] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3aceb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1817] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25507,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1818] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_283db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1819] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30edb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1820] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_399db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1821] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_250db,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1822] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dbdb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1823] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_309ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1824] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_394ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1825] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_206bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1826] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_291bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1827] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31cbf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1828] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a7bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1829] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1830] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ba1f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1831] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3451f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1832] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d01f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1833] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21c4f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1834] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a74f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1835] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3324f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1836] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bd4f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1837] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21703,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1838] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a203,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1839] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32d03,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1840] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b803,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1841] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ad3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1842] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b5d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1843] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_340d3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1844] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cbd3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1845] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1846] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28147,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1847] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30c47,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1848] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39747,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1849] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23fe3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1850] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cae3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1851] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_355e3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1852] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_383b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1853] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ab7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1854] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c5b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1855] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_350b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1856] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dbb7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1857] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24e47,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1858] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d947,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1859] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3071b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1860] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3921b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1861] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2326f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1862] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bd6f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1863] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3486f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1864] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d36f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1865] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21f5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1866] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2aa5f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1867] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3355f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1868] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c05f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1869] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21a13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1870] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a513,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1871] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33013,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1872] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bb13,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1873] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22d23,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1874] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b823,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1875] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34323,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1876] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ce23,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1877] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25583,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1878] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28457,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1879] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30f57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1880] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39a57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1881] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_242f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1882] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cdf3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1883] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_358f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1884] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38687,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1885] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23d87,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1886] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c887,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1887] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35387,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1888] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3825b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1889] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25157,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1890] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dc57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1891] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30a6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1892] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3956b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1893] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1894] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b753,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1895] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34253,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1896] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cd53,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1897] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21883,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1898] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a383,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1899] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32e83,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1900] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b983,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1901] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21457,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1902] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29f57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1903] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32a57,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1904] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b557,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1905] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22767,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1906] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b267,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1907] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33d67,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1908] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c867,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1909] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24fc7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1910] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dac7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1911] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3089b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1912] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3939b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1913] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23c37,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1914] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c737,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1915] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35237,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1916] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_380cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1917] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_237cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1918] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c2cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1919] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34dcb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1920] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d8cb,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1921] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24a9b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1922] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d59b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1923] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_303af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1924] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38eaf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1925] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_253b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1926] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bf7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1927] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4f6b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1928] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1653,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1929] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39c7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1930] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_48af,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1931] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0f97,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1932] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_330b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1933] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_374e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 142,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1934] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11ee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 143,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1935] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_423a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 143,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1936] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0cd6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 144,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1937] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_310a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 144,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1938] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_469e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 144,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1939] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ce6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 144,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1940] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0692,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 144,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1941] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c7e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 144,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1942] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_55c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 145,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1943] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b2a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 145,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1944] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15c6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 146,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1945] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_163a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 146,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1946] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2f8e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 146,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1947] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2516,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 146,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1948] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b76,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 146,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1949] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 146,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1950] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_264a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 147,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1951] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3fd2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 147,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1952] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4532,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 148,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1953] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4996,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 148,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1954] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2036,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 148,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1955] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_399e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 148,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1956] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ffe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 148,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1957] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34fe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 148,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1958] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a32,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 149,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1959] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_376e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 149,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1960] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12d6e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 149,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1961] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2436e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 150,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1962] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31dba,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 151,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1963] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11ce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 152,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1964] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_107ce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 152,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1965] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23dce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 152,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1966] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_353ce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 152,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1967] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_421a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 152,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1968] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11d56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 152,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1969] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23356,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 153,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1970] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32956,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 154,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1971] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0cf6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1972] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_122f6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1973] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_258f6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1974] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_313c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1975] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_312a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1976] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1272a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1977] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d2a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1978] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31466,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1979] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_46be,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1980] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1018a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1981] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2378a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1982] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32d8a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1983] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5cc6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1984] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11712,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1985] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d12,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1986] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32312,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1987] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_06b2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1988] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13cb2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1989] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252b2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1990] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_348b2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1991] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c5e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1992] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1325e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 155,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1993] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2285e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 156,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1994] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35e5e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 157,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1995] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_55e2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 158,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1996] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_14be2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 158,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1997] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2023e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 158,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1998] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3383e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 158,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[1999] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b0a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 158,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2000] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1410a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 158,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2001] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21846,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 159,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2002] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30e46,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 160,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2003] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2004] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10be6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2005] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_221e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2006] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_357e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2007] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_161a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2008] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10c1a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2009] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2221a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2010] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3581a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2011] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2fae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2012] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_145ae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2013] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21cfa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2014] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_332fa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2015] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2536,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2016] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15b36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2017] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21202,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2018] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30802,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2019] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2020] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_105a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2021] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ba2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2022] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_351a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2023] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10c6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2024] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_106c6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 161,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2025] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23cc6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 162,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2026] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_352c6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 163,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2027] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_266a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 164,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2028] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15c6a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 164,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2029] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_216a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 164,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2030] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30ca6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 164,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2031] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ff2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 164,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2032] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_155f2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 164,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2033] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24bf2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 165,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2034] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_302ce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 166,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2035] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4512,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2036] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11c6e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2037] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2326e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2038] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3286e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2039] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_49b6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2040] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10082,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2041] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23682,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2042] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32c82,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2043] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2016,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2044] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15616,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2045] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21162,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2046] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30762,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2047] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39be,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2048] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12fbe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2049] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_245be,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2050] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31c8a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2051] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5fde,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2052] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1162a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2053] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20c2a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2054] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3222a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2055] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34de,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2056] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a12,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2057] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_370e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2058] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12d0e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 167,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2059] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2430e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 168,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2060] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31dda,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 169,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2061] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11ae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 170,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2062] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_107ae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 170,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2063] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23dae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 170,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2064] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_353ae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 170,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2065] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_427a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 170,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2066] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11d36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 170,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2067] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23336,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 171,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2068] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32936,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 172,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2069] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0c96,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2070] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12296,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2071] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25896,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2072] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_313a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2073] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_314a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2074] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1274a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2075] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d4a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2076] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31406,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2077] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_46de,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2078] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_101ea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2079] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_237ea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2080] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32dea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2081] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ca6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2082] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11772,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2083] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20d72,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2084] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32372,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2085] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_06d2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2086] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13cd2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2087] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252d2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2088] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_348d2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2089] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c3e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2090] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1323e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 173,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2091] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2283e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 174,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2092] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35e3e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 175,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2093] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5582,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 176,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2094] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_14b82,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 176,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2095] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2025e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 176,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2096] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3385e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 176,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2097] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b6a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 176,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2098] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1416a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 176,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2099] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21826,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 177,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2100] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30e26,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 178,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2101] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1586,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2102] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10b86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2103] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22186,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2104] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35786,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2105] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_167a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2106] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10c7a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2107] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2227a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2108] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3587a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2109] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2fce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2110] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_145ce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2111] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21c9a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2112] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3329a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2113] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2556,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2114] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15b56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2115] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21262,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2116] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30862,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2117] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2118] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_105c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2119] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23bc2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2120] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_351c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2121] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_10a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2122] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_106a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 179,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2123] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ca6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 180,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2124] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_352a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 181,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2125] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_260a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 182,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2126] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15c0a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 182,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2127] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_216c6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 182,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2128] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30cc6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 182,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2129] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f92,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 182,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2130] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15592,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 182,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2131] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b92,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 183,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2132] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_302ae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 184,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2133] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4572,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2134] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_11c0e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2135] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2320e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2136] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3280e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2137] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_49d6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2138] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_100e2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2139] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236e2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2140] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ce2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2141] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2076,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2142] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_15676,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2143] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21102,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2144] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30702,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2145] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39de,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2146] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12fde,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2147] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_245de,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2148] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31cea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2149] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5fbe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2150] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1164a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2151] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20c4a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2152] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3224a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2153] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34be,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2154] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a72,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2155] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_09ea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 185,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2156] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2912,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 186,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2157] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03b2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 186,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2158] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5f7e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 187,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2159] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 187,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2160] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 187,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2161] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a6e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 187,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2162] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_593a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 187,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2163] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4dce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 187,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2164] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e02,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 188,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2165] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4796,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 188,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2166] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_246e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 189,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2167] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_478a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 189,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2168] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_08fe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 189,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2169] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e52,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 189,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2170] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3e2a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 189,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2171] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e46,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 189,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2172] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02ba,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 190,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2173] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_580e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 190,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2174] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2175] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5802,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2176] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d76,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2177] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_52ca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2178] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2179] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34f6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2180] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a3a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2181] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_09ca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2182] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0216,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 191,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2183] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f62,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 192,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2184] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 193,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2185] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2932,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 194,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2186] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_227e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 194,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2187] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f4a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 194,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2188] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b96,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 194,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2189] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0392,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 194,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2190] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cde,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 194,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2191] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_192a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 195,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2192] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1276,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 196,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2193] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5f5e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2194] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5baa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2195] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_54f6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2196] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_51c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2197] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0386,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2198] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2199] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_191e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2200] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_126a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2201] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2202] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c3a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2203] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3906,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2204] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3252,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2205] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a4e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2206] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_169a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2207] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_13e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2208] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4be6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2209] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_591a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2210] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5266,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2211] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2eb2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2212] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bfe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2213] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4dee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2214] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_463a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 197,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2215] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4306,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 198,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2216] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5c52,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 199,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2217] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e22,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 200,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2218] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0b6e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 200,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2219] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07ba,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 200,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2220] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0086,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 200,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2221] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_47b6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 200,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2222] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4082,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 200,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2223] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5dce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 201,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2224] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_561a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 202,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2225] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_244e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2226] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_209a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2227] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3de6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2228] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3632,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2229] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_47aa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2230] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_40f6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2231] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5dc2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2232] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_560e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2233] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_08de,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2234] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_052a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2235] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e76,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2236] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b42,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2237] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e72,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2238] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5abe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2239] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_578a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2240] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_50d6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2241] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3e0a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2242] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2243] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_37a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2244] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30ee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2245] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e66,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2246] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ab2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 203,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2247] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_57fe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 204,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2248] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_50ca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 205,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2249] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_029a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 206,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2250] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fe6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 206,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2251] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1832,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 206,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2252] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_157e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 206,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2253] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_582e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 206,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2254] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_557a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 206,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2255] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e46,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 207,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2256] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a92,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 208,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2257] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38c6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2258] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3512,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2259] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e5e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2260] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0aaa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2261] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5822,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2262] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_556e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2263] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_51ba,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2264] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2265] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2266] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2267] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_12ee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2268] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4aee,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2269] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_52ea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2270] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2f36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2271] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2802,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2272] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_254e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2273] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3282,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2274] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0fce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2275] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_081a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2276] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0566,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2277] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34d6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2278] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a1a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2279] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_09aa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2280] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0276,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 209,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2281] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f02,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 210,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2282] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bce,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 211,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2283] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2952,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 212,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2284] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_221e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 212,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2285] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3f2a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 212,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2286] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bf6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 212,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2287] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03f2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 212,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2288] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cbe,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 212,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2289] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_194a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 213,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2290] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1216,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 214,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2291] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5f3e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2292] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5bca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2293] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5496,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2294] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_51a2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2295] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2296] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cb2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2297] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_197e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2298] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_120a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2299] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_238e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2300] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c5a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2301] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3966,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2302] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3232,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2303] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a2e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2304] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_16fa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2305] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1386,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2306] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4b86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2307] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_597a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2308] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5206,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2309] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ed2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2310] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b9e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2311] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4d8e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2312] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_465a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 215,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2313] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4366,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 216,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2314] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5c32,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 217,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2315] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e42,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 218,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2316] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0b0e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 218,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2317] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07da,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 218,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2318] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00e6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 218,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2319] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_47d6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 218,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2320] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_40e2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 218,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2321] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5dae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 219,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2322] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_567a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 220,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2323] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_242e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2324] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20fa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2325] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2326] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3652,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2327] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_47ca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2328] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4096,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2329] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5da2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2330] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_566e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2331] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_08be,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2332] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_054a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2333] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e16,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2334] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b22,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2335] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e12,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2336] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ade,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2337] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_57ea,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2338] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_50b6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2339] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3e6a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2340] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2341] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_37c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2342] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_308e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2343] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e06,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2344] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ad2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 221,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2345] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_579e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 222,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2346] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_50aa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 223,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2347] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02fa,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 224,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2348] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f86,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 224,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2349] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1852,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 224,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2350] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_151e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 224,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2351] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_584e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 224,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2352] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_551a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 224,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2353] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2e26,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 225,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2354] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2af2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 226,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2355] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38a6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2356] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3572,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2357] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0e3e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2358] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0aca,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2359] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5842,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2360] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_550e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2361] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_51da,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2362] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ae6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2363] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d36,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2364] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19c2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2365] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_128e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2366] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_4a8e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2367] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_528a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2368] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2f56,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2369] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2862,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2370] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_252e,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2371] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32e2,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2372] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0fae,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2373] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_087a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2374] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0506,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2375] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34b6,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2376] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a7a,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2377] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a73c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2378] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a040,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2379] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d640,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2380] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dd3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2381] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cba0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2382] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c4f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2383] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19f38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2384] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_182f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2385] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b098,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 227,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2386] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8dac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 228,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2387] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a3ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 228,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2388] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a698,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2389] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d50c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2390] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2391] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c450,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2392] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cb0c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2393] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2394] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2395] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d004,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2396] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d7f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2397] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c264,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2398] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dea8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2399] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_199fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2400] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19ca8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2401] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2402] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8460,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2403] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ba60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2404] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a15c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2405] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_afc0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2406] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a814,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2407] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1de14,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2408] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c5c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2409] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2410] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8970,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2411] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bf70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2412] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a22c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2413] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d0d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2414] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ade4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2415] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c3e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2416] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c6d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2417] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9988,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 229,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2418] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_92dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 230,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2419] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_188dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 230,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2420] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18f88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2421] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2422] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b740,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2423] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ad40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2424] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d03c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2425] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_86e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2426] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8334,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2427] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b934,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2428] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bce0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2429] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2430] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a7d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2431] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ddd8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2432] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c094,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2433] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_904c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2434] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c84c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2435] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18290,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2436] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1864c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2437] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2438] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b104,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2439] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a704,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2440] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aaf0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2441] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_80a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2442] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9de8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2443] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b3e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2444] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b6a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2445] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a548,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2446] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a19c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2447] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d79c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2448] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1db48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2449] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9a98,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2450] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_97ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2451] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18dac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2452] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b098,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2453] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bf0c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2454] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b850,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2455] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ae50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2456] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d50c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2457] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2458] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2459] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ea0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2460] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0798,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 231,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2461] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_280c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2462] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5964,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2463] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2464] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2465] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a71c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2466] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a8dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2467] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed9c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2468] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2469] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a060,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2470] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a520,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2471] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2472] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eba0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2473] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d660,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2474] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2475] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dce0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2476] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e1a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2477] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dd1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2478] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fedc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2479] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c39c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2480] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e55c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2481] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cb80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2482] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b194,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2483] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d354,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2484] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f414,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2485] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c4d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2486] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e994,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2487] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cb54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2488] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f158,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2489] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19f18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2490] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a0d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2491] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c598,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2492] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e758,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2493] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_182d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2494] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a794,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2495] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c954,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2496] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea14,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2497] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b0b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2498] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b278,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 232,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2499] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f738,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 233,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2500] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f8f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 234,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2501] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8d8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 235,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2502] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 235,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2503] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f00c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 235,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2504] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 235,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2505] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a38c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 235,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2506] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a54c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 235,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2507] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e60c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 236,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2508] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ebcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 237,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2509] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a6b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2510] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a878,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2511] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ed38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2512] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eef8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2513] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d52c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2514] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f6ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2515] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dbac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2516] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fd6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2517] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2518] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f330,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2519] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d4f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2520] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f9b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2521] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c470,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2522] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e930,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2523] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1caf0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2524] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f084,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2525] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cb2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2526] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b130,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2527] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d2f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2528] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f7b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2529] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2530] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a290,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2531] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e450,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2532] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e910,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2533] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba24,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2534] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bfe4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2535] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e0a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2536] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e264,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2537] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d024,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2538] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f5e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2539] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d6a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2540] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f864,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2541] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d7d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2542] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f890,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2543] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1da50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2544] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2545] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c244,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2546] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e704,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2547] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c8c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2548] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2549] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_de88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2550] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e048,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2551] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c508,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2552] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2553] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_199dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2554] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ba9c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2555] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dc5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2556] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e11c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2557] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19c88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2558] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1be48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2559] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c308,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2560] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e4c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2561] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2562] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2563] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f1fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2564] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2565] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8440,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2566] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a900,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2567] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cac0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2568] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2569] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ba40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2570] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bf00,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2571] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e0c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2572] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e580,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2573] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a17c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2574] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a23c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2575] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e7fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2576] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2577] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_afe0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2578] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f0a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2579] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d260,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2580] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f720,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2581] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a834,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2582] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_adf4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2583] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eeb4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2584] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f074,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2585] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1de34,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2586] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e3f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2587] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c4b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2588] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e674,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2589] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c5e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2590] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e6a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2591] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c860,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2592] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ed20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2593] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c0c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2594] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2595] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f28c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2596] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f44c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2597] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8950,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2598] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2599] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cfd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2600] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f090,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2601] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bf50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2602] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a010,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2603] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e5d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2604] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e690,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2605] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a20c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2606] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a7cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2607] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e88c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2608] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2609] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d0f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2610] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2611] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d770,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2612] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f830,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2613] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_adc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2614] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2615] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d044,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2616] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f504,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2617] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c3c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2618] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e484,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2619] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c644,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2620] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eb04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2621] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c6f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2622] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ebb0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2623] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2624] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f304,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2625] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_99a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2626] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bb68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 238,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2627] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dc28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 239,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2628] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e1e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 240,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2629] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_92fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 241,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2630] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b7bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 241,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2631] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d97c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 241,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2632] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 241,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2633] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_188fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 241,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2634] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1adbc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 241,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2635] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cf7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 242,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2636] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f03c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 243,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2637] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18fa8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2638] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b168,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2639] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f228,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2640] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f7e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2641] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2642] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bfdc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2643] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e09c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2644] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e25c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2645] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b760,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2646] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b820,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2647] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fde0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2648] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fea0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2649] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ad60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2650] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ae20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2651] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d3e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2652] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f4a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2653] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d01c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2654] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f5dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2655] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d69c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2656] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f85c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2657] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_86c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2658] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ab80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2659] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cd40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2660] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee00,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2661] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8314,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2662] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a4d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2663] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c994,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2664] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eb54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2665] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b914,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2666] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bad4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2667] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2668] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e154,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2669] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bcc0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2670] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a180,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2671] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e340,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2672] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e400,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2673] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aab4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2674] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2675] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d134,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2676] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2677] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a7f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2678] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a8b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2679] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ea78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2680] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2681] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ddf8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2682] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1feb8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2683] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c078,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2684] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e538,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2685] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c0b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2686] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e274,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2687] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c734,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2688] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2689] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_906c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2690] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b52c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2691] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d6ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2692] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fbac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2693] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c86c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2694] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2695] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d330,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2696] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f4f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2697] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_182b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2698] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a470,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2699] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c930,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2700] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eaf0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2701] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1866c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2702] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ab2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2703] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ccec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2704] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f1ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2705] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2706] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b990,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2707] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fb50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2708] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2709] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b124,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2710] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b2e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2711] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f7a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2712] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f964,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2713] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a724,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2714] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a8e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2715] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eda4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2716] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2717] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aad0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2718] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1af90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2719] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d150,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2720] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f210,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2721] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8084,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2722] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a244,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2723] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c704,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2724] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e8c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2725] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9dc8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2726] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_be88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2727] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c048,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2728] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e508,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2729] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b3c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2730] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b488,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2731] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f648,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2732] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2733] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b684,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2734] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b844,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2735] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2736] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fec4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2737] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a568,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2738] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a628,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2739] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ebe8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2740] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eca8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2741] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2742] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a37c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2743] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e43c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2744] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e9fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2745] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d7bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2746] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f97c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2747] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1da3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2748] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fffc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2749] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1db68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2750] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fc28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2751] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c1e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2752] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e2a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2753] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9ab8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2754] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bc78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2755] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c138,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2756] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e2f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2757] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_978c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2758] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b94c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2759] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da0c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2760] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ffcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2761] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18d8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2762] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1af4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2763] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f00c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2764] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f5cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2765] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b0b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2766] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b278,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2767] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f738,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2768] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f8f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2769] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bf2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2770] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a0ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2771] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e5ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2772] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e76c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2773] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b870,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2774] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bd30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2775] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fef0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2776] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e3b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2777] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ae70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2778] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f330,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2779] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d4f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2780] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f9b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2781] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d52c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2782] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f6ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2783] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dbac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2784] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2785] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2786] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2787] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2788] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2789] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_282c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2790] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5944,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2791] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2792] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2793] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a77c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2794] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a8bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2795] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_edfc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2796] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2797] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a000,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2798] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a540,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2799] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e680,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2800] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ebc0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2801] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d600,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2802] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2803] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dc80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2804] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e1c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2805] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dd7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2806] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1febc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2807] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c3fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2808] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e53c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2809] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cbe0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2810] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2811] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d334,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2812] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f474,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2813] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c4b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2814] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e9f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2815] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cb34,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2816] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f138,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2817] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19f78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2818] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a0b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2819] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c5f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2820] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e738,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2821] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_182b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2822] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a7f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2823] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c934,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2824] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2825] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b0d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2826] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b218,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 244,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2827] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f758,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 245,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2828] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f898,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 246,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2829] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8dec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 247,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2830] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 247,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2831] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f06c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 247,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2832] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 247,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2833] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a3ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 247,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2834] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a52c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 247,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2835] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e66c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 248,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2836] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ebac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 249,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2837] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a6d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2838] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a818,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2839] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ed58,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2840] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ee98,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2841] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d54c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2842] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f68c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2843] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dbcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2844] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fd0c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2845] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ae10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2846] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f350,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2847] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d490,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2848] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f9d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2849] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c410,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2850] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e950,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2851] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ca90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2852] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f0e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2853] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cb4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2854] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b150,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2855] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d290,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2856] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f7d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2857] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2858] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a2f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2859] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e430,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2860] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e970,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2861] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2862] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bf84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2863] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e0c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2864] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e204,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2865] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d044,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2866] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f584,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2867] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d6c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2868] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f804,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2869] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d7b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2870] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f8f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2871] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1da30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2872] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2873] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c224,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2874] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e764,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2875] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c8a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2876] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ede4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2877] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dee8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2878] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e028,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2879] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c568,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2880] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e6a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2881] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_199bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2882] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bafc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2883] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dc3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2884] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e17c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2885] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_19ce8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2886] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1be28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2887] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c368,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2888] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e4a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2889] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8b1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2890] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2891] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f19c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2892] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2893] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8420,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2894] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a960,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2895] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_caa0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2896] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_efe0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2897] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ba20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2898] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bf60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2899] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e0a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2900] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e5e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2901] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a11c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2902] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a25c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2903] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e79c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2904] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2905] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_af80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2906] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f0c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2907] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d200,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2908] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f740,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2909] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a854,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2910] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ad94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2911] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eed4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2912] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f014,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2913] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1de54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2914] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e394,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2915] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c4d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2916] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e614,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2917] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c580,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2918] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e6c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2919] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c800,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2920] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ed40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2921] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8c6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2922] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b1ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2923] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f2ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2924] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f42c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2925] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8930,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2926] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aa70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2927] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cfb0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2928] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f0f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2929] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bf30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2930] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a070,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2931] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e5b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2932] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e6f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2933] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a26c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2934] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a7ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2935] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e8ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2936] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2937] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d090,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2938] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f5d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2939] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d710,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2940] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f850,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2941] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ada4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2942] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aee4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2943] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d024,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2944] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f564,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2945] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c3a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2946] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e4e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2947] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c624,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2948] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1eb64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2949] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c690,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2950] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ebd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2951] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cd10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2952] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f364,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2953] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_99c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2954] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bb08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 250,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2955] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_dc48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 251,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2956] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e188,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 252,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2957] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_929c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 253,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2958] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b7dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 253,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2959] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d91c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 253,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2960] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fa5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 253,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2961] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1889c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 253,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2962] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1addc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 253,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2963] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cf1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 254,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2964] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f05c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 255,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2965] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18fc8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2966] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b108,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2967] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f248,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2968] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f788,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2969] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ba7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2970] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bfbc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2971] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e0fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2972] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e23c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2973] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b700,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2974] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b840,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2975] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fd80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2976] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fec0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2977] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ad00,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2978] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ae40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2979] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d380,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2980] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f4c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2981] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d07c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2982] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f5bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2983] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d6fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2984] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f83c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2985] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_86a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2986] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_abe0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2987] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_cd20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2988] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ee60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2989] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_8374,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2990] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a4b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2991] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c9f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2992] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eb34,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2993] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b974,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2994] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bab4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2995] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fff4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2996] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e134,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2997] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1bca0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2998] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a1e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[2999] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e320,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3000] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e460,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3001] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_aad4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3002] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ac14,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3003] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d154,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3004] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f294,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3005] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a798,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3006] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a8d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3007] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ea18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3008] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ef58,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3009] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dd98,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3010] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fed8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3011] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c018,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3012] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e558,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3013] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c0d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3014] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e214,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3015] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c754,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3016] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e894,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3017] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_900c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3018] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b54c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3019] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d68c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3020] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fbcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3021] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c80c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3022] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ed4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3023] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_d350,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3024] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f490,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3025] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_182d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3026] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a410,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3027] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c950,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3028] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ea90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3029] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1860c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3030] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ab4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3031] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1cc8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3032] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f1cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3033] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b4b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3034] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b9f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3035] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fb30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3036] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fc70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3037] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b144,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3038] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b284,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3039] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f7c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3040] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_f904,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3041] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a744,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3042] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1a884,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3043] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1edc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3044] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ef04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3045] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aab0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3046] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1aff0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3047] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d130,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3048] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f270,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3049] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_80e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3050] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a224,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3051] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c764,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3052] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e8a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3053] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9da8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3054] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bee8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3055] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c028,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3056] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e568,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3057] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b3a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3058] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b4e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3059] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f628,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3060] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fb68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3061] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b6e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3062] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b824,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3063] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3064] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fea4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3065] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a508,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3066] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a648,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3067] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_eb88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3068] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ecc8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3069] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a1dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3070] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a31c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3071] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e45c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3072] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e99c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3073] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d7dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3074] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f91c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3075] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1da5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3076] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ff9c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3077] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1db08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3078] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fc48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3079] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1c188,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3080] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e2c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3081] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_9ad8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3082] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bc18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3083] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_c158,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3084] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e298,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3085] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_97ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3086] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b92c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3087] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_da6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3088] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_ffac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3089] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_18dec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3090] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1af2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3091] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f06c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3092] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f5ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3093] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b0d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3094] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1b218,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3095] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f758,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3096] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f898,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3097] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bf4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3098] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_a08c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3099] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e5cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3100] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e70c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3101] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_b810,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3102] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_bd50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3103] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_fe90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3104] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_e3d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3105] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1ae10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3106] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f350,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3107] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d490,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3108] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f9d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3109] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1d54c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3110] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1f68c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3111] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1dbcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3112] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1fd0c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3113] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3114] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3115] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ee0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3116] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3117] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_284c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3118] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5924,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3119] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3120] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2280,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 8,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3121] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24604,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3122] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3123] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22e08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3124] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24378,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3125] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20fcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3126] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21a9c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3127] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_217d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3128] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20800,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3129] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_253a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 256,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3130] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23f70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 257,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3131] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23ba4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 257,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3132] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3133] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21968,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3134] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_243c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3135] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25c38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3136] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2125c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3137] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_240c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3138] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f98,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3139] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_228cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3140] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3141] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20990,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3142] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_214a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3143] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21194,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3144] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_202c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3145] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3146] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23934,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3147] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23268,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3148] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22758,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3149] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2132c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3150] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3151] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_256fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3152] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b2c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3153] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f14,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3154] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23a24,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3155] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23718,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3156] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22848,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3157] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_214dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3158] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25eb8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3159] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25bec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3160] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21110,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3161] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_238b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 258,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3162] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20440,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 259,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3163] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_200b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 259,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3164] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_235e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3165] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3166] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_228d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3167] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22508,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3168] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25678,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3169] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_229d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3170] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_234e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3171] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_231dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3172] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2220c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3173] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24dac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3174] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2597c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3175] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3176] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_246e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3177] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23374,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3178] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21e04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3179] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21b78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3180] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20fa8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3181] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_257c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3182] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22298,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3183] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23fcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3184] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2503c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3185] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2239c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3186] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20eac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3187] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20be0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3188] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23cd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3189] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24470,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3190] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25300,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3191] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3192] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_240a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3193] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23da0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3194] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20970,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3195] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_205a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3196] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23694,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3197] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25e34,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3198] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22dc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3199] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22638,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3200] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25b68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3201] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3202] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3203] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5e98,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3204] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3205] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2834,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3206] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_595c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3207] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3208] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 9,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3209] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24664,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3210] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29418,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3211] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30118,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3212] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38a18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3213] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3214] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2deb4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3215] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34bb4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3216] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39968,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3217] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22e68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3218] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2db68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3219] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34468,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3220] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3921c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3221] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24318,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3222] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_290cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3223] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31dcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3224] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_386cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3225] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20fac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3226] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b8ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3227] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_325ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3228] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3aeac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3229] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21afc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3230] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_287fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3231] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_330fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3232] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bdfc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3233] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_217b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3234] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_280b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3235] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30db0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3236] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b6b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3237] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20860,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3238] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b560,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3239] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33e60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3240] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ab60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3241] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_253c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3242] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dcc0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 260,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3243] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_349c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 261,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3244] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_397f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 262,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3245] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23f10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 263,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3246] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a810,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 263,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3247] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35510,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 263,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3248] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3de10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 263,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3249] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23bc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 263,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3250] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a4c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 263,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3251] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_351c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 264,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3252] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dac4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 265,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3253] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22cf4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3254] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d9f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3255] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_342f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3256] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_390a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3257] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21908,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3258] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28208,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3259] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30f08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3260] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b808,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3261] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_243a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3262] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29158,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3263] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31a58,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3264] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38758,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3265] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25c58,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3266] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c958,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3267] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3170c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3268] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3800c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3269] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2123c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3270] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29f3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3271] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3083c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3272] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b53c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3273] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_240a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3274] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cda8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3275] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31b5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3276] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3845c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3277] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22ff8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3278] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d8f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3279] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_345f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3280] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_393ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3281] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_228ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3282] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d5ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3283] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35eac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3284] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cbac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3285] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3286] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c65c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3287] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31410,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3288] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38110,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3289] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_209f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3290] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b2f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3291] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33ff0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3292] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a8f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3293] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_214c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3294] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_281c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3295] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30ac0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3296] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b7c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3297] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_211f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3298] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29af4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3299] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_307f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3300] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b0f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3301] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_202a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3302] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28fa4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3303] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_338a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3304] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a5a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3305] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3306] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d704,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3307] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34004,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3308] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cd04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3309] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23954,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3310] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a254,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3311] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32f54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3312] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d854,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3313] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23208,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3314] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bf08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3315] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32808,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3316] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d508,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3317] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22738,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3318] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d038,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3319] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35d38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3320] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c638,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3321] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2134c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3322] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29c4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3323] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3094c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3324] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b24c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3325] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25de8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3326] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c6e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3327] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3149c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3328] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3819c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3329] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2569c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3330] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c39c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3331] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31150,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3332] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39a50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3333] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3334] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29900,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3335] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30200,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3336] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38f00,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3337] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3338] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d874,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3339] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34574,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3340] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39328,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3341] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23a44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3342] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a744,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3343] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35044,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3344] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dd44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3345] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23778,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3346] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a078,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3347] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32d78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3348] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d678,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3349] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22828,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3350] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d528,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3351] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35e28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3352] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cb28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3353] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_214bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3354] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_281bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3355] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30abc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3356] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b7bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3357] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25ed8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3358] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cbd8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3359] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3198c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3360] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3828c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3361] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25b8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3362] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c48c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3363] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31240,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3364] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39f40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3365] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21170,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3366] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29a70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3367] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30770,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3368] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b070,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3369] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_238d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3370] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a5d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 266,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3371] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ed0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 267,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3372] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dbd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 268,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3373] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20420,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 269,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3374] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b120,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 269,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3375] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33a20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 269,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3376] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a720,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 269,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3377] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_200d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 269,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3378] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28dd4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 269,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3379] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_336d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 270,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3380] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a3d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 271,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3381] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23584,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3382] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2be84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3383] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32b84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3384] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d484,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3385] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3386] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c664,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3387] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31418,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3388] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38118,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3389] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_228b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3390] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d5b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3391] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35eb4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3392] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cbb4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3393] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22568,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3394] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ae68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3395] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35b68,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3396] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c468,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3397] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25618,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3398] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c318,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3399] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_310cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3400] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39dcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3401] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_229b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3402] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d2b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3403] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35fb8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3404] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c8b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3405] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23488,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3406] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a188,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3407] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32a88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3408] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d788,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3409] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_231bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3410] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2babc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3411] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_327bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3412] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d0bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3413] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2226c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3414] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2af6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3415] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3586c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3416] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c56c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3417] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24dcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3418] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29b80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3419] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30480,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3420] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b180,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3421] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2591c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3422] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c21c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3423] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_313d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3424] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39cd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3425] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3426] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ded0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3427] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34bd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3428] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39984,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3429] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24680,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3430] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_294b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3431] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_301b4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3432] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38ab4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3433] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23314,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3434] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bc14,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3435] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32914,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3436] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d214,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3437] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21e64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3438] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28b64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3439] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33464,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3440] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a164,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3441] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21b18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3442] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28418,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3443] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33118,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3444] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ba18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3445] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20fc8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3446] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b8c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3447] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_325c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3448] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3aec8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3449] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_257a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3450] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c0a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3451] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34da8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3452] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39b5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3453] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_222f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3454] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2aff8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3455] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_358f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3456] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c5f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3457] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23fac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3458] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a8ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3459] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_355ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3460] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3deac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3461] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2505c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3462] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dd5c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3463] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3465c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3464] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39410,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3465] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_223fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3466] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2acfc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3467] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_359fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3468] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c2fc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3469] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20ecc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3470] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bbcc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3471] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_324cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3472] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d1cc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3473] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20b80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3474] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b480,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3475] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32180,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3476] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3aa80,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3477] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23cb0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3478] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a9b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3479] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_352b0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3480] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dfb0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3481] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24410,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3482] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_295c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3483] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31ec4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3484] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38bc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3485] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25360,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3486] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dc60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3487] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34960,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3488] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39714,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3489] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c14,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3490] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d914,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3491] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34214,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3492] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_393c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3493] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_240c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3494] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cdc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3495] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31bf8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3496] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_384f8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3497] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23dc0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3498] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a6c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3499] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_353c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3500] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dcc0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3501] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20910,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3502] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b210,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3503] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33f10,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3504] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a810,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3505] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_205c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3506] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28ec4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3507] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33bc4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3508] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a4c4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3509] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3510] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a3f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3511] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32cf4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3512] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d9f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3513] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25e54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3514] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cb54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3515] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31908,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3516] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38208,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3517] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22da4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3518] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d6a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3519] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_343a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3520] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39158,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3521] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22658,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3522] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d358,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3523] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35c58,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3524] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c958,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3525] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25b08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3526] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c408,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3527] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3123c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3528] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39f3c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3529] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3530] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3531] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ef8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3532] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07c0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3533] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2854,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3534] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_593c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3535] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e04,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3536] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2298,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 10,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3537] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24644,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3538] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29438,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3539] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30138,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3540] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38a38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3541] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25594,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3542] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2de94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3543] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34b94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3544] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39948,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3545] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22e48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3546] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2db48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3547] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34448,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3548] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3923c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3549] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24338,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3550] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_290ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3551] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31dec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3552] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_386ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3553] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20f8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3554] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b88c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3555] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3258c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3556] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ae8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3557] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21adc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3558] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_287dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3559] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_330dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3560] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3bddc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3561] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21790,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3562] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28090,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3563] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30d90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3564] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b690,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3565] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20840,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3566] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b540,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3567] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33e40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3568] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ab40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3569] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_253e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3570] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dce0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 272,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3571] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_349e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 273,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3572] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_397d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 274,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3573] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23f30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 275,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3574] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a830,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 275,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3575] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35530,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 275,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3576] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3de30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 275,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3577] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23be4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 275,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3578] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a4e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 275,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3579] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_351e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 276,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3580] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dae4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 277,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3581] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22cd4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3582] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d9d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3583] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_342d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3584] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39088,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3585] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21928,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3586] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28228,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3587] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30f28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3588] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b828,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3589] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24384,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3590] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29178,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3591] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31a78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3592] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38778,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3593] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25c78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3594] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c978,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3595] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3172c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3596] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3802c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3597] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2121c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3598] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29f1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3599] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3081c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3600] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b51c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3601] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24088,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3602] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cd88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3603] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31b7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3604] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3847c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3605] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22fd8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3606] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d8d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3607] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_345d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3608] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3938c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3609] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2288c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3610] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d58c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3611] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35e8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3612] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cb8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3613] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3614] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c67c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3615] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31430,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3616] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38130,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3617] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_209d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3618] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b2d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3619] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33fd0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3620] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a8d0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3621] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_214e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3622] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_281e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3623] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30ae0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3624] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b7e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3625] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_211d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3626] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29ad4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3627] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_307d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3628] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b0d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3629] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20284,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3630] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28f84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3631] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33884,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3632] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a584,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3633] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22a24,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3634] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d724,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3635] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34024,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3636] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cd24,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3637] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23974,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3638] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a274,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3639] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32f74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3640] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d874,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3641] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23228,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3642] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bf28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3643] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32828,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3644] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d528,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3645] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22718,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3646] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d018,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3647] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35d18,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3648] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c618,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3649] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2136c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3650] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29c6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3651] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3096c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3652] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b26c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3653] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25dc8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3654] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c6c8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3655] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_314bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3656] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_381bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3657] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_256bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3658] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c3bc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3659] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31170,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3660] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39a70,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3661] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24b6c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3662] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29920,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3663] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30220,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3664] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38f20,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3665] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22f54,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3666] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d854,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3667] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34554,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3668] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39308,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3669] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23a64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3670] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a764,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3671] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35064,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3672] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dd64,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3673] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23758,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3674] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a058,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3675] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32d58,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3676] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d658,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3677] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22808,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3678] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d508,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3679] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35e08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3680] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cb08,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3681] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2149c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3682] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2819c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3683] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30a9c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3684] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b79c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3685] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25ef8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3686] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cbf8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3687] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_319ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3688] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_382ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3689] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25bac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3690] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c4ac,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3691] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31260,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3692] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39f60,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3693] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21150,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3694] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29a50,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3695] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30750,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3696] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b050,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3697] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_238f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3698] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a5f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 278,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3699] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ef0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 279,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3700] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dbf0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 280,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3701] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20400,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 281,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3702] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b100,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 281,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3703] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33a00,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 281,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3704] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a700,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 281,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3705] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_200f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 281,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3706] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28df4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 281,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3707] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_336f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 282,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3708] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a3f4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 283,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3709] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_235a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3710] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bea4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3711] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32ba4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3712] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d4a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3713] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25d44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3714] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c644,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3715] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31438,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3716] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38138,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3717] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22894,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3718] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d594,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3719] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35e94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3720] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3cb94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3721] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22548,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3722] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ae48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3723] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35b48,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3724] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c448,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3725] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25638,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3726] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c338,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3727] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_310ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3728] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39dec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3729] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22998,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3730] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d298,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3731] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35f98,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3732] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c898,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3733] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_234a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3734] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a1a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3735] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32aa8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3736] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d7a8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3737] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2319c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3738] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2ba9c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3739] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3279c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3740] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d09c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3741] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2224c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3742] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2af4c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3743] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3584c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3744] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c54c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3745] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24dec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3746] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29ba0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3747] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_304a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3748] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3b1a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3749] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2593c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3750] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c23c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3751] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_313f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3752] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39cf0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3753] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_255f0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3754] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2def0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3755] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34bf0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3756] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_399a4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3757] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_246a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3758] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_29494,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3759] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_30194,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3760] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38a94,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3761] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23334,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3762] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bc34,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3763] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32934,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3764] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d234,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3765] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21e44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3766] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28b44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3767] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33444,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3768] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a144,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3769] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_21b38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3770] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28438,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3771] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33138,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3772] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3ba38,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3773] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20fe8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3774] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b8e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3775] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_325e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3776] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3aee8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3777] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25788,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3778] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c088,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3779] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34d88,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3780] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39b7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3781] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_222d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3782] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2afd8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3783] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_358d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3784] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c5d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3785] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23f8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3786] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a88c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3787] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3558c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3788] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3de8c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3789] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2507c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3790] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dd7c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3791] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3467c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3792] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39430,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 0,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3793] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_223dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3794] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2acdc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3795] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_359dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3796] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c2dc,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3797] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20eec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3798] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2bbec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3799] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_324ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3800] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d1ec,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3801] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20ba0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3802] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b4a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3803] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_321a0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3804] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3aaa0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3805] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23c90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3806] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a990,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3807] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35290,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3808] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3df90,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3809] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_24430,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3810] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_295e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3811] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31ee4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3812] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38be4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3813] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25340,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3814] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2dc40,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3815] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34940,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3816] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39734,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3817] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22c34,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3818] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d934,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3819] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34234,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3820] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_393e8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3821] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_240e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3822] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cde4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3823] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31bd8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3824] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_384d8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3825] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_23de0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3826] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a6e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3827] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_353e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3828] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3dce0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3829] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_20930,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3830] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2b230,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3831] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33f30,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3832] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a830,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3833] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_205e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[3834] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_28ee4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[51] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0013,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 6,\n+\t[3835] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_33be4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[52] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_001c,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 6,\n+\t[3836] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a4e4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[53] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_017b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 6,\n+\t[3837] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_236d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[54] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0164,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3838] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2a3d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[55] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00c3,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3839] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_32cd4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[56] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00cc,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3840] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3d9d4,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[57] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01a5,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3841] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25e74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[58] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0196,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3842] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2cb74,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[59] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_010d,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3843] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_31928,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[60] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00fe,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3844] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_38228,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[61] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0084,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3845] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22d84,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[62] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0046,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3846] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d684,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[63] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01ec,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3847] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_34384,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[64] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01ae,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 6,\n-\t.flow_sig_id = 7,\n+\t[3848] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39178,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n-\t\tBNXT_ULP_HDR_BIT_O_TCP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[65] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d3,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 7,\n+\t[3849] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22678,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[66] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00ac,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 7,\n+\t[3850] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2d378,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[67] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_000b,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 7,\n+\t[3851] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_35c78,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[68] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0004,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 7,\n+\t[3852] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3c978,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[69] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0163,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 7,\n+\t[3853] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_25b28,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[70] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_017c,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3854] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2c428,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[71] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00db,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3855] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3121c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[72] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d4,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3856] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_39f1c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[73] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01bd,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3857] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3488,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[74] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_018e,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3858] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_3a44,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[75] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0115,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3859] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_5ed8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[76] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00e6,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3860] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07e0,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[77] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_009c,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3861] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_2874,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[78] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005e,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3862] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_591c,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[79] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01f4,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3863] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_1e24,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n-\t[80] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_01b6,\n-\t.class_tid = 1,\n-\t.hdr_sig_id = 7,\n-\t.flow_sig_id = 8,\n+\t[3864] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_22b8,\n+\t.class_tid = 2,\n+\t.hdr_sig_id = 11,\n+\t.flow_sig_id = 284,\n+\t.flow_pattern_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n \t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_UDP |\n-\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\nindex 324c288564..4a1faacfbe 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  8 14:57:13 2020 */\n+/* date: Thu Dec 17 19:43:07 2020 */\n \n #ifndef ULP_TEMPLATE_DB_H_\n #define ULP_TEMPLATE_DB_H_\n@@ -12,43 +12,43 @@\n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n #define BNXT_ULP_GEN_TBL_MAX_SZ 6\n-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 512\n-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 81\n-#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049\n-#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919\n-#define BNXT_ULP_CLASS_HID_SHFTR 25\n-#define BNXT_ULP_CLASS_HID_SHFTL 23\n-#define BNXT_ULP_CLASS_HID_MASK 511\n+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 3865\n+#define BNXT_ULP_CLASS_HID_LOW_PRIME 5939\n+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7669\n+#define BNXT_ULP_CLASS_HID_SHFTR 31\n+#define BNXT_ULP_CLASS_HID_SHFTL 31\n+#define BNXT_ULP_CLASS_HID_MASK 262143\n #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048\n-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 30\n+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86\n #define BNXT_ULP_ACT_HID_LOW_PRIME 7919\n-#define BNXT_ULP_ACT_HID_HIGH_PRIME 6701\n-#define BNXT_ULP_ACT_HID_SHFTR 24\n-#define BNXT_ULP_ACT_HID_SHFTL 23\n+#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793\n+#define BNXT_ULP_ACT_HID_SHFTR 27\n+#define BNXT_ULP_ACT_HID_SHFTL 26\n #define BNXT_ULP_ACT_HID_MASK 2047\n #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8\n #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1\n #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7\n #define BNXT_ULP_HDR_SIG_ID_SHIFT 4\n-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033\n-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7\n-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41\n-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 257\n-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 11\n-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 367\n-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 14\n+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5593\n+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8\n+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 63\n+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 412\n+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 17\n+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 503\n+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 16\n #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7\n #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38\n #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192\n #define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10\n #define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341\n #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10\n-#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 3\n-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 11\n+#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7\n+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35\n #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2\n #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1\n-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 132\n-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 13\n+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512\n+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 26\n #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2\n #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4\n #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0\n@@ -202,7 +202,9 @@ enum bnxt_ulp_cond_opc {\n \tBNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7,\n \tBNXT_ULP_COND_OPC_RF_IS_SET = 8,\n \tBNXT_ULP_COND_OPC_RF_NOT_SET = 9,\n-\tBNXT_ULP_COND_OPC_LAST = 10\n+\tBNXT_ULP_COND_OPC_FLOW_PAT_MATCH = 10,\n+\tBNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11,\n+\tBNXT_ULP_COND_OPC_LAST = 12\n };\n \n enum bnxt_ulp_critical_resource {\n@@ -231,9 +233,9 @@ enum bnxt_ulp_direction {\n };\n \n enum bnxt_ulp_fdb_opc {\n-\tBNXT_ULP_FDB_OPC_PUSH = 0,\n-\tBNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE = 1,\n-\tBNXT_ULP_FDB_OPC_PUSH_REGFILE = 2,\n+\tBNXT_ULP_FDB_OPC_PUSH_FID = 0,\n+\tBNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,\n+\tBNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE = 2,\n \tBNXT_ULP_FDB_OPC_NOP = 3,\n \tBNXT_ULP_FDB_OPC_LAST = 4\n };\n@@ -252,7 +254,9 @@ enum bnxt_ulp_field_cond_src {\n \tBNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,\n \tBNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,\n \tBNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,\n-\tBNXT_ULP_FIELD_COND_SRC_LAST = 6\n+\tBNXT_ULP_FIELD_COND_SRC_FLOW_PAT_MATCH = 6,\n+\tBNXT_ULP_FIELD_COND_SRC_ACT_PAT_MATCH = 7,\n+\tBNXT_ULP_FIELD_COND_SRC_LAST = 8\n };\n \n enum bnxt_ulp_field_opc {\n@@ -266,19 +270,20 @@ enum bnxt_ulp_field_opc {\n \n enum bnxt_ulp_field_src {\n \tBNXT_ULP_FIELD_SRC_ZERO = 0,\n-\tBNXT_ULP_FIELD_SRC_CONST = 1,\n-\tBNXT_ULP_FIELD_SRC_CF = 2,\n-\tBNXT_ULP_FIELD_SRC_RF = 3,\n-\tBNXT_ULP_FIELD_SRC_ACT_PROP = 4,\n-\tBNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5,\n-\tBNXT_ULP_FIELD_SRC_GLB_RF = 6,\n-\tBNXT_ULP_FIELD_SRC_HF = 7,\n-\tBNXT_ULP_FIELD_SRC_HDR_BIT = 8,\n-\tBNXT_ULP_FIELD_SRC_ACT_BIT = 9,\n-\tBNXT_ULP_FIELD_SRC_FIELD_BIT = 10,\n-\tBNXT_ULP_FIELD_SRC_SKIP = 11,\n-\tBNXT_ULP_FIELD_SRC_REJECT = 12,\n-\tBNXT_ULP_FIELD_SRC_LAST = 13\n+\tBNXT_ULP_FIELD_SRC_ONES = 1,\n+\tBNXT_ULP_FIELD_SRC_CONST = 2,\n+\tBNXT_ULP_FIELD_SRC_CF = 3,\n+\tBNXT_ULP_FIELD_SRC_RF = 4,\n+\tBNXT_ULP_FIELD_SRC_ACT_PROP = 5,\n+\tBNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 6,\n+\tBNXT_ULP_FIELD_SRC_GLB_RF = 7,\n+\tBNXT_ULP_FIELD_SRC_HF = 8,\n+\tBNXT_ULP_FIELD_SRC_HDR_BIT = 9,\n+\tBNXT_ULP_FIELD_SRC_ACT_BIT = 10,\n+\tBNXT_ULP_FIELD_SRC_FIELD_BIT = 11,\n+\tBNXT_ULP_FIELD_SRC_SKIP = 12,\n+\tBNXT_ULP_FIELD_SRC_REJECT = 13,\n+\tBNXT_ULP_FIELD_SRC_LAST = 14\n };\n \n enum bnxt_ulp_generic_tbl_opc {\n@@ -429,7 +434,7 @@ enum bnxt_ulp_resource_func {\n \tBNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,\n \tBNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,\n \tBNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,\n-\tBNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88\n+\tBNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88\n };\n \n enum bnxt_ulp_resource_sub_type {\n@@ -973,126 +978,3965 @@ enum ulp_sr_sym {\n };\n \n enum bnxt_ulp_class_hid {\n-\tBNXT_ULP_CLASS_HID_005c = 0x005c,\n-\tBNXT_ULP_CLASS_HID_0003 = 0x0003,\n-\tBNXT_ULP_CLASS_HID_0132 = 0x0132,\n-\tBNXT_ULP_CLASS_HID_00e1 = 0x00e1,\n-\tBNXT_ULP_CLASS_HID_0044 = 0x0044,\n-\tBNXT_ULP_CLASS_HID_001b = 0x001b,\n-\tBNXT_ULP_CLASS_HID_012a = 0x012a,\n-\tBNXT_ULP_CLASS_HID_00f9 = 0x00f9,\n-\tBNXT_ULP_CLASS_HID_018d = 0x018d,\n-\tBNXT_ULP_CLASS_HID_00a7 = 0x00a7,\n-\tBNXT_ULP_CLASS_HID_006f = 0x006f,\n-\tBNXT_ULP_CLASS_HID_0181 = 0x0181,\n-\tBNXT_ULP_CLASS_HID_0195 = 0x0195,\n-\tBNXT_ULP_CLASS_HID_00bf = 0x00bf,\n-\tBNXT_ULP_CLASS_HID_0077 = 0x0077,\n-\tBNXT_ULP_CLASS_HID_0199 = 0x0199,\n-\tBNXT_ULP_CLASS_HID_009a = 0x009a,\n-\tBNXT_ULP_CLASS_HID_0192 = 0x0192,\n-\tBNXT_ULP_CLASS_HID_01e2 = 0x01e2,\n-\tBNXT_ULP_CLASS_HID_00fa = 0x00fa,\n-\tBNXT_ULP_CLASS_HID_0165 = 0x0165,\n-\tBNXT_ULP_CLASS_HID_0042 = 0x0042,\n-\tBNXT_ULP_CLASS_HID_00cd = 0x00cd,\n-\tBNXT_ULP_CLASS_HID_01aa = 0x01aa,\n-\tBNXT_ULP_CLASS_HID_0178 = 0x0178,\n-\tBNXT_ULP_CLASS_HID_0070 = 0x0070,\n-\tBNXT_ULP_CLASS_HID_00f3 = 0x00f3,\n-\tBNXT_ULP_CLASS_HID_01d8 = 0x01d8,\n-\tBNXT_ULP_CLASS_HID_005b = 0x005b,\n-\tBNXT_ULP_CLASS_HID_0153 = 0x0153,\n-\tBNXT_ULP_CLASS_HID_01a3 = 0x01a3,\n-\tBNXT_ULP_CLASS_HID_00bb = 0x00bb,\n-\tBNXT_ULP_CLASS_HID_0082 = 0x0082,\n-\tBNXT_ULP_CLASS_HID_018a = 0x018a,\n-\tBNXT_ULP_CLASS_HID_01fa = 0x01fa,\n-\tBNXT_ULP_CLASS_HID_00e2 = 0x00e2,\n-\tBNXT_ULP_CLASS_HID_017d = 0x017d,\n-\tBNXT_ULP_CLASS_HID_005a = 0x005a,\n-\tBNXT_ULP_CLASS_HID_00d5 = 0x00d5,\n-\tBNXT_ULP_CLASS_HID_01b2 = 0x01b2,\n-\tBNXT_ULP_CLASS_HID_0160 = 0x0160,\n-\tBNXT_ULP_CLASS_HID_0068 = 0x0068,\n-\tBNXT_ULP_CLASS_HID_00eb = 0x00eb,\n-\tBNXT_ULP_CLASS_HID_01c0 = 0x01c0,\n-\tBNXT_ULP_CLASS_HID_0043 = 0x0043,\n-\tBNXT_ULP_CLASS_HID_014b = 0x014b,\n-\tBNXT_ULP_CLASS_HID_01bb = 0x01bb,\n-\tBNXT_ULP_CLASS_HID_00a3 = 0x00a3,\n-\tBNXT_ULP_CLASS_HID_00cb = 0x00cb,\n-\tBNXT_ULP_CLASS_HID_00b4 = 0x00b4,\n-\tBNXT_ULP_CLASS_HID_0013 = 0x0013,\n-\tBNXT_ULP_CLASS_HID_001c = 0x001c,\n-\tBNXT_ULP_CLASS_HID_017b = 0x017b,\n-\tBNXT_ULP_CLASS_HID_0164 = 0x0164,\n-\tBNXT_ULP_CLASS_HID_00c3 = 0x00c3,\n-\tBNXT_ULP_CLASS_HID_00cc = 0x00cc,\n-\tBNXT_ULP_CLASS_HID_01a5 = 0x01a5,\n-\tBNXT_ULP_CLASS_HID_0196 = 0x0196,\n-\tBNXT_ULP_CLASS_HID_010d = 0x010d,\n-\tBNXT_ULP_CLASS_HID_00fe = 0x00fe,\n-\tBNXT_ULP_CLASS_HID_0084 = 0x0084,\n-\tBNXT_ULP_CLASS_HID_0046 = 0x0046,\n-\tBNXT_ULP_CLASS_HID_01ec = 0x01ec,\n-\tBNXT_ULP_CLASS_HID_01ae = 0x01ae,\n-\tBNXT_ULP_CLASS_HID_00d3 = 0x00d3,\n-\tBNXT_ULP_CLASS_HID_00ac = 0x00ac,\n-\tBNXT_ULP_CLASS_HID_000b = 0x000b,\n-\tBNXT_ULP_CLASS_HID_0004 = 0x0004,\n-\tBNXT_ULP_CLASS_HID_0163 = 0x0163,\n-\tBNXT_ULP_CLASS_HID_017c = 0x017c,\n-\tBNXT_ULP_CLASS_HID_00db = 0x00db,\n-\tBNXT_ULP_CLASS_HID_00d4 = 0x00d4,\n-\tBNXT_ULP_CLASS_HID_01bd = 0x01bd,\n-\tBNXT_ULP_CLASS_HID_018e = 0x018e,\n-\tBNXT_ULP_CLASS_HID_0115 = 0x0115,\n+\tBNXT_ULP_CLASS_HID_26d1 = 0x26d1,\n+\tBNXT_ULP_CLASS_HID_0071 = 0x0071,\n+\tBNXT_ULP_CLASS_HID_53a5 = 0x53a5,\n+\tBNXT_ULP_CLASS_HID_1d49 = 0x1d49,\n+\tBNXT_ULP_CLASS_HID_2095 = 0x2095,\n+\tBNXT_ULP_CLASS_HID_5701 = 0x5701,\n+\tBNXT_ULP_CLASS_HID_4d79 = 0x4d79,\n+\tBNXT_ULP_CLASS_HID_170d = 0x170d,\n+\tBNXT_ULP_CLASS_HID_1a69 = 0x1a69,\n+\tBNXT_ULP_CLASS_HID_50c5 = 0x50c5,\n+\tBNXT_ULP_CLASS_HID_473d = 0x473d,\n+\tBNXT_ULP_CLASS_HID_10c1 = 0x10c1,\n+\tBNXT_ULP_CLASS_HID_142d = 0x142d,\n+\tBNXT_ULP_CLASS_HID_4a99 = 0x4a99,\n+\tBNXT_ULP_CLASS_HID_40f1 = 0x40f1,\n+\tBNXT_ULP_CLASS_HID_0a85 = 0x0a85,\n+\tBNXT_ULP_CLASS_HID_0179 = 0x0179,\n+\tBNXT_ULP_CLASS_HID_37d5 = 0x37d5,\n+\tBNXT_ULP_CLASS_HID_2e4d = 0x2e4d,\n+\tBNXT_ULP_CLASS_HID_54ad = 0x54ad,\n+\tBNXT_ULP_CLASS_HID_5809 = 0x5809,\n+\tBNXT_ULP_CLASS_HID_31a9 = 0x31a9,\n+\tBNXT_ULP_CLASS_HID_2801 = 0x2801,\n+\tBNXT_ULP_CLASS_HID_4e61 = 0x4e61,\n+\tBNXT_ULP_CLASS_HID_2561 = 0x2561,\n+\tBNXT_ULP_CLASS_HID_2bad = 0x2bad,\n+\tBNXT_ULP_CLASS_HID_26f1 = 0x26f1,\n+\tBNXT_ULP_CLASS_HID_13cf1 = 0x13cf1,\n+\tBNXT_ULP_CLASS_HID_252f1 = 0x252f1,\n+\tBNXT_ULP_CLASS_HID_30c25 = 0x30c25,\n+\tBNXT_ULP_CLASS_HID_0051 = 0x0051,\n+\tBNXT_ULP_CLASS_HID_11651 = 0x11651,\n+\tBNXT_ULP_CLASS_HID_22c51 = 0x22c51,\n+\tBNXT_ULP_CLASS_HID_34251 = 0x34251,\n+\tBNXT_ULP_CLASS_HID_5385 = 0x5385,\n+\tBNXT_ULP_CLASS_HID_10cc9 = 0x10cc9,\n+\tBNXT_ULP_CLASS_HID_222c9 = 0x222c9,\n+\tBNXT_ULP_CLASS_HID_338c9 = 0x338c9,\n+\tBNXT_ULP_CLASS_HID_1d69 = 0x1d69,\n+\tBNXT_ULP_CLASS_HID_13369 = 0x13369,\n+\tBNXT_ULP_CLASS_HID_24969 = 0x24969,\n+\tBNXT_ULP_CLASS_HID_3025d = 0x3025d,\n+\tBNXT_ULP_CLASS_HID_20b5 = 0x20b5,\n+\tBNXT_ULP_CLASS_HID_136b5 = 0x136b5,\n+\tBNXT_ULP_CLASS_HID_24cb5 = 0x24cb5,\n+\tBNXT_ULP_CLASS_HID_305f9 = 0x305f9,\n+\tBNXT_ULP_CLASS_HID_5721 = 0x5721,\n+\tBNXT_ULP_CLASS_HID_11015 = 0x11015,\n+\tBNXT_ULP_CLASS_HID_22615 = 0x22615,\n+\tBNXT_ULP_CLASS_HID_33c15 = 0x33c15,\n+\tBNXT_ULP_CLASS_HID_4d59 = 0x4d59,\n+\tBNXT_ULP_CLASS_HID_1068d = 0x1068d,\n+\tBNXT_ULP_CLASS_HID_21c8d = 0x21c8d,\n+\tBNXT_ULP_CLASS_HID_3328d = 0x3328d,\n+\tBNXT_ULP_CLASS_HID_172d = 0x172d,\n+\tBNXT_ULP_CLASS_HID_12d2d = 0x12d2d,\n+\tBNXT_ULP_CLASS_HID_2432d = 0x2432d,\n+\tBNXT_ULP_CLASS_HID_3592d = 0x3592d,\n+\tBNXT_ULP_CLASS_HID_1a49 = 0x1a49,\n+\tBNXT_ULP_CLASS_HID_13049 = 0x13049,\n+\tBNXT_ULP_CLASS_HID_24649 = 0x24649,\n+\tBNXT_ULP_CLASS_HID_35c49 = 0x35c49,\n+\tBNXT_ULP_CLASS_HID_50e5 = 0x50e5,\n+\tBNXT_ULP_CLASS_HID_10a29 = 0x10a29,\n+\tBNXT_ULP_CLASS_HID_22029 = 0x22029,\n+\tBNXT_ULP_CLASS_HID_33629 = 0x33629,\n+\tBNXT_ULP_CLASS_HID_471d = 0x471d,\n+\tBNXT_ULP_CLASS_HID_10041 = 0x10041,\n+\tBNXT_ULP_CLASS_HID_21641 = 0x21641,\n+\tBNXT_ULP_CLASS_HID_32c41 = 0x32c41,\n+\tBNXT_ULP_CLASS_HID_10e1 = 0x10e1,\n+\tBNXT_ULP_CLASS_HID_126e1 = 0x126e1,\n+\tBNXT_ULP_CLASS_HID_23ce1 = 0x23ce1,\n+\tBNXT_ULP_CLASS_HID_352e1 = 0x352e1,\n+\tBNXT_ULP_CLASS_HID_140d = 0x140d,\n+\tBNXT_ULP_CLASS_HID_12a0d = 0x12a0d,\n+\tBNXT_ULP_CLASS_HID_2400d = 0x2400d,\n+\tBNXT_ULP_CLASS_HID_3560d = 0x3560d,\n+\tBNXT_ULP_CLASS_HID_4ab9 = 0x4ab9,\n+\tBNXT_ULP_CLASS_HID_103ed = 0x103ed,\n+\tBNXT_ULP_CLASS_HID_219ed = 0x219ed,\n+\tBNXT_ULP_CLASS_HID_32fed = 0x32fed,\n+\tBNXT_ULP_CLASS_HID_40d1 = 0x40d1,\n+\tBNXT_ULP_CLASS_HID_156d1 = 0x156d1,\n+\tBNXT_ULP_CLASS_HID_21005 = 0x21005,\n+\tBNXT_ULP_CLASS_HID_32605 = 0x32605,\n+\tBNXT_ULP_CLASS_HID_0aa5 = 0x0aa5,\n+\tBNXT_ULP_CLASS_HID_120a5 = 0x120a5,\n+\tBNXT_ULP_CLASS_HID_236a5 = 0x236a5,\n+\tBNXT_ULP_CLASS_HID_34ca5 = 0x34ca5,\n+\tBNXT_ULP_CLASS_HID_0159 = 0x0159,\n+\tBNXT_ULP_CLASS_HID_11759 = 0x11759,\n+\tBNXT_ULP_CLASS_HID_22d59 = 0x22d59,\n+\tBNXT_ULP_CLASS_HID_34359 = 0x34359,\n+\tBNXT_ULP_CLASS_HID_37f5 = 0x37f5,\n+\tBNXT_ULP_CLASS_HID_14df5 = 0x14df5,\n+\tBNXT_ULP_CLASS_HID_20739 = 0x20739,\n+\tBNXT_ULP_CLASS_HID_31d39 = 0x31d39,\n+\tBNXT_ULP_CLASS_HID_2e6d = 0x2e6d,\n+\tBNXT_ULP_CLASS_HID_1446d = 0x1446d,\n+\tBNXT_ULP_CLASS_HID_25a6d = 0x25a6d,\n+\tBNXT_ULP_CLASS_HID_31351 = 0x31351,\n+\tBNXT_ULP_CLASS_HID_548d = 0x548d,\n+\tBNXT_ULP_CLASS_HID_10df1 = 0x10df1,\n+\tBNXT_ULP_CLASS_HID_223f1 = 0x223f1,\n+\tBNXT_ULP_CLASS_HID_339f1 = 0x339f1,\n+\tBNXT_ULP_CLASS_HID_5829 = 0x5829,\n+\tBNXT_ULP_CLASS_HID_1111d = 0x1111d,\n+\tBNXT_ULP_CLASS_HID_2271d = 0x2271d,\n+\tBNXT_ULP_CLASS_HID_33d1d = 0x33d1d,\n+\tBNXT_ULP_CLASS_HID_3189 = 0x3189,\n+\tBNXT_ULP_CLASS_HID_14789 = 0x14789,\n+\tBNXT_ULP_CLASS_HID_200fd = 0x200fd,\n+\tBNXT_ULP_CLASS_HID_316fd = 0x316fd,\n+\tBNXT_ULP_CLASS_HID_2821 = 0x2821,\n+\tBNXT_ULP_CLASS_HID_13e21 = 0x13e21,\n+\tBNXT_ULP_CLASS_HID_25421 = 0x25421,\n+\tBNXT_ULP_CLASS_HID_30d15 = 0x30d15,\n+\tBNXT_ULP_CLASS_HID_4e41 = 0x4e41,\n+\tBNXT_ULP_CLASS_HID_107b5 = 0x107b5,\n+\tBNXT_ULP_CLASS_HID_21db5 = 0x21db5,\n+\tBNXT_ULP_CLASS_HID_333b5 = 0x333b5,\n+\tBNXT_ULP_CLASS_HID_2541 = 0x2541,\n+\tBNXT_ULP_CLASS_HID_2b8d = 0x2b8d,\n+\tBNXT_ULP_CLASS_HID_2691 = 0x2691,\n+\tBNXT_ULP_CLASS_HID_13c91 = 0x13c91,\n+\tBNXT_ULP_CLASS_HID_25291 = 0x25291,\n+\tBNXT_ULP_CLASS_HID_30c45 = 0x30c45,\n+\tBNXT_ULP_CLASS_HID_0031 = 0x0031,\n+\tBNXT_ULP_CLASS_HID_11631 = 0x11631,\n+\tBNXT_ULP_CLASS_HID_22c31 = 0x22c31,\n+\tBNXT_ULP_CLASS_HID_34231 = 0x34231,\n+\tBNXT_ULP_CLASS_HID_53e5 = 0x53e5,\n+\tBNXT_ULP_CLASS_HID_10ca9 = 0x10ca9,\n+\tBNXT_ULP_CLASS_HID_222a9 = 0x222a9,\n+\tBNXT_ULP_CLASS_HID_338a9 = 0x338a9,\n+\tBNXT_ULP_CLASS_HID_1d09 = 0x1d09,\n+\tBNXT_ULP_CLASS_HID_13309 = 0x13309,\n+\tBNXT_ULP_CLASS_HID_24909 = 0x24909,\n+\tBNXT_ULP_CLASS_HID_3023d = 0x3023d,\n+\tBNXT_ULP_CLASS_HID_20d5 = 0x20d5,\n+\tBNXT_ULP_CLASS_HID_136d5 = 0x136d5,\n+\tBNXT_ULP_CLASS_HID_24cd5 = 0x24cd5,\n+\tBNXT_ULP_CLASS_HID_30599 = 0x30599,\n+\tBNXT_ULP_CLASS_HID_5741 = 0x5741,\n+\tBNXT_ULP_CLASS_HID_11075 = 0x11075,\n+\tBNXT_ULP_CLASS_HID_22675 = 0x22675,\n+\tBNXT_ULP_CLASS_HID_33c75 = 0x33c75,\n+\tBNXT_ULP_CLASS_HID_4d39 = 0x4d39,\n+\tBNXT_ULP_CLASS_HID_106ed = 0x106ed,\n+\tBNXT_ULP_CLASS_HID_21ced = 0x21ced,\n+\tBNXT_ULP_CLASS_HID_332ed = 0x332ed,\n+\tBNXT_ULP_CLASS_HID_174d = 0x174d,\n+\tBNXT_ULP_CLASS_HID_12d4d = 0x12d4d,\n+\tBNXT_ULP_CLASS_HID_2434d = 0x2434d,\n+\tBNXT_ULP_CLASS_HID_3594d = 0x3594d,\n+\tBNXT_ULP_CLASS_HID_1a29 = 0x1a29,\n+\tBNXT_ULP_CLASS_HID_13029 = 0x13029,\n+\tBNXT_ULP_CLASS_HID_24629 = 0x24629,\n+\tBNXT_ULP_CLASS_HID_35c29 = 0x35c29,\n+\tBNXT_ULP_CLASS_HID_5085 = 0x5085,\n+\tBNXT_ULP_CLASS_HID_10a49 = 0x10a49,\n+\tBNXT_ULP_CLASS_HID_22049 = 0x22049,\n+\tBNXT_ULP_CLASS_HID_33649 = 0x33649,\n+\tBNXT_ULP_CLASS_HID_477d = 0x477d,\n+\tBNXT_ULP_CLASS_HID_10021 = 0x10021,\n+\tBNXT_ULP_CLASS_HID_21621 = 0x21621,\n+\tBNXT_ULP_CLASS_HID_32c21 = 0x32c21,\n+\tBNXT_ULP_CLASS_HID_1081 = 0x1081,\n+\tBNXT_ULP_CLASS_HID_12681 = 0x12681,\n+\tBNXT_ULP_CLASS_HID_23c81 = 0x23c81,\n+\tBNXT_ULP_CLASS_HID_35281 = 0x35281,\n+\tBNXT_ULP_CLASS_HID_146d = 0x146d,\n+\tBNXT_ULP_CLASS_HID_12a6d = 0x12a6d,\n+\tBNXT_ULP_CLASS_HID_2406d = 0x2406d,\n+\tBNXT_ULP_CLASS_HID_3566d = 0x3566d,\n+\tBNXT_ULP_CLASS_HID_4ad9 = 0x4ad9,\n+\tBNXT_ULP_CLASS_HID_1038d = 0x1038d,\n+\tBNXT_ULP_CLASS_HID_2198d = 0x2198d,\n+\tBNXT_ULP_CLASS_HID_32f8d = 0x32f8d,\n+\tBNXT_ULP_CLASS_HID_40b1 = 0x40b1,\n+\tBNXT_ULP_CLASS_HID_156b1 = 0x156b1,\n+\tBNXT_ULP_CLASS_HID_21065 = 0x21065,\n+\tBNXT_ULP_CLASS_HID_32665 = 0x32665,\n+\tBNXT_ULP_CLASS_HID_0ac5 = 0x0ac5,\n+\tBNXT_ULP_CLASS_HID_120c5 = 0x120c5,\n+\tBNXT_ULP_CLASS_HID_236c5 = 0x236c5,\n+\tBNXT_ULP_CLASS_HID_34cc5 = 0x34cc5,\n+\tBNXT_ULP_CLASS_HID_0139 = 0x0139,\n+\tBNXT_ULP_CLASS_HID_11739 = 0x11739,\n+\tBNXT_ULP_CLASS_HID_22d39 = 0x22d39,\n+\tBNXT_ULP_CLASS_HID_34339 = 0x34339,\n+\tBNXT_ULP_CLASS_HID_3795 = 0x3795,\n+\tBNXT_ULP_CLASS_HID_14d95 = 0x14d95,\n+\tBNXT_ULP_CLASS_HID_20759 = 0x20759,\n+\tBNXT_ULP_CLASS_HID_31d59 = 0x31d59,\n+\tBNXT_ULP_CLASS_HID_2e0d = 0x2e0d,\n+\tBNXT_ULP_CLASS_HID_1440d = 0x1440d,\n+\tBNXT_ULP_CLASS_HID_25a0d = 0x25a0d,\n+\tBNXT_ULP_CLASS_HID_31331 = 0x31331,\n+\tBNXT_ULP_CLASS_HID_54ed = 0x54ed,\n+\tBNXT_ULP_CLASS_HID_10d91 = 0x10d91,\n+\tBNXT_ULP_CLASS_HID_22391 = 0x22391,\n+\tBNXT_ULP_CLASS_HID_33991 = 0x33991,\n+\tBNXT_ULP_CLASS_HID_5849 = 0x5849,\n+\tBNXT_ULP_CLASS_HID_1117d = 0x1117d,\n+\tBNXT_ULP_CLASS_HID_2277d = 0x2277d,\n+\tBNXT_ULP_CLASS_HID_33d7d = 0x33d7d,\n+\tBNXT_ULP_CLASS_HID_31e9 = 0x31e9,\n+\tBNXT_ULP_CLASS_HID_147e9 = 0x147e9,\n+\tBNXT_ULP_CLASS_HID_2009d = 0x2009d,\n+\tBNXT_ULP_CLASS_HID_3169d = 0x3169d,\n+\tBNXT_ULP_CLASS_HID_2841 = 0x2841,\n+\tBNXT_ULP_CLASS_HID_13e41 = 0x13e41,\n+\tBNXT_ULP_CLASS_HID_25441 = 0x25441,\n+\tBNXT_ULP_CLASS_HID_30d75 = 0x30d75,\n+\tBNXT_ULP_CLASS_HID_4e21 = 0x4e21,\n+\tBNXT_ULP_CLASS_HID_107d5 = 0x107d5,\n+\tBNXT_ULP_CLASS_HID_21dd5 = 0x21dd5,\n+\tBNXT_ULP_CLASS_HID_333d5 = 0x333d5,\n+\tBNXT_ULP_CLASS_HID_2521 = 0x2521,\n+\tBNXT_ULP_CLASS_HID_2bed = 0x2bed,\n+\tBNXT_ULP_CLASS_HID_1865 = 0x1865,\n+\tBNXT_ULP_CLASS_HID_389d = 0x389d,\n+\tBNXT_ULP_CLASS_HID_123d = 0x123d,\n+\tBNXT_ULP_CLASS_HID_4ef1 = 0x4ef1,\n+\tBNXT_ULP_CLASS_HID_1229 = 0x1229,\n+\tBNXT_ULP_CLASS_HID_3241 = 0x3241,\n+\tBNXT_ULP_CLASS_HID_0be1 = 0x0be1,\n+\tBNXT_ULP_CLASS_HID_48b5 = 0x48b5,\n+\tBNXT_ULP_CLASS_HID_0bed = 0x0bed,\n+\tBNXT_ULP_CLASS_HID_2c05 = 0x2c05,\n+\tBNXT_ULP_CLASS_HID_05a5 = 0x05a5,\n+\tBNXT_ULP_CLASS_HID_4279 = 0x4279,\n+\tBNXT_ULP_CLASS_HID_05d1 = 0x05d1,\n+\tBNXT_ULP_CLASS_HID_25c9 = 0x25c9,\n+\tBNXT_ULP_CLASS_HID_5c55 = 0x5c55,\n+\tBNXT_ULP_CLASS_HID_3c3d = 0x3c3d,\n+\tBNXT_ULP_CLASS_HID_4fc9 = 0x4fc9,\n+\tBNXT_ULP_CLASS_HID_1335 = 0x1335,\n+\tBNXT_ULP_CLASS_HID_4981 = 0x4981,\n+\tBNXT_ULP_CLASS_HID_2969 = 0x2969,\n+\tBNXT_ULP_CLASS_HID_498d = 0x498d,\n+\tBNXT_ULP_CLASS_HID_0cf9 = 0x0cf9,\n+\tBNXT_ULP_CLASS_HID_4345 = 0x4345,\n+\tBNXT_ULP_CLASS_HID_232d = 0x232d,\n+\tBNXT_ULP_CLASS_HID_2579 = 0x2579,\n+\tBNXT_ULP_CLASS_HID_2bb5 = 0x2bb5,\n+\tBNXT_ULP_CLASS_HID_1845 = 0x1845,\n+\tBNXT_ULP_CLASS_HID_1399 = 0x1399,\n+\tBNXT_ULP_CLASS_HID_0eed = 0x0eed,\n+\tBNXT_ULP_CLASS_HID_0a21 = 0x0a21,\n+\tBNXT_ULP_CLASS_HID_38bd = 0x38bd,\n+\tBNXT_ULP_CLASS_HID_33f1 = 0x33f1,\n+\tBNXT_ULP_CLASS_HID_2ec5 = 0x2ec5,\n+\tBNXT_ULP_CLASS_HID_2a19 = 0x2a19,\n+\tBNXT_ULP_CLASS_HID_121d = 0x121d,\n+\tBNXT_ULP_CLASS_HID_0d51 = 0x0d51,\n+\tBNXT_ULP_CLASS_HID_08a5 = 0x08a5,\n+\tBNXT_ULP_CLASS_HID_03f9 = 0x03f9,\n+\tBNXT_ULP_CLASS_HID_4ed1 = 0x4ed1,\n+\tBNXT_ULP_CLASS_HID_4a25 = 0x4a25,\n+\tBNXT_ULP_CLASS_HID_4579 = 0x4579,\n+\tBNXT_ULP_CLASS_HID_404d = 0x404d,\n+\tBNXT_ULP_CLASS_HID_1209 = 0x1209,\n+\tBNXT_ULP_CLASS_HID_0d5d = 0x0d5d,\n+\tBNXT_ULP_CLASS_HID_0891 = 0x0891,\n+\tBNXT_ULP_CLASS_HID_03e5 = 0x03e5,\n+\tBNXT_ULP_CLASS_HID_3261 = 0x3261,\n+\tBNXT_ULP_CLASS_HID_2db5 = 0x2db5,\n+\tBNXT_ULP_CLASS_HID_2889 = 0x2889,\n+\tBNXT_ULP_CLASS_HID_23dd = 0x23dd,\n+\tBNXT_ULP_CLASS_HID_0bc1 = 0x0bc1,\n+\tBNXT_ULP_CLASS_HID_0715 = 0x0715,\n+\tBNXT_ULP_CLASS_HID_0269 = 0x0269,\n+\tBNXT_ULP_CLASS_HID_5a69 = 0x5a69,\n+\tBNXT_ULP_CLASS_HID_4895 = 0x4895,\n+\tBNXT_ULP_CLASS_HID_43e9 = 0x43e9,\n+\tBNXT_ULP_CLASS_HID_3f3d = 0x3f3d,\n+\tBNXT_ULP_CLASS_HID_3a71 = 0x3a71,\n+\tBNXT_ULP_CLASS_HID_0bcd = 0x0bcd,\n+\tBNXT_ULP_CLASS_HID_0701 = 0x0701,\n+\tBNXT_ULP_CLASS_HID_0255 = 0x0255,\n+\tBNXT_ULP_CLASS_HID_5a55 = 0x5a55,\n+\tBNXT_ULP_CLASS_HID_2c25 = 0x2c25,\n+\tBNXT_ULP_CLASS_HID_2779 = 0x2779,\n+\tBNXT_ULP_CLASS_HID_224d = 0x224d,\n+\tBNXT_ULP_CLASS_HID_1d81 = 0x1d81,\n+\tBNXT_ULP_CLASS_HID_0585 = 0x0585,\n+\tBNXT_ULP_CLASS_HID_00d9 = 0x00d9,\n+\tBNXT_ULP_CLASS_HID_58d9 = 0x58d9,\n+\tBNXT_ULP_CLASS_HID_542d = 0x542d,\n+\tBNXT_ULP_CLASS_HID_4259 = 0x4259,\n+\tBNXT_ULP_CLASS_HID_3dad = 0x3dad,\n+\tBNXT_ULP_CLASS_HID_38e1 = 0x38e1,\n+\tBNXT_ULP_CLASS_HID_3435 = 0x3435,\n+\tBNXT_ULP_CLASS_HID_05f1 = 0x05f1,\n+\tBNXT_ULP_CLASS_HID_00c5 = 0x00c5,\n+\tBNXT_ULP_CLASS_HID_58c5 = 0x58c5,\n+\tBNXT_ULP_CLASS_HID_5419 = 0x5419,\n+\tBNXT_ULP_CLASS_HID_25e9 = 0x25e9,\n+\tBNXT_ULP_CLASS_HID_213d = 0x213d,\n+\tBNXT_ULP_CLASS_HID_1c71 = 0x1c71,\n+\tBNXT_ULP_CLASS_HID_1745 = 0x1745,\n+\tBNXT_ULP_CLASS_HID_5c75 = 0x5c75,\n+\tBNXT_ULP_CLASS_HID_5749 = 0x5749,\n+\tBNXT_ULP_CLASS_HID_529d = 0x529d,\n+\tBNXT_ULP_CLASS_HID_4dd1 = 0x4dd1,\n+\tBNXT_ULP_CLASS_HID_3c1d = 0x3c1d,\n+\tBNXT_ULP_CLASS_HID_3751 = 0x3751,\n+\tBNXT_ULP_CLASS_HID_32a5 = 0x32a5,\n+\tBNXT_ULP_CLASS_HID_2df9 = 0x2df9,\n+\tBNXT_ULP_CLASS_HID_4fe9 = 0x4fe9,\n+\tBNXT_ULP_CLASS_HID_4b3d = 0x4b3d,\n+\tBNXT_ULP_CLASS_HID_4671 = 0x4671,\n+\tBNXT_ULP_CLASS_HID_4145 = 0x4145,\n+\tBNXT_ULP_CLASS_HID_1315 = 0x1315,\n+\tBNXT_ULP_CLASS_HID_0e69 = 0x0e69,\n+\tBNXT_ULP_CLASS_HID_09bd = 0x09bd,\n+\tBNXT_ULP_CLASS_HID_04f1 = 0x04f1,\n+\tBNXT_ULP_CLASS_HID_49a1 = 0x49a1,\n+\tBNXT_ULP_CLASS_HID_44f5 = 0x44f5,\n+\tBNXT_ULP_CLASS_HID_3fc9 = 0x3fc9,\n+\tBNXT_ULP_CLASS_HID_3b1d = 0x3b1d,\n+\tBNXT_ULP_CLASS_HID_2949 = 0x2949,\n+\tBNXT_ULP_CLASS_HID_249d = 0x249d,\n+\tBNXT_ULP_CLASS_HID_1fd1 = 0x1fd1,\n+\tBNXT_ULP_CLASS_HID_1b25 = 0x1b25,\n+\tBNXT_ULP_CLASS_HID_49ad = 0x49ad,\n+\tBNXT_ULP_CLASS_HID_44e1 = 0x44e1,\n+\tBNXT_ULP_CLASS_HID_4035 = 0x4035,\n+\tBNXT_ULP_CLASS_HID_3b09 = 0x3b09,\n+\tBNXT_ULP_CLASS_HID_0cd9 = 0x0cd9,\n+\tBNXT_ULP_CLASS_HID_082d = 0x082d,\n+\tBNXT_ULP_CLASS_HID_0361 = 0x0361,\n+\tBNXT_ULP_CLASS_HID_5b61 = 0x5b61,\n+\tBNXT_ULP_CLASS_HID_4365 = 0x4365,\n+\tBNXT_ULP_CLASS_HID_3eb9 = 0x3eb9,\n+\tBNXT_ULP_CLASS_HID_398d = 0x398d,\n+\tBNXT_ULP_CLASS_HID_34c1 = 0x34c1,\n+\tBNXT_ULP_CLASS_HID_230d = 0x230d,\n+\tBNXT_ULP_CLASS_HID_1e41 = 0x1e41,\n+\tBNXT_ULP_CLASS_HID_1995 = 0x1995,\n+\tBNXT_ULP_CLASS_HID_14e9 = 0x14e9,\n+\tBNXT_ULP_CLASS_HID_2559 = 0x2559,\n+\tBNXT_ULP_CLASS_HID_2b95 = 0x2b95,\n+\tBNXT_ULP_CLASS_HID_1825 = 0x1825,\n+\tBNXT_ULP_CLASS_HID_13f9 = 0x13f9,\n+\tBNXT_ULP_CLASS_HID_0e8d = 0x0e8d,\n+\tBNXT_ULP_CLASS_HID_0a41 = 0x0a41,\n+\tBNXT_ULP_CLASS_HID_38dd = 0x38dd,\n+\tBNXT_ULP_CLASS_HID_3391 = 0x3391,\n+\tBNXT_ULP_CLASS_HID_2ea5 = 0x2ea5,\n+\tBNXT_ULP_CLASS_HID_2a79 = 0x2a79,\n+\tBNXT_ULP_CLASS_HID_127d = 0x127d,\n+\tBNXT_ULP_CLASS_HID_0d31 = 0x0d31,\n+\tBNXT_ULP_CLASS_HID_08c5 = 0x08c5,\n+\tBNXT_ULP_CLASS_HID_0399 = 0x0399,\n+\tBNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,\n+\tBNXT_ULP_CLASS_HID_4a45 = 0x4a45,\n+\tBNXT_ULP_CLASS_HID_4519 = 0x4519,\n+\tBNXT_ULP_CLASS_HID_402d = 0x402d,\n+\tBNXT_ULP_CLASS_HID_1269 = 0x1269,\n+\tBNXT_ULP_CLASS_HID_0d3d = 0x0d3d,\n+\tBNXT_ULP_CLASS_HID_08f1 = 0x08f1,\n+\tBNXT_ULP_CLASS_HID_0385 = 0x0385,\n+\tBNXT_ULP_CLASS_HID_3201 = 0x3201,\n+\tBNXT_ULP_CLASS_HID_2dd5 = 0x2dd5,\n+\tBNXT_ULP_CLASS_HID_28e9 = 0x28e9,\n+\tBNXT_ULP_CLASS_HID_23bd = 0x23bd,\n+\tBNXT_ULP_CLASS_HID_0ba1 = 0x0ba1,\n+\tBNXT_ULP_CLASS_HID_0775 = 0x0775,\n+\tBNXT_ULP_CLASS_HID_0209 = 0x0209,\n+\tBNXT_ULP_CLASS_HID_5a09 = 0x5a09,\n+\tBNXT_ULP_CLASS_HID_48f5 = 0x48f5,\n+\tBNXT_ULP_CLASS_HID_4389 = 0x4389,\n+\tBNXT_ULP_CLASS_HID_3f5d = 0x3f5d,\n+\tBNXT_ULP_CLASS_HID_3a11 = 0x3a11,\n+\tBNXT_ULP_CLASS_HID_0bad = 0x0bad,\n+\tBNXT_ULP_CLASS_HID_0761 = 0x0761,\n+\tBNXT_ULP_CLASS_HID_0235 = 0x0235,\n+\tBNXT_ULP_CLASS_HID_5a35 = 0x5a35,\n+\tBNXT_ULP_CLASS_HID_2c45 = 0x2c45,\n+\tBNXT_ULP_CLASS_HID_2719 = 0x2719,\n+\tBNXT_ULP_CLASS_HID_222d = 0x222d,\n+\tBNXT_ULP_CLASS_HID_1de1 = 0x1de1,\n+\tBNXT_ULP_CLASS_HID_05e5 = 0x05e5,\n+\tBNXT_ULP_CLASS_HID_00b9 = 0x00b9,\n+\tBNXT_ULP_CLASS_HID_58b9 = 0x58b9,\n+\tBNXT_ULP_CLASS_HID_544d = 0x544d,\n+\tBNXT_ULP_CLASS_HID_4239 = 0x4239,\n+\tBNXT_ULP_CLASS_HID_3dcd = 0x3dcd,\n+\tBNXT_ULP_CLASS_HID_3881 = 0x3881,\n+\tBNXT_ULP_CLASS_HID_3455 = 0x3455,\n+\tBNXT_ULP_CLASS_HID_0591 = 0x0591,\n+\tBNXT_ULP_CLASS_HID_00a5 = 0x00a5,\n+\tBNXT_ULP_CLASS_HID_58a5 = 0x58a5,\n+\tBNXT_ULP_CLASS_HID_5479 = 0x5479,\n+\tBNXT_ULP_CLASS_HID_2589 = 0x2589,\n+\tBNXT_ULP_CLASS_HID_215d = 0x215d,\n+\tBNXT_ULP_CLASS_HID_1c11 = 0x1c11,\n+\tBNXT_ULP_CLASS_HID_1725 = 0x1725,\n+\tBNXT_ULP_CLASS_HID_5c15 = 0x5c15,\n+\tBNXT_ULP_CLASS_HID_5729 = 0x5729,\n+\tBNXT_ULP_CLASS_HID_52fd = 0x52fd,\n+\tBNXT_ULP_CLASS_HID_4db1 = 0x4db1,\n+\tBNXT_ULP_CLASS_HID_3c7d = 0x3c7d,\n+\tBNXT_ULP_CLASS_HID_3731 = 0x3731,\n+\tBNXT_ULP_CLASS_HID_32c5 = 0x32c5,\n+\tBNXT_ULP_CLASS_HID_2d99 = 0x2d99,\n+\tBNXT_ULP_CLASS_HID_4f89 = 0x4f89,\n+\tBNXT_ULP_CLASS_HID_4b5d = 0x4b5d,\n+\tBNXT_ULP_CLASS_HID_4611 = 0x4611,\n+\tBNXT_ULP_CLASS_HID_4125 = 0x4125,\n+\tBNXT_ULP_CLASS_HID_1375 = 0x1375,\n+\tBNXT_ULP_CLASS_HID_0e09 = 0x0e09,\n+\tBNXT_ULP_CLASS_HID_09dd = 0x09dd,\n+\tBNXT_ULP_CLASS_HID_0491 = 0x0491,\n+\tBNXT_ULP_CLASS_HID_49c1 = 0x49c1,\n+\tBNXT_ULP_CLASS_HID_4495 = 0x4495,\n+\tBNXT_ULP_CLASS_HID_3fa9 = 0x3fa9,\n+\tBNXT_ULP_CLASS_HID_3b7d = 0x3b7d,\n+\tBNXT_ULP_CLASS_HID_2929 = 0x2929,\n+\tBNXT_ULP_CLASS_HID_24fd = 0x24fd,\n+\tBNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,\n+\tBNXT_ULP_CLASS_HID_1b45 = 0x1b45,\n+\tBNXT_ULP_CLASS_HID_49cd = 0x49cd,\n+\tBNXT_ULP_CLASS_HID_4481 = 0x4481,\n+\tBNXT_ULP_CLASS_HID_4055 = 0x4055,\n+\tBNXT_ULP_CLASS_HID_3b69 = 0x3b69,\n+\tBNXT_ULP_CLASS_HID_0cb9 = 0x0cb9,\n+\tBNXT_ULP_CLASS_HID_084d = 0x084d,\n+\tBNXT_ULP_CLASS_HID_0301 = 0x0301,\n+\tBNXT_ULP_CLASS_HID_5b01 = 0x5b01,\n+\tBNXT_ULP_CLASS_HID_4305 = 0x4305,\n+\tBNXT_ULP_CLASS_HID_3ed9 = 0x3ed9,\n+\tBNXT_ULP_CLASS_HID_39ed = 0x39ed,\n+\tBNXT_ULP_CLASS_HID_34a1 = 0x34a1,\n+\tBNXT_ULP_CLASS_HID_236d = 0x236d,\n+\tBNXT_ULP_CLASS_HID_1e21 = 0x1e21,\n+\tBNXT_ULP_CLASS_HID_19f5 = 0x19f5,\n+\tBNXT_ULP_CLASS_HID_1489 = 0x1489,\n+\tBNXT_ULP_CLASS_HID_2539 = 0x2539,\n+\tBNXT_ULP_CLASS_HID_2bf5 = 0x2bf5,\n+\tBNXT_ULP_CLASS_HID_b6af = 0xb6af,\n+\tBNXT_ULP_CLASS_HID_b1d3 = 0xb1d3,\n+\tBNXT_ULP_CLASS_HID_1c7d3 = 0x1c7d3,\n+\tBNXT_ULP_CLASS_HID_1ccaf = 0x1ccaf,\n+\tBNXT_ULP_CLASS_HID_da33 = 0xda33,\n+\tBNXT_ULP_CLASS_HID_d567 = 0xd567,\n+\tBNXT_ULP_CLASS_HID_18eab = 0x18eab,\n+\tBNXT_ULP_CLASS_HID_19367 = 0x19367,\n+\tBNXT_ULP_CLASS_HID_a10b = 0xa10b,\n+\tBNXT_ULP_CLASS_HID_9c3f = 0x9c3f,\n+\tBNXT_ULP_CLASS_HID_1b23f = 0x1b23f,\n+\tBNXT_ULP_CLASS_HID_1b70b = 0x1b70b,\n+\tBNXT_ULP_CLASS_HID_c49f = 0xc49f,\n+\tBNXT_ULP_CLASS_HID_bfc3 = 0xbfc3,\n+\tBNXT_ULP_CLASS_HID_1d5c3 = 0x1d5c3,\n+\tBNXT_ULP_CLASS_HID_1da9f = 0x1da9f,\n+\tBNXT_ULP_CLASS_HID_b063 = 0xb063,\n+\tBNXT_ULP_CLASS_HID_ab97 = 0xab97,\n+\tBNXT_ULP_CLASS_HID_1c197 = 0x1c197,\n+\tBNXT_ULP_CLASS_HID_1c663 = 0x1c663,\n+\tBNXT_ULP_CLASS_HID_d3f7 = 0xd3f7,\n+\tBNXT_ULP_CLASS_HID_cf3b = 0xcf3b,\n+\tBNXT_ULP_CLASS_HID_1886f = 0x1886f,\n+\tBNXT_ULP_CLASS_HID_18d3b = 0x18d3b,\n+\tBNXT_ULP_CLASS_HID_9acf = 0x9acf,\n+\tBNXT_ULP_CLASS_HID_95f3 = 0x95f3,\n+\tBNXT_ULP_CLASS_HID_1abf3 = 0x1abf3,\n+\tBNXT_ULP_CLASS_HID_1b0cf = 0x1b0cf,\n+\tBNXT_ULP_CLASS_HID_be53 = 0xbe53,\n+\tBNXT_ULP_CLASS_HID_b987 = 0xb987,\n+\tBNXT_ULP_CLASS_HID_1cf87 = 0x1cf87,\n+\tBNXT_ULP_CLASS_HID_1d453 = 0x1d453,\n+\tBNXT_ULP_CLASS_HID_aa27 = 0xaa27,\n+\tBNXT_ULP_CLASS_HID_a56b = 0xa56b,\n+\tBNXT_ULP_CLASS_HID_1bb6b = 0x1bb6b,\n+\tBNXT_ULP_CLASS_HID_1c027 = 0x1c027,\n+\tBNXT_ULP_CLASS_HID_cdcb = 0xcdcb,\n+\tBNXT_ULP_CLASS_HID_c8ff = 0xc8ff,\n+\tBNXT_ULP_CLASS_HID_18223 = 0x18223,\n+\tBNXT_ULP_CLASS_HID_186ff = 0x186ff,\n+\tBNXT_ULP_CLASS_HID_9483 = 0x9483,\n+\tBNXT_ULP_CLASS_HID_8fb7 = 0x8fb7,\n+\tBNXT_ULP_CLASS_HID_1a5b7 = 0x1a5b7,\n+\tBNXT_ULP_CLASS_HID_1aa83 = 0x1aa83,\n+\tBNXT_ULP_CLASS_HID_b817 = 0xb817,\n+\tBNXT_ULP_CLASS_HID_b35b = 0xb35b,\n+\tBNXT_ULP_CLASS_HID_1c95b = 0x1c95b,\n+\tBNXT_ULP_CLASS_HID_1ce17 = 0x1ce17,\n+\tBNXT_ULP_CLASS_HID_a3fb = 0xa3fb,\n+\tBNXT_ULP_CLASS_HID_9f2f = 0x9f2f,\n+\tBNXT_ULP_CLASS_HID_1b52f = 0x1b52f,\n+\tBNXT_ULP_CLASS_HID_1b9fb = 0x1b9fb,\n+\tBNXT_ULP_CLASS_HID_c78f = 0xc78f,\n+\tBNXT_ULP_CLASS_HID_c2b3 = 0xc2b3,\n+\tBNXT_ULP_CLASS_HID_1d8b3 = 0x1d8b3,\n+\tBNXT_ULP_CLASS_HID_180b3 = 0x180b3,\n+\tBNXT_ULP_CLASS_HID_8e47 = 0x8e47,\n+\tBNXT_ULP_CLASS_HID_898b = 0x898b,\n+\tBNXT_ULP_CLASS_HID_19f8b = 0x19f8b,\n+\tBNXT_ULP_CLASS_HID_1a447 = 0x1a447,\n+\tBNXT_ULP_CLASS_HID_b1eb = 0xb1eb,\n+\tBNXT_ULP_CLASS_HID_ad1f = 0xad1f,\n+\tBNXT_ULP_CLASS_HID_1c31f = 0x1c31f,\n+\tBNXT_ULP_CLASS_HID_1c7eb = 0x1c7eb,\n+\tBNXT_ULP_CLASS_HID_9137 = 0x9137,\n+\tBNXT_ULP_CLASS_HID_8c7b = 0x8c7b,\n+\tBNXT_ULP_CLASS_HID_1a27b = 0x1a27b,\n+\tBNXT_ULP_CLASS_HID_1a737 = 0x1a737,\n+\tBNXT_ULP_CLASS_HID_b4db = 0xb4db,\n+\tBNXT_ULP_CLASS_HID_b00f = 0xb00f,\n+\tBNXT_ULP_CLASS_HID_1c60f = 0x1c60f,\n+\tBNXT_ULP_CLASS_HID_1cadb = 0x1cadb,\n+\tBNXT_ULP_CLASS_HID_8b0b = 0x8b0b,\n+\tBNXT_ULP_CLASS_HID_863f = 0x863f,\n+\tBNXT_ULP_CLASS_HID_19c3f = 0x19c3f,\n+\tBNXT_ULP_CLASS_HID_1a10b = 0x1a10b,\n+\tBNXT_ULP_CLASS_HID_ae9f = 0xae9f,\n+\tBNXT_ULP_CLASS_HID_a9c3 = 0xa9c3,\n+\tBNXT_ULP_CLASS_HID_1bfc3 = 0x1bfc3,\n+\tBNXT_ULP_CLASS_HID_1c49f = 0x1c49f,\n+\tBNXT_ULP_CLASS_HID_2563 = 0x2563,\n+\tBNXT_ULP_CLASS_HID_2baf = 0x2baf,\n+\tBNXT_ULP_CLASS_HID_4f33 = 0x4f33,\n+\tBNXT_ULP_CLASS_HID_160b = 0x160b,\n+\tBNXT_ULP_CLASS_HID_399f = 0x399f,\n+\tBNXT_ULP_CLASS_HID_48f7 = 0x48f7,\n+\tBNXT_ULP_CLASS_HID_0fcf = 0x0fcf,\n+\tBNXT_ULP_CLASS_HID_3353 = 0x3353,\n+\tBNXT_ULP_CLASS_HID_b68f = 0xb68f,\n+\tBNXT_ULP_CLASS_HID_b94f = 0xb94f,\n+\tBNXT_ULP_CLASS_HID_fc0f = 0xfc0f,\n+\tBNXT_ULP_CLASS_HID_fecf = 0xfecf,\n+\tBNXT_ULP_CLASS_HID_b1f3 = 0xb1f3,\n+\tBNXT_ULP_CLASS_HID_b4b3 = 0xb4b3,\n+\tBNXT_ULP_CLASS_HID_f773 = 0xf773,\n+\tBNXT_ULP_CLASS_HID_fa33 = 0xfa33,\n+\tBNXT_ULP_CLASS_HID_1c7f3 = 0x1c7f3,\n+\tBNXT_ULP_CLASS_HID_1eab3 = 0x1eab3,\n+\tBNXT_ULP_CLASS_HID_1cd73 = 0x1cd73,\n+\tBNXT_ULP_CLASS_HID_1f033 = 0x1f033,\n+\tBNXT_ULP_CLASS_HID_1cc8f = 0x1cc8f,\n+\tBNXT_ULP_CLASS_HID_1ef4f = 0x1ef4f,\n+\tBNXT_ULP_CLASS_HID_1d20f = 0x1d20f,\n+\tBNXT_ULP_CLASS_HID_1f4cf = 0x1f4cf,\n+\tBNXT_ULP_CLASS_HID_da13 = 0xda13,\n+\tBNXT_ULP_CLASS_HID_a007 = 0xa007,\n+\tBNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,\n+\tBNXT_ULP_CLASS_HID_e587 = 0xe587,\n+\tBNXT_ULP_CLASS_HID_d547 = 0xd547,\n+\tBNXT_ULP_CLASS_HID_f807 = 0xf807,\n+\tBNXT_ULP_CLASS_HID_dac7 = 0xdac7,\n+\tBNXT_ULP_CLASS_HID_e0cb = 0xe0cb,\n+\tBNXT_ULP_CLASS_HID_18e8b = 0x18e8b,\n+\tBNXT_ULP_CLASS_HID_1b14b = 0x1b14b,\n+\tBNXT_ULP_CLASS_HID_1d40b = 0x1d40b,\n+\tBNXT_ULP_CLASS_HID_1f6cb = 0x1f6cb,\n+\tBNXT_ULP_CLASS_HID_19347 = 0x19347,\n+\tBNXT_ULP_CLASS_HID_1b607 = 0x1b607,\n+\tBNXT_ULP_CLASS_HID_1d8c7 = 0x1d8c7,\n+\tBNXT_ULP_CLASS_HID_1fb87 = 0x1fb87,\n+\tBNXT_ULP_CLASS_HID_a12b = 0xa12b,\n+\tBNXT_ULP_CLASS_HID_a3eb = 0xa3eb,\n+\tBNXT_ULP_CLASS_HID_e6ab = 0xe6ab,\n+\tBNXT_ULP_CLASS_HID_e96b = 0xe96b,\n+\tBNXT_ULP_CLASS_HID_9c1f = 0x9c1f,\n+\tBNXT_ULP_CLASS_HID_bedf = 0xbedf,\n+\tBNXT_ULP_CLASS_HID_e19f = 0xe19f,\n+\tBNXT_ULP_CLASS_HID_e45f = 0xe45f,\n+\tBNXT_ULP_CLASS_HID_1b21f = 0x1b21f,\n+\tBNXT_ULP_CLASS_HID_1b4df = 0x1b4df,\n+\tBNXT_ULP_CLASS_HID_1f79f = 0x1f79f,\n+\tBNXT_ULP_CLASS_HID_1fa5f = 0x1fa5f,\n+\tBNXT_ULP_CLASS_HID_1b72b = 0x1b72b,\n+\tBNXT_ULP_CLASS_HID_1b9eb = 0x1b9eb,\n+\tBNXT_ULP_CLASS_HID_1fcab = 0x1fcab,\n+\tBNXT_ULP_CLASS_HID_1ff6b = 0x1ff6b,\n+\tBNXT_ULP_CLASS_HID_c4bf = 0xc4bf,\n+\tBNXT_ULP_CLASS_HID_e77f = 0xe77f,\n+\tBNXT_ULP_CLASS_HID_ca3f = 0xca3f,\n+\tBNXT_ULP_CLASS_HID_ecff = 0xecff,\n+\tBNXT_ULP_CLASS_HID_bfe3 = 0xbfe3,\n+\tBNXT_ULP_CLASS_HID_e2a3 = 0xe2a3,\n+\tBNXT_ULP_CLASS_HID_c563 = 0xc563,\n+\tBNXT_ULP_CLASS_HID_e823 = 0xe823,\n+\tBNXT_ULP_CLASS_HID_1d5e3 = 0x1d5e3,\n+\tBNXT_ULP_CLASS_HID_1f8a3 = 0x1f8a3,\n+\tBNXT_ULP_CLASS_HID_1db63 = 0x1db63,\n+\tBNXT_ULP_CLASS_HID_1e117 = 0x1e117,\n+\tBNXT_ULP_CLASS_HID_1dabf = 0x1dabf,\n+\tBNXT_ULP_CLASS_HID_1a0a3 = 0x1a0a3,\n+\tBNXT_ULP_CLASS_HID_1c363 = 0x1c363,\n+\tBNXT_ULP_CLASS_HID_1e623 = 0x1e623,\n+\tBNXT_ULP_CLASS_HID_b043 = 0xb043,\n+\tBNXT_ULP_CLASS_HID_b303 = 0xb303,\n+\tBNXT_ULP_CLASS_HID_f5c3 = 0xf5c3,\n+\tBNXT_ULP_CLASS_HID_f883 = 0xf883,\n+\tBNXT_ULP_CLASS_HID_abb7 = 0xabb7,\n+\tBNXT_ULP_CLASS_HID_ae77 = 0xae77,\n+\tBNXT_ULP_CLASS_HID_f137 = 0xf137,\n+\tBNXT_ULP_CLASS_HID_f3f7 = 0xf3f7,\n+\tBNXT_ULP_CLASS_HID_1c1b7 = 0x1c1b7,\n+\tBNXT_ULP_CLASS_HID_1e477 = 0x1e477,\n+\tBNXT_ULP_CLASS_HID_1c737 = 0x1c737,\n+\tBNXT_ULP_CLASS_HID_1e9f7 = 0x1e9f7,\n+\tBNXT_ULP_CLASS_HID_1c643 = 0x1c643,\n+\tBNXT_ULP_CLASS_HID_1e903 = 0x1e903,\n+\tBNXT_ULP_CLASS_HID_1cbc3 = 0x1cbc3,\n+\tBNXT_ULP_CLASS_HID_1ee83 = 0x1ee83,\n+\tBNXT_ULP_CLASS_HID_d3d7 = 0xd3d7,\n+\tBNXT_ULP_CLASS_HID_f697 = 0xf697,\n+\tBNXT_ULP_CLASS_HID_d957 = 0xd957,\n+\tBNXT_ULP_CLASS_HID_fc17 = 0xfc17,\n+\tBNXT_ULP_CLASS_HID_cf1b = 0xcf1b,\n+\tBNXT_ULP_CLASS_HID_f1db = 0xf1db,\n+\tBNXT_ULP_CLASS_HID_d49b = 0xd49b,\n+\tBNXT_ULP_CLASS_HID_f75b = 0xf75b,\n+\tBNXT_ULP_CLASS_HID_1884f = 0x1884f,\n+\tBNXT_ULP_CLASS_HID_1ab0f = 0x1ab0f,\n+\tBNXT_ULP_CLASS_HID_1cdcf = 0x1cdcf,\n+\tBNXT_ULP_CLASS_HID_1f08f = 0x1f08f,\n+\tBNXT_ULP_CLASS_HID_18d1b = 0x18d1b,\n+\tBNXT_ULP_CLASS_HID_1afdb = 0x1afdb,\n+\tBNXT_ULP_CLASS_HID_1d29b = 0x1d29b,\n+\tBNXT_ULP_CLASS_HID_1f55b = 0x1f55b,\n+\tBNXT_ULP_CLASS_HID_9aef = 0x9aef,\n+\tBNXT_ULP_CLASS_HID_bdaf = 0xbdaf,\n+\tBNXT_ULP_CLASS_HID_e06f = 0xe06f,\n+\tBNXT_ULP_CLASS_HID_e32f = 0xe32f,\n+\tBNXT_ULP_CLASS_HID_95d3 = 0x95d3,\n+\tBNXT_ULP_CLASS_HID_b893 = 0xb893,\n+\tBNXT_ULP_CLASS_HID_db53 = 0xdb53,\n+\tBNXT_ULP_CLASS_HID_fe13 = 0xfe13,\n+\tBNXT_ULP_CLASS_HID_1abd3 = 0x1abd3,\n+\tBNXT_ULP_CLASS_HID_1ae93 = 0x1ae93,\n+\tBNXT_ULP_CLASS_HID_1f153 = 0x1f153,\n+\tBNXT_ULP_CLASS_HID_1f413 = 0x1f413,\n+\tBNXT_ULP_CLASS_HID_1b0ef = 0x1b0ef,\n+\tBNXT_ULP_CLASS_HID_1b3af = 0x1b3af,\n+\tBNXT_ULP_CLASS_HID_1f66f = 0x1f66f,\n+\tBNXT_ULP_CLASS_HID_1f92f = 0x1f92f,\n+\tBNXT_ULP_CLASS_HID_be73 = 0xbe73,\n+\tBNXT_ULP_CLASS_HID_e133 = 0xe133,\n+\tBNXT_ULP_CLASS_HID_c3f3 = 0xc3f3,\n+\tBNXT_ULP_CLASS_HID_e6b3 = 0xe6b3,\n+\tBNXT_ULP_CLASS_HID_b9a7 = 0xb9a7,\n+\tBNXT_ULP_CLASS_HID_bc67 = 0xbc67,\n+\tBNXT_ULP_CLASS_HID_ff27 = 0xff27,\n+\tBNXT_ULP_CLASS_HID_e1e7 = 0xe1e7,\n+\tBNXT_ULP_CLASS_HID_1cfa7 = 0x1cfa7,\n+\tBNXT_ULP_CLASS_HID_1f267 = 0x1f267,\n+\tBNXT_ULP_CLASS_HID_1d527 = 0x1d527,\n+\tBNXT_ULP_CLASS_HID_1f7e7 = 0x1f7e7,\n+\tBNXT_ULP_CLASS_HID_1d473 = 0x1d473,\n+\tBNXT_ULP_CLASS_HID_1f733 = 0x1f733,\n+\tBNXT_ULP_CLASS_HID_1d9f3 = 0x1d9f3,\n+\tBNXT_ULP_CLASS_HID_1fcb3 = 0x1fcb3,\n+\tBNXT_ULP_CLASS_HID_aa07 = 0xaa07,\n+\tBNXT_ULP_CLASS_HID_acc7 = 0xacc7,\n+\tBNXT_ULP_CLASS_HID_ef87 = 0xef87,\n+\tBNXT_ULP_CLASS_HID_f247 = 0xf247,\n+\tBNXT_ULP_CLASS_HID_a54b = 0xa54b,\n+\tBNXT_ULP_CLASS_HID_a80b = 0xa80b,\n+\tBNXT_ULP_CLASS_HID_eacb = 0xeacb,\n+\tBNXT_ULP_CLASS_HID_ed8b = 0xed8b,\n+\tBNXT_ULP_CLASS_HID_1bb4b = 0x1bb4b,\n+\tBNXT_ULP_CLASS_HID_1be0b = 0x1be0b,\n+\tBNXT_ULP_CLASS_HID_1c0cb = 0x1c0cb,\n+\tBNXT_ULP_CLASS_HID_1e38b = 0x1e38b,\n+\tBNXT_ULP_CLASS_HID_1c007 = 0x1c007,\n+\tBNXT_ULP_CLASS_HID_1e2c7 = 0x1e2c7,\n+\tBNXT_ULP_CLASS_HID_1c587 = 0x1c587,\n+\tBNXT_ULP_CLASS_HID_1e847 = 0x1e847,\n+\tBNXT_ULP_CLASS_HID_cdeb = 0xcdeb,\n+\tBNXT_ULP_CLASS_HID_f0ab = 0xf0ab,\n+\tBNXT_ULP_CLASS_HID_d36b = 0xd36b,\n+\tBNXT_ULP_CLASS_HID_f62b = 0xf62b,\n+\tBNXT_ULP_CLASS_HID_c8df = 0xc8df,\n+\tBNXT_ULP_CLASS_HID_eb9f = 0xeb9f,\n+\tBNXT_ULP_CLASS_HID_ce5f = 0xce5f,\n+\tBNXT_ULP_CLASS_HID_f11f = 0xf11f,\n+\tBNXT_ULP_CLASS_HID_18203 = 0x18203,\n+\tBNXT_ULP_CLASS_HID_1a4c3 = 0x1a4c3,\n+\tBNXT_ULP_CLASS_HID_1c783 = 0x1c783,\n+\tBNXT_ULP_CLASS_HID_1ea43 = 0x1ea43,\n+\tBNXT_ULP_CLASS_HID_186df = 0x186df,\n+\tBNXT_ULP_CLASS_HID_1a99f = 0x1a99f,\n+\tBNXT_ULP_CLASS_HID_1cc5f = 0x1cc5f,\n+\tBNXT_ULP_CLASS_HID_1ef1f = 0x1ef1f,\n+\tBNXT_ULP_CLASS_HID_94a3 = 0x94a3,\n+\tBNXT_ULP_CLASS_HID_b763 = 0xb763,\n+\tBNXT_ULP_CLASS_HID_da23 = 0xda23,\n+\tBNXT_ULP_CLASS_HID_fce3 = 0xfce3,\n+\tBNXT_ULP_CLASS_HID_8f97 = 0x8f97,\n+\tBNXT_ULP_CLASS_HID_b257 = 0xb257,\n+\tBNXT_ULP_CLASS_HID_d517 = 0xd517,\n+\tBNXT_ULP_CLASS_HID_f7d7 = 0xf7d7,\n+\tBNXT_ULP_CLASS_HID_1a597 = 0x1a597,\n+\tBNXT_ULP_CLASS_HID_1a857 = 0x1a857,\n+\tBNXT_ULP_CLASS_HID_1eb17 = 0x1eb17,\n+\tBNXT_ULP_CLASS_HID_1edd7 = 0x1edd7,\n+\tBNXT_ULP_CLASS_HID_1aaa3 = 0x1aaa3,\n+\tBNXT_ULP_CLASS_HID_1ad63 = 0x1ad63,\n+\tBNXT_ULP_CLASS_HID_1f023 = 0x1f023,\n+\tBNXT_ULP_CLASS_HID_1f2e3 = 0x1f2e3,\n+\tBNXT_ULP_CLASS_HID_b837 = 0xb837,\n+\tBNXT_ULP_CLASS_HID_baf7 = 0xbaf7,\n+\tBNXT_ULP_CLASS_HID_fdb7 = 0xfdb7,\n+\tBNXT_ULP_CLASS_HID_e077 = 0xe077,\n+\tBNXT_ULP_CLASS_HID_b37b = 0xb37b,\n+\tBNXT_ULP_CLASS_HID_b63b = 0xb63b,\n+\tBNXT_ULP_CLASS_HID_f8fb = 0xf8fb,\n+\tBNXT_ULP_CLASS_HID_fbbb = 0xfbbb,\n+\tBNXT_ULP_CLASS_HID_1c97b = 0x1c97b,\n+\tBNXT_ULP_CLASS_HID_1ec3b = 0x1ec3b,\n+\tBNXT_ULP_CLASS_HID_1cefb = 0x1cefb,\n+\tBNXT_ULP_CLASS_HID_1f1bb = 0x1f1bb,\n+\tBNXT_ULP_CLASS_HID_1ce37 = 0x1ce37,\n+\tBNXT_ULP_CLASS_HID_1f0f7 = 0x1f0f7,\n+\tBNXT_ULP_CLASS_HID_1d3b7 = 0x1d3b7,\n+\tBNXT_ULP_CLASS_HID_1f677 = 0x1f677,\n+\tBNXT_ULP_CLASS_HID_a3db = 0xa3db,\n+\tBNXT_ULP_CLASS_HID_a69b = 0xa69b,\n+\tBNXT_ULP_CLASS_HID_e95b = 0xe95b,\n+\tBNXT_ULP_CLASS_HID_ec1b = 0xec1b,\n+\tBNXT_ULP_CLASS_HID_9f0f = 0x9f0f,\n+\tBNXT_ULP_CLASS_HID_a1cf = 0xa1cf,\n+\tBNXT_ULP_CLASS_HID_e48f = 0xe48f,\n+\tBNXT_ULP_CLASS_HID_e74f = 0xe74f,\n+\tBNXT_ULP_CLASS_HID_1b50f = 0x1b50f,\n+\tBNXT_ULP_CLASS_HID_1b7cf = 0x1b7cf,\n+\tBNXT_ULP_CLASS_HID_1fa8f = 0x1fa8f,\n+\tBNXT_ULP_CLASS_HID_1fd4f = 0x1fd4f,\n+\tBNXT_ULP_CLASS_HID_1b9db = 0x1b9db,\n+\tBNXT_ULP_CLASS_HID_1bc9b = 0x1bc9b,\n+\tBNXT_ULP_CLASS_HID_1ff5b = 0x1ff5b,\n+\tBNXT_ULP_CLASS_HID_1e21b = 0x1e21b,\n+\tBNXT_ULP_CLASS_HID_c7af = 0xc7af,\n+\tBNXT_ULP_CLASS_HID_ea6f = 0xea6f,\n+\tBNXT_ULP_CLASS_HID_cd2f = 0xcd2f,\n+\tBNXT_ULP_CLASS_HID_efef = 0xefef,\n+\tBNXT_ULP_CLASS_HID_c293 = 0xc293,\n+\tBNXT_ULP_CLASS_HID_e553 = 0xe553,\n+\tBNXT_ULP_CLASS_HID_c813 = 0xc813,\n+\tBNXT_ULP_CLASS_HID_ead3 = 0xead3,\n+\tBNXT_ULP_CLASS_HID_1d893 = 0x1d893,\n+\tBNXT_ULP_CLASS_HID_1fb53 = 0x1fb53,\n+\tBNXT_ULP_CLASS_HID_1c147 = 0x1c147,\n+\tBNXT_ULP_CLASS_HID_1e407 = 0x1e407,\n+\tBNXT_ULP_CLASS_HID_18093 = 0x18093,\n+\tBNXT_ULP_CLASS_HID_1a353 = 0x1a353,\n+\tBNXT_ULP_CLASS_HID_1c613 = 0x1c613,\n+\tBNXT_ULP_CLASS_HID_1e8d3 = 0x1e8d3,\n+\tBNXT_ULP_CLASS_HID_8e67 = 0x8e67,\n+\tBNXT_ULP_CLASS_HID_b127 = 0xb127,\n+\tBNXT_ULP_CLASS_HID_d3e7 = 0xd3e7,\n+\tBNXT_ULP_CLASS_HID_f6a7 = 0xf6a7,\n+\tBNXT_ULP_CLASS_HID_89ab = 0x89ab,\n+\tBNXT_ULP_CLASS_HID_ac6b = 0xac6b,\n+\tBNXT_ULP_CLASS_HID_cf2b = 0xcf2b,\n+\tBNXT_ULP_CLASS_HID_f1eb = 0xf1eb,\n+\tBNXT_ULP_CLASS_HID_19fab = 0x19fab,\n+\tBNXT_ULP_CLASS_HID_1a26b = 0x1a26b,\n+\tBNXT_ULP_CLASS_HID_1e52b = 0x1e52b,\n+\tBNXT_ULP_CLASS_HID_1e7eb = 0x1e7eb,\n+\tBNXT_ULP_CLASS_HID_1a467 = 0x1a467,\n+\tBNXT_ULP_CLASS_HID_1a727 = 0x1a727,\n+\tBNXT_ULP_CLASS_HID_1e9e7 = 0x1e9e7,\n+\tBNXT_ULP_CLASS_HID_1eca7 = 0x1eca7,\n+\tBNXT_ULP_CLASS_HID_b1cb = 0xb1cb,\n+\tBNXT_ULP_CLASS_HID_b48b = 0xb48b,\n+\tBNXT_ULP_CLASS_HID_f74b = 0xf74b,\n+\tBNXT_ULP_CLASS_HID_fa0b = 0xfa0b,\n+\tBNXT_ULP_CLASS_HID_ad3f = 0xad3f,\n+\tBNXT_ULP_CLASS_HID_afff = 0xafff,\n+\tBNXT_ULP_CLASS_HID_f2bf = 0xf2bf,\n+\tBNXT_ULP_CLASS_HID_f57f = 0xf57f,\n+\tBNXT_ULP_CLASS_HID_1c33f = 0x1c33f,\n+\tBNXT_ULP_CLASS_HID_1e5ff = 0x1e5ff,\n+\tBNXT_ULP_CLASS_HID_1c8bf = 0x1c8bf,\n+\tBNXT_ULP_CLASS_HID_1eb7f = 0x1eb7f,\n+\tBNXT_ULP_CLASS_HID_1c7cb = 0x1c7cb,\n+\tBNXT_ULP_CLASS_HID_1ea8b = 0x1ea8b,\n+\tBNXT_ULP_CLASS_HID_1cd4b = 0x1cd4b,\n+\tBNXT_ULP_CLASS_HID_1f00b = 0x1f00b,\n+\tBNXT_ULP_CLASS_HID_9117 = 0x9117,\n+\tBNXT_ULP_CLASS_HID_b3d7 = 0xb3d7,\n+\tBNXT_ULP_CLASS_HID_d697 = 0xd697,\n+\tBNXT_ULP_CLASS_HID_f957 = 0xf957,\n+\tBNXT_ULP_CLASS_HID_8c5b = 0x8c5b,\n+\tBNXT_ULP_CLASS_HID_af1b = 0xaf1b,\n+\tBNXT_ULP_CLASS_HID_d1db = 0xd1db,\n+\tBNXT_ULP_CLASS_HID_f49b = 0xf49b,\n+\tBNXT_ULP_CLASS_HID_1a25b = 0x1a25b,\n+\tBNXT_ULP_CLASS_HID_1a51b = 0x1a51b,\n+\tBNXT_ULP_CLASS_HID_1e7db = 0x1e7db,\n+\tBNXT_ULP_CLASS_HID_1ea9b = 0x1ea9b,\n+\tBNXT_ULP_CLASS_HID_1a717 = 0x1a717,\n+\tBNXT_ULP_CLASS_HID_1a9d7 = 0x1a9d7,\n+\tBNXT_ULP_CLASS_HID_1ec97 = 0x1ec97,\n+\tBNXT_ULP_CLASS_HID_1ef57 = 0x1ef57,\n+\tBNXT_ULP_CLASS_HID_b4fb = 0xb4fb,\n+\tBNXT_ULP_CLASS_HID_b7bb = 0xb7bb,\n+\tBNXT_ULP_CLASS_HID_fa7b = 0xfa7b,\n+\tBNXT_ULP_CLASS_HID_fd3b = 0xfd3b,\n+\tBNXT_ULP_CLASS_HID_b02f = 0xb02f,\n+\tBNXT_ULP_CLASS_HID_b2ef = 0xb2ef,\n+\tBNXT_ULP_CLASS_HID_f5af = 0xf5af,\n+\tBNXT_ULP_CLASS_HID_f86f = 0xf86f,\n+\tBNXT_ULP_CLASS_HID_1c62f = 0x1c62f,\n+\tBNXT_ULP_CLASS_HID_1e8ef = 0x1e8ef,\n+\tBNXT_ULP_CLASS_HID_1cbaf = 0x1cbaf,\n+\tBNXT_ULP_CLASS_HID_1ee6f = 0x1ee6f,\n+\tBNXT_ULP_CLASS_HID_1cafb = 0x1cafb,\n+\tBNXT_ULP_CLASS_HID_1edbb = 0x1edbb,\n+\tBNXT_ULP_CLASS_HID_1d07b = 0x1d07b,\n+\tBNXT_ULP_CLASS_HID_1f33b = 0x1f33b,\n+\tBNXT_ULP_CLASS_HID_8b2b = 0x8b2b,\n+\tBNXT_ULP_CLASS_HID_adeb = 0xadeb,\n+\tBNXT_ULP_CLASS_HID_d0ab = 0xd0ab,\n+\tBNXT_ULP_CLASS_HID_f36b = 0xf36b,\n+\tBNXT_ULP_CLASS_HID_861f = 0x861f,\n+\tBNXT_ULP_CLASS_HID_a8df = 0xa8df,\n+\tBNXT_ULP_CLASS_HID_cb9f = 0xcb9f,\n+\tBNXT_ULP_CLASS_HID_ee5f = 0xee5f,\n+\tBNXT_ULP_CLASS_HID_19c1f = 0x19c1f,\n+\tBNXT_ULP_CLASS_HID_1bedf = 0x1bedf,\n+\tBNXT_ULP_CLASS_HID_1e19f = 0x1e19f,\n+\tBNXT_ULP_CLASS_HID_1e45f = 0x1e45f,\n+\tBNXT_ULP_CLASS_HID_1a12b = 0x1a12b,\n+\tBNXT_ULP_CLASS_HID_1a3eb = 0x1a3eb,\n+\tBNXT_ULP_CLASS_HID_1e6ab = 0x1e6ab,\n+\tBNXT_ULP_CLASS_HID_1e96b = 0x1e96b,\n+\tBNXT_ULP_CLASS_HID_aebf = 0xaebf,\n+\tBNXT_ULP_CLASS_HID_b17f = 0xb17f,\n+\tBNXT_ULP_CLASS_HID_f43f = 0xf43f,\n+\tBNXT_ULP_CLASS_HID_f6ff = 0xf6ff,\n+\tBNXT_ULP_CLASS_HID_a9e3 = 0xa9e3,\n+\tBNXT_ULP_CLASS_HID_aca3 = 0xaca3,\n+\tBNXT_ULP_CLASS_HID_ef63 = 0xef63,\n+\tBNXT_ULP_CLASS_HID_f223 = 0xf223,\n+\tBNXT_ULP_CLASS_HID_1bfe3 = 0x1bfe3,\n+\tBNXT_ULP_CLASS_HID_1e2a3 = 0x1e2a3,\n+\tBNXT_ULP_CLASS_HID_1c563 = 0x1c563,\n+\tBNXT_ULP_CLASS_HID_1e823 = 0x1e823,\n+\tBNXT_ULP_CLASS_HID_1c4bf = 0x1c4bf,\n+\tBNXT_ULP_CLASS_HID_1e77f = 0x1e77f,\n+\tBNXT_ULP_CLASS_HID_1ca3f = 0x1ca3f,\n+\tBNXT_ULP_CLASS_HID_1ecff = 0x1ecff,\n+\tBNXT_ULP_CLASS_HID_2543 = 0x2543,\n+\tBNXT_ULP_CLASS_HID_2b8f = 0x2b8f,\n+\tBNXT_ULP_CLASS_HID_4f13 = 0x4f13,\n+\tBNXT_ULP_CLASS_HID_162b = 0x162b,\n+\tBNXT_ULP_CLASS_HID_39bf = 0x39bf,\n+\tBNXT_ULP_CLASS_HID_48d7 = 0x48d7,\n+\tBNXT_ULP_CLASS_HID_0fef = 0x0fef,\n+\tBNXT_ULP_CLASS_HID_3373 = 0x3373,\n+\tBNXT_ULP_CLASS_HID_b6ef = 0xb6ef,\n+\tBNXT_ULP_CLASS_HID_b92f = 0xb92f,\n+\tBNXT_ULP_CLASS_HID_fc6f = 0xfc6f,\n+\tBNXT_ULP_CLASS_HID_feaf = 0xfeaf,\n+\tBNXT_ULP_CLASS_HID_b193 = 0xb193,\n+\tBNXT_ULP_CLASS_HID_b4d3 = 0xb4d3,\n+\tBNXT_ULP_CLASS_HID_f713 = 0xf713,\n+\tBNXT_ULP_CLASS_HID_fa53 = 0xfa53,\n+\tBNXT_ULP_CLASS_HID_1c793 = 0x1c793,\n+\tBNXT_ULP_CLASS_HID_1ead3 = 0x1ead3,\n+\tBNXT_ULP_CLASS_HID_1cd13 = 0x1cd13,\n+\tBNXT_ULP_CLASS_HID_1f053 = 0x1f053,\n+\tBNXT_ULP_CLASS_HID_1ccef = 0x1ccef,\n+\tBNXT_ULP_CLASS_HID_1ef2f = 0x1ef2f,\n+\tBNXT_ULP_CLASS_HID_1d26f = 0x1d26f,\n+\tBNXT_ULP_CLASS_HID_1f4af = 0x1f4af,\n+\tBNXT_ULP_CLASS_HID_da73 = 0xda73,\n+\tBNXT_ULP_CLASS_HID_a067 = 0xa067,\n+\tBNXT_ULP_CLASS_HID_c2a7 = 0xc2a7,\n+\tBNXT_ULP_CLASS_HID_e5e7 = 0xe5e7,\n+\tBNXT_ULP_CLASS_HID_d527 = 0xd527,\n+\tBNXT_ULP_CLASS_HID_f867 = 0xf867,\n+\tBNXT_ULP_CLASS_HID_daa7 = 0xdaa7,\n+\tBNXT_ULP_CLASS_HID_e0ab = 0xe0ab,\n+\tBNXT_ULP_CLASS_HID_18eeb = 0x18eeb,\n+\tBNXT_ULP_CLASS_HID_1b12b = 0x1b12b,\n+\tBNXT_ULP_CLASS_HID_1d46b = 0x1d46b,\n+\tBNXT_ULP_CLASS_HID_1f6ab = 0x1f6ab,\n+\tBNXT_ULP_CLASS_HID_19327 = 0x19327,\n+\tBNXT_ULP_CLASS_HID_1b667 = 0x1b667,\n+\tBNXT_ULP_CLASS_HID_1d8a7 = 0x1d8a7,\n+\tBNXT_ULP_CLASS_HID_1fbe7 = 0x1fbe7,\n+\tBNXT_ULP_CLASS_HID_a14b = 0xa14b,\n+\tBNXT_ULP_CLASS_HID_a38b = 0xa38b,\n+\tBNXT_ULP_CLASS_HID_e6cb = 0xe6cb,\n+\tBNXT_ULP_CLASS_HID_e90b = 0xe90b,\n+\tBNXT_ULP_CLASS_HID_9c7f = 0x9c7f,\n+\tBNXT_ULP_CLASS_HID_bebf = 0xbebf,\n+\tBNXT_ULP_CLASS_HID_e1ff = 0xe1ff,\n+\tBNXT_ULP_CLASS_HID_e43f = 0xe43f,\n+\tBNXT_ULP_CLASS_HID_1b27f = 0x1b27f,\n+\tBNXT_ULP_CLASS_HID_1b4bf = 0x1b4bf,\n+\tBNXT_ULP_CLASS_HID_1f7ff = 0x1f7ff,\n+\tBNXT_ULP_CLASS_HID_1fa3f = 0x1fa3f,\n+\tBNXT_ULP_CLASS_HID_1b74b = 0x1b74b,\n+\tBNXT_ULP_CLASS_HID_1b98b = 0x1b98b,\n+\tBNXT_ULP_CLASS_HID_1fccb = 0x1fccb,\n+\tBNXT_ULP_CLASS_HID_1ff0b = 0x1ff0b,\n+\tBNXT_ULP_CLASS_HID_c4df = 0xc4df,\n+\tBNXT_ULP_CLASS_HID_e71f = 0xe71f,\n+\tBNXT_ULP_CLASS_HID_ca5f = 0xca5f,\n+\tBNXT_ULP_CLASS_HID_ec9f = 0xec9f,\n+\tBNXT_ULP_CLASS_HID_bf83 = 0xbf83,\n+\tBNXT_ULP_CLASS_HID_e2c3 = 0xe2c3,\n+\tBNXT_ULP_CLASS_HID_c503 = 0xc503,\n+\tBNXT_ULP_CLASS_HID_e843 = 0xe843,\n+\tBNXT_ULP_CLASS_HID_1d583 = 0x1d583,\n+\tBNXT_ULP_CLASS_HID_1f8c3 = 0x1f8c3,\n+\tBNXT_ULP_CLASS_HID_1db03 = 0x1db03,\n+\tBNXT_ULP_CLASS_HID_1e177 = 0x1e177,\n+\tBNXT_ULP_CLASS_HID_1dadf = 0x1dadf,\n+\tBNXT_ULP_CLASS_HID_1a0c3 = 0x1a0c3,\n+\tBNXT_ULP_CLASS_HID_1c303 = 0x1c303,\n+\tBNXT_ULP_CLASS_HID_1e643 = 0x1e643,\n+\tBNXT_ULP_CLASS_HID_b023 = 0xb023,\n+\tBNXT_ULP_CLASS_HID_b363 = 0xb363,\n+\tBNXT_ULP_CLASS_HID_f5a3 = 0xf5a3,\n+\tBNXT_ULP_CLASS_HID_f8e3 = 0xf8e3,\n+\tBNXT_ULP_CLASS_HID_abd7 = 0xabd7,\n+\tBNXT_ULP_CLASS_HID_ae17 = 0xae17,\n+\tBNXT_ULP_CLASS_HID_f157 = 0xf157,\n+\tBNXT_ULP_CLASS_HID_f397 = 0xf397,\n+\tBNXT_ULP_CLASS_HID_1c1d7 = 0x1c1d7,\n+\tBNXT_ULP_CLASS_HID_1e417 = 0x1e417,\n+\tBNXT_ULP_CLASS_HID_1c757 = 0x1c757,\n+\tBNXT_ULP_CLASS_HID_1e997 = 0x1e997,\n+\tBNXT_ULP_CLASS_HID_1c623 = 0x1c623,\n+\tBNXT_ULP_CLASS_HID_1e963 = 0x1e963,\n+\tBNXT_ULP_CLASS_HID_1cba3 = 0x1cba3,\n+\tBNXT_ULP_CLASS_HID_1eee3 = 0x1eee3,\n+\tBNXT_ULP_CLASS_HID_d3b7 = 0xd3b7,\n+\tBNXT_ULP_CLASS_HID_f6f7 = 0xf6f7,\n+\tBNXT_ULP_CLASS_HID_d937 = 0xd937,\n+\tBNXT_ULP_CLASS_HID_fc77 = 0xfc77,\n+\tBNXT_ULP_CLASS_HID_cf7b = 0xcf7b,\n+\tBNXT_ULP_CLASS_HID_f1bb = 0xf1bb,\n+\tBNXT_ULP_CLASS_HID_d4fb = 0xd4fb,\n+\tBNXT_ULP_CLASS_HID_f73b = 0xf73b,\n+\tBNXT_ULP_CLASS_HID_1882f = 0x1882f,\n+\tBNXT_ULP_CLASS_HID_1ab6f = 0x1ab6f,\n+\tBNXT_ULP_CLASS_HID_1cdaf = 0x1cdaf,\n+\tBNXT_ULP_CLASS_HID_1f0ef = 0x1f0ef,\n+\tBNXT_ULP_CLASS_HID_18d7b = 0x18d7b,\n+\tBNXT_ULP_CLASS_HID_1afbb = 0x1afbb,\n+\tBNXT_ULP_CLASS_HID_1d2fb = 0x1d2fb,\n+\tBNXT_ULP_CLASS_HID_1f53b = 0x1f53b,\n+\tBNXT_ULP_CLASS_HID_9a8f = 0x9a8f,\n+\tBNXT_ULP_CLASS_HID_bdcf = 0xbdcf,\n+\tBNXT_ULP_CLASS_HID_e00f = 0xe00f,\n+\tBNXT_ULP_CLASS_HID_e34f = 0xe34f,\n+\tBNXT_ULP_CLASS_HID_95b3 = 0x95b3,\n+\tBNXT_ULP_CLASS_HID_b8f3 = 0xb8f3,\n+\tBNXT_ULP_CLASS_HID_db33 = 0xdb33,\n+\tBNXT_ULP_CLASS_HID_fe73 = 0xfe73,\n+\tBNXT_ULP_CLASS_HID_1abb3 = 0x1abb3,\n+\tBNXT_ULP_CLASS_HID_1aef3 = 0x1aef3,\n+\tBNXT_ULP_CLASS_HID_1f133 = 0x1f133,\n+\tBNXT_ULP_CLASS_HID_1f473 = 0x1f473,\n+\tBNXT_ULP_CLASS_HID_1b08f = 0x1b08f,\n+\tBNXT_ULP_CLASS_HID_1b3cf = 0x1b3cf,\n+\tBNXT_ULP_CLASS_HID_1f60f = 0x1f60f,\n+\tBNXT_ULP_CLASS_HID_1f94f = 0x1f94f,\n+\tBNXT_ULP_CLASS_HID_be13 = 0xbe13,\n+\tBNXT_ULP_CLASS_HID_e153 = 0xe153,\n+\tBNXT_ULP_CLASS_HID_c393 = 0xc393,\n+\tBNXT_ULP_CLASS_HID_e6d3 = 0xe6d3,\n+\tBNXT_ULP_CLASS_HID_b9c7 = 0xb9c7,\n+\tBNXT_ULP_CLASS_HID_bc07 = 0xbc07,\n+\tBNXT_ULP_CLASS_HID_ff47 = 0xff47,\n+\tBNXT_ULP_CLASS_HID_e187 = 0xe187,\n+\tBNXT_ULP_CLASS_HID_1cfc7 = 0x1cfc7,\n+\tBNXT_ULP_CLASS_HID_1f207 = 0x1f207,\n+\tBNXT_ULP_CLASS_HID_1d547 = 0x1d547,\n+\tBNXT_ULP_CLASS_HID_1f787 = 0x1f787,\n+\tBNXT_ULP_CLASS_HID_1d413 = 0x1d413,\n+\tBNXT_ULP_CLASS_HID_1f753 = 0x1f753,\n+\tBNXT_ULP_CLASS_HID_1d993 = 0x1d993,\n+\tBNXT_ULP_CLASS_HID_1fcd3 = 0x1fcd3,\n+\tBNXT_ULP_CLASS_HID_aa67 = 0xaa67,\n+\tBNXT_ULP_CLASS_HID_aca7 = 0xaca7,\n+\tBNXT_ULP_CLASS_HID_efe7 = 0xefe7,\n+\tBNXT_ULP_CLASS_HID_f227 = 0xf227,\n+\tBNXT_ULP_CLASS_HID_a52b = 0xa52b,\n+\tBNXT_ULP_CLASS_HID_a86b = 0xa86b,\n+\tBNXT_ULP_CLASS_HID_eaab = 0xeaab,\n+\tBNXT_ULP_CLASS_HID_edeb = 0xedeb,\n+\tBNXT_ULP_CLASS_HID_1bb2b = 0x1bb2b,\n+\tBNXT_ULP_CLASS_HID_1be6b = 0x1be6b,\n+\tBNXT_ULP_CLASS_HID_1c0ab = 0x1c0ab,\n+\tBNXT_ULP_CLASS_HID_1e3eb = 0x1e3eb,\n+\tBNXT_ULP_CLASS_HID_1c067 = 0x1c067,\n+\tBNXT_ULP_CLASS_HID_1e2a7 = 0x1e2a7,\n+\tBNXT_ULP_CLASS_HID_1c5e7 = 0x1c5e7,\n+\tBNXT_ULP_CLASS_HID_1e827 = 0x1e827,\n+\tBNXT_ULP_CLASS_HID_cd8b = 0xcd8b,\n+\tBNXT_ULP_CLASS_HID_f0cb = 0xf0cb,\n+\tBNXT_ULP_CLASS_HID_d30b = 0xd30b,\n+\tBNXT_ULP_CLASS_HID_f64b = 0xf64b,\n+\tBNXT_ULP_CLASS_HID_c8bf = 0xc8bf,\n+\tBNXT_ULP_CLASS_HID_ebff = 0xebff,\n+\tBNXT_ULP_CLASS_HID_ce3f = 0xce3f,\n+\tBNXT_ULP_CLASS_HID_f17f = 0xf17f,\n+\tBNXT_ULP_CLASS_HID_18263 = 0x18263,\n+\tBNXT_ULP_CLASS_HID_1a4a3 = 0x1a4a3,\n+\tBNXT_ULP_CLASS_HID_1c7e3 = 0x1c7e3,\n+\tBNXT_ULP_CLASS_HID_1ea23 = 0x1ea23,\n+\tBNXT_ULP_CLASS_HID_186bf = 0x186bf,\n+\tBNXT_ULP_CLASS_HID_1a9ff = 0x1a9ff,\n+\tBNXT_ULP_CLASS_HID_1cc3f = 0x1cc3f,\n+\tBNXT_ULP_CLASS_HID_1ef7f = 0x1ef7f,\n+\tBNXT_ULP_CLASS_HID_94c3 = 0x94c3,\n+\tBNXT_ULP_CLASS_HID_b703 = 0xb703,\n+\tBNXT_ULP_CLASS_HID_da43 = 0xda43,\n+\tBNXT_ULP_CLASS_HID_fc83 = 0xfc83,\n+\tBNXT_ULP_CLASS_HID_8ff7 = 0x8ff7,\n+\tBNXT_ULP_CLASS_HID_b237 = 0xb237,\n+\tBNXT_ULP_CLASS_HID_d577 = 0xd577,\n+\tBNXT_ULP_CLASS_HID_f7b7 = 0xf7b7,\n+\tBNXT_ULP_CLASS_HID_1a5f7 = 0x1a5f7,\n+\tBNXT_ULP_CLASS_HID_1a837 = 0x1a837,\n+\tBNXT_ULP_CLASS_HID_1eb77 = 0x1eb77,\n+\tBNXT_ULP_CLASS_HID_1edb7 = 0x1edb7,\n+\tBNXT_ULP_CLASS_HID_1aac3 = 0x1aac3,\n+\tBNXT_ULP_CLASS_HID_1ad03 = 0x1ad03,\n+\tBNXT_ULP_CLASS_HID_1f043 = 0x1f043,\n+\tBNXT_ULP_CLASS_HID_1f283 = 0x1f283,\n+\tBNXT_ULP_CLASS_HID_b857 = 0xb857,\n+\tBNXT_ULP_CLASS_HID_ba97 = 0xba97,\n+\tBNXT_ULP_CLASS_HID_fdd7 = 0xfdd7,\n+\tBNXT_ULP_CLASS_HID_e017 = 0xe017,\n+\tBNXT_ULP_CLASS_HID_b31b = 0xb31b,\n+\tBNXT_ULP_CLASS_HID_b65b = 0xb65b,\n+\tBNXT_ULP_CLASS_HID_f89b = 0xf89b,\n+\tBNXT_ULP_CLASS_HID_fbdb = 0xfbdb,\n+\tBNXT_ULP_CLASS_HID_1c91b = 0x1c91b,\n+\tBNXT_ULP_CLASS_HID_1ec5b = 0x1ec5b,\n+\tBNXT_ULP_CLASS_HID_1ce9b = 0x1ce9b,\n+\tBNXT_ULP_CLASS_HID_1f1db = 0x1f1db,\n+\tBNXT_ULP_CLASS_HID_1ce57 = 0x1ce57,\n+\tBNXT_ULP_CLASS_HID_1f097 = 0x1f097,\n+\tBNXT_ULP_CLASS_HID_1d3d7 = 0x1d3d7,\n+\tBNXT_ULP_CLASS_HID_1f617 = 0x1f617,\n+\tBNXT_ULP_CLASS_HID_a3bb = 0xa3bb,\n+\tBNXT_ULP_CLASS_HID_a6fb = 0xa6fb,\n+\tBNXT_ULP_CLASS_HID_e93b = 0xe93b,\n+\tBNXT_ULP_CLASS_HID_ec7b = 0xec7b,\n+\tBNXT_ULP_CLASS_HID_9f6f = 0x9f6f,\n+\tBNXT_ULP_CLASS_HID_a1af = 0xa1af,\n+\tBNXT_ULP_CLASS_HID_e4ef = 0xe4ef,\n+\tBNXT_ULP_CLASS_HID_e72f = 0xe72f,\n+\tBNXT_ULP_CLASS_HID_1b56f = 0x1b56f,\n+\tBNXT_ULP_CLASS_HID_1b7af = 0x1b7af,\n+\tBNXT_ULP_CLASS_HID_1faef = 0x1faef,\n+\tBNXT_ULP_CLASS_HID_1fd2f = 0x1fd2f,\n+\tBNXT_ULP_CLASS_HID_1b9bb = 0x1b9bb,\n+\tBNXT_ULP_CLASS_HID_1bcfb = 0x1bcfb,\n+\tBNXT_ULP_CLASS_HID_1ff3b = 0x1ff3b,\n+\tBNXT_ULP_CLASS_HID_1e27b = 0x1e27b,\n+\tBNXT_ULP_CLASS_HID_c7cf = 0xc7cf,\n+\tBNXT_ULP_CLASS_HID_ea0f = 0xea0f,\n+\tBNXT_ULP_CLASS_HID_cd4f = 0xcd4f,\n+\tBNXT_ULP_CLASS_HID_ef8f = 0xef8f,\n+\tBNXT_ULP_CLASS_HID_c2f3 = 0xc2f3,\n+\tBNXT_ULP_CLASS_HID_e533 = 0xe533,\n+\tBNXT_ULP_CLASS_HID_c873 = 0xc873,\n+\tBNXT_ULP_CLASS_HID_eab3 = 0xeab3,\n+\tBNXT_ULP_CLASS_HID_1d8f3 = 0x1d8f3,\n+\tBNXT_ULP_CLASS_HID_1fb33 = 0x1fb33,\n+\tBNXT_ULP_CLASS_HID_1c127 = 0x1c127,\n+\tBNXT_ULP_CLASS_HID_1e467 = 0x1e467,\n+\tBNXT_ULP_CLASS_HID_180f3 = 0x180f3,\n+\tBNXT_ULP_CLASS_HID_1a333 = 0x1a333,\n+\tBNXT_ULP_CLASS_HID_1c673 = 0x1c673,\n+\tBNXT_ULP_CLASS_HID_1e8b3 = 0x1e8b3,\n+\tBNXT_ULP_CLASS_HID_8e07 = 0x8e07,\n+\tBNXT_ULP_CLASS_HID_b147 = 0xb147,\n+\tBNXT_ULP_CLASS_HID_d387 = 0xd387,\n+\tBNXT_ULP_CLASS_HID_f6c7 = 0xf6c7,\n+\tBNXT_ULP_CLASS_HID_89cb = 0x89cb,\n+\tBNXT_ULP_CLASS_HID_ac0b = 0xac0b,\n+\tBNXT_ULP_CLASS_HID_cf4b = 0xcf4b,\n+\tBNXT_ULP_CLASS_HID_f18b = 0xf18b,\n+\tBNXT_ULP_CLASS_HID_19fcb = 0x19fcb,\n+\tBNXT_ULP_CLASS_HID_1a20b = 0x1a20b,\n+\tBNXT_ULP_CLASS_HID_1e54b = 0x1e54b,\n+\tBNXT_ULP_CLASS_HID_1e78b = 0x1e78b,\n+\tBNXT_ULP_CLASS_HID_1a407 = 0x1a407,\n+\tBNXT_ULP_CLASS_HID_1a747 = 0x1a747,\n+\tBNXT_ULP_CLASS_HID_1e987 = 0x1e987,\n+\tBNXT_ULP_CLASS_HID_1ecc7 = 0x1ecc7,\n+\tBNXT_ULP_CLASS_HID_b1ab = 0xb1ab,\n+\tBNXT_ULP_CLASS_HID_b4eb = 0xb4eb,\n+\tBNXT_ULP_CLASS_HID_f72b = 0xf72b,\n+\tBNXT_ULP_CLASS_HID_fa6b = 0xfa6b,\n+\tBNXT_ULP_CLASS_HID_ad5f = 0xad5f,\n+\tBNXT_ULP_CLASS_HID_af9f = 0xaf9f,\n+\tBNXT_ULP_CLASS_HID_f2df = 0xf2df,\n+\tBNXT_ULP_CLASS_HID_f51f = 0xf51f,\n+\tBNXT_ULP_CLASS_HID_1c35f = 0x1c35f,\n+\tBNXT_ULP_CLASS_HID_1e59f = 0x1e59f,\n+\tBNXT_ULP_CLASS_HID_1c8df = 0x1c8df,\n+\tBNXT_ULP_CLASS_HID_1eb1f = 0x1eb1f,\n+\tBNXT_ULP_CLASS_HID_1c7ab = 0x1c7ab,\n+\tBNXT_ULP_CLASS_HID_1eaeb = 0x1eaeb,\n+\tBNXT_ULP_CLASS_HID_1cd2b = 0x1cd2b,\n+\tBNXT_ULP_CLASS_HID_1f06b = 0x1f06b,\n+\tBNXT_ULP_CLASS_HID_9177 = 0x9177,\n+\tBNXT_ULP_CLASS_HID_b3b7 = 0xb3b7,\n+\tBNXT_ULP_CLASS_HID_d6f7 = 0xd6f7,\n+\tBNXT_ULP_CLASS_HID_f937 = 0xf937,\n+\tBNXT_ULP_CLASS_HID_8c3b = 0x8c3b,\n+\tBNXT_ULP_CLASS_HID_af7b = 0xaf7b,\n+\tBNXT_ULP_CLASS_HID_d1bb = 0xd1bb,\n+\tBNXT_ULP_CLASS_HID_f4fb = 0xf4fb,\n+\tBNXT_ULP_CLASS_HID_1a23b = 0x1a23b,\n+\tBNXT_ULP_CLASS_HID_1a57b = 0x1a57b,\n+\tBNXT_ULP_CLASS_HID_1e7bb = 0x1e7bb,\n+\tBNXT_ULP_CLASS_HID_1eafb = 0x1eafb,\n+\tBNXT_ULP_CLASS_HID_1a777 = 0x1a777,\n+\tBNXT_ULP_CLASS_HID_1a9b7 = 0x1a9b7,\n+\tBNXT_ULP_CLASS_HID_1ecf7 = 0x1ecf7,\n+\tBNXT_ULP_CLASS_HID_1ef37 = 0x1ef37,\n+\tBNXT_ULP_CLASS_HID_b49b = 0xb49b,\n+\tBNXT_ULP_CLASS_HID_b7db = 0xb7db,\n+\tBNXT_ULP_CLASS_HID_fa1b = 0xfa1b,\n+\tBNXT_ULP_CLASS_HID_fd5b = 0xfd5b,\n+\tBNXT_ULP_CLASS_HID_b04f = 0xb04f,\n+\tBNXT_ULP_CLASS_HID_b28f = 0xb28f,\n+\tBNXT_ULP_CLASS_HID_f5cf = 0xf5cf,\n+\tBNXT_ULP_CLASS_HID_f80f = 0xf80f,\n+\tBNXT_ULP_CLASS_HID_1c64f = 0x1c64f,\n+\tBNXT_ULP_CLASS_HID_1e88f = 0x1e88f,\n+\tBNXT_ULP_CLASS_HID_1cbcf = 0x1cbcf,\n+\tBNXT_ULP_CLASS_HID_1ee0f = 0x1ee0f,\n+\tBNXT_ULP_CLASS_HID_1ca9b = 0x1ca9b,\n+\tBNXT_ULP_CLASS_HID_1eddb = 0x1eddb,\n+\tBNXT_ULP_CLASS_HID_1d01b = 0x1d01b,\n+\tBNXT_ULP_CLASS_HID_1f35b = 0x1f35b,\n+\tBNXT_ULP_CLASS_HID_8b4b = 0x8b4b,\n+\tBNXT_ULP_CLASS_HID_ad8b = 0xad8b,\n+\tBNXT_ULP_CLASS_HID_d0cb = 0xd0cb,\n+\tBNXT_ULP_CLASS_HID_f30b = 0xf30b,\n+\tBNXT_ULP_CLASS_HID_867f = 0x867f,\n+\tBNXT_ULP_CLASS_HID_a8bf = 0xa8bf,\n+\tBNXT_ULP_CLASS_HID_cbff = 0xcbff,\n+\tBNXT_ULP_CLASS_HID_ee3f = 0xee3f,\n+\tBNXT_ULP_CLASS_HID_19c7f = 0x19c7f,\n+\tBNXT_ULP_CLASS_HID_1bebf = 0x1bebf,\n+\tBNXT_ULP_CLASS_HID_1e1ff = 0x1e1ff,\n+\tBNXT_ULP_CLASS_HID_1e43f = 0x1e43f,\n+\tBNXT_ULP_CLASS_HID_1a14b = 0x1a14b,\n+\tBNXT_ULP_CLASS_HID_1a38b = 0x1a38b,\n+\tBNXT_ULP_CLASS_HID_1e6cb = 0x1e6cb,\n+\tBNXT_ULP_CLASS_HID_1e90b = 0x1e90b,\n+\tBNXT_ULP_CLASS_HID_aedf = 0xaedf,\n+\tBNXT_ULP_CLASS_HID_b11f = 0xb11f,\n+\tBNXT_ULP_CLASS_HID_f45f = 0xf45f,\n+\tBNXT_ULP_CLASS_HID_f69f = 0xf69f,\n+\tBNXT_ULP_CLASS_HID_a983 = 0xa983,\n+\tBNXT_ULP_CLASS_HID_acc3 = 0xacc3,\n+\tBNXT_ULP_CLASS_HID_ef03 = 0xef03,\n+\tBNXT_ULP_CLASS_HID_f243 = 0xf243,\n+\tBNXT_ULP_CLASS_HID_1bf83 = 0x1bf83,\n+\tBNXT_ULP_CLASS_HID_1e2c3 = 0x1e2c3,\n+\tBNXT_ULP_CLASS_HID_1c503 = 0x1c503,\n+\tBNXT_ULP_CLASS_HID_1e843 = 0x1e843,\n+\tBNXT_ULP_CLASS_HID_1c4df = 0x1c4df,\n+\tBNXT_ULP_CLASS_HID_1e71f = 0x1e71f,\n+\tBNXT_ULP_CLASS_HID_1ca5f = 0x1ca5f,\n+\tBNXT_ULP_CLASS_HID_1ec9f = 0x1ec9f,\n+\tBNXT_ULP_CLASS_HID_2523 = 0x2523,\n+\tBNXT_ULP_CLASS_HID_2bef = 0x2bef,\n+\tBNXT_ULP_CLASS_HID_4f73 = 0x4f73,\n+\tBNXT_ULP_CLASS_HID_164b = 0x164b,\n+\tBNXT_ULP_CLASS_HID_39df = 0x39df,\n+\tBNXT_ULP_CLASS_HID_48b7 = 0x48b7,\n+\tBNXT_ULP_CLASS_HID_0f8f = 0x0f8f,\n+\tBNXT_ULP_CLASS_HID_3313 = 0x3313,\n+\tBNXT_ULP_CLASS_HID_257b7 = 0x257b7,\n+\tBNXT_ULP_CLASS_HID_24467 = 0x24467,\n+\tBNXT_ULP_CLASS_HID_23fbb = 0x23fbb,\n+\tBNXT_ULP_CLASS_HID_252cb = 0x252cb,\n+\tBNXT_ULP_CLASS_HID_21e7f = 0x21e7f,\n+\tBNXT_ULP_CLASS_HID_20b2f = 0x20b2f,\n+\tBNXT_ULP_CLASS_HID_20663 = 0x20663,\n+\tBNXT_ULP_CLASS_HID_219b3 = 0x219b3,\n+\tBNXT_ULP_CLASS_HID_24213 = 0x24213,\n+\tBNXT_ULP_CLASS_HID_22ec3 = 0x22ec3,\n+\tBNXT_ULP_CLASS_HID_22a17 = 0x22a17,\n+\tBNXT_ULP_CLASS_HID_23d27 = 0x23d27,\n+\tBNXT_ULP_CLASS_HID_208db = 0x208db,\n+\tBNXT_ULP_CLASS_HID_25277 = 0x25277,\n+\tBNXT_ULP_CLASS_HID_24d8b = 0x24d8b,\n+\tBNXT_ULP_CLASS_HID_203ef = 0x203ef,\n+\tBNXT_ULP_CLASS_HID_2517b = 0x2517b,\n+\tBNXT_ULP_CLASS_HID_23e2b = 0x23e2b,\n+\tBNXT_ULP_CLASS_HID_2397f = 0x2397f,\n+\tBNXT_ULP_CLASS_HID_24c8f = 0x24c8f,\n+\tBNXT_ULP_CLASS_HID_21823 = 0x21823,\n+\tBNXT_ULP_CLASS_HID_20513 = 0x20513,\n+\tBNXT_ULP_CLASS_HID_20027 = 0x20027,\n+\tBNXT_ULP_CLASS_HID_21377 = 0x21377,\n+\tBNXT_ULP_CLASS_HID_23bd7 = 0x23bd7,\n+\tBNXT_ULP_CLASS_HID_22887 = 0x22887,\n+\tBNXT_ULP_CLASS_HID_223db = 0x223db,\n+\tBNXT_ULP_CLASS_HID_236eb = 0x236eb,\n+\tBNXT_ULP_CLASS_HID_2029f = 0x2029f,\n+\tBNXT_ULP_CLASS_HID_24c3b = 0x24c3b,\n+\tBNXT_ULP_CLASS_HID_2474f = 0x2474f,\n+\tBNXT_ULP_CLASS_HID_25a9f = 0x25a9f,\n+\tBNXT_ULP_CLASS_HID_24b3f = 0x24b3f,\n+\tBNXT_ULP_CLASS_HID_237ef = 0x237ef,\n+\tBNXT_ULP_CLASS_HID_23323 = 0x23323,\n+\tBNXT_ULP_CLASS_HID_24673 = 0x24673,\n+\tBNXT_ULP_CLASS_HID_211e7 = 0x211e7,\n+\tBNXT_ULP_CLASS_HID_25b83 = 0x25b83,\n+\tBNXT_ULP_CLASS_HID_256d7 = 0x256d7,\n+\tBNXT_ULP_CLASS_HID_20d3b = 0x20d3b,\n+\tBNXT_ULP_CLASS_HID_2359b = 0x2359b,\n+\tBNXT_ULP_CLASS_HID_2224b = 0x2224b,\n+\tBNXT_ULP_CLASS_HID_21d9f = 0x21d9f,\n+\tBNXT_ULP_CLASS_HID_230af = 0x230af,\n+\tBNXT_ULP_CLASS_HID_2590f = 0x2590f,\n+\tBNXT_ULP_CLASS_HID_245ff = 0x245ff,\n+\tBNXT_ULP_CLASS_HID_24133 = 0x24133,\n+\tBNXT_ULP_CLASS_HID_25443 = 0x25443,\n+\tBNXT_ULP_CLASS_HID_244e3 = 0x244e3,\n+\tBNXT_ULP_CLASS_HID_231d3 = 0x231d3,\n+\tBNXT_ULP_CLASS_HID_22ce7 = 0x22ce7,\n+\tBNXT_ULP_CLASS_HID_24037 = 0x24037,\n+\tBNXT_ULP_CLASS_HID_20bab = 0x20bab,\n+\tBNXT_ULP_CLASS_HID_25547 = 0x25547,\n+\tBNXT_ULP_CLASS_HID_2509b = 0x2509b,\n+\tBNXT_ULP_CLASS_HID_206ff = 0x206ff,\n+\tBNXT_ULP_CLASS_HID_22f5f = 0x22f5f,\n+\tBNXT_ULP_CLASS_HID_21c0f = 0x21c0f,\n+\tBNXT_ULP_CLASS_HID_21743 = 0x21743,\n+\tBNXT_ULP_CLASS_HID_22a93 = 0x22a93,\n+\tBNXT_ULP_CLASS_HID_252f3 = 0x252f3,\n+\tBNXT_ULP_CLASS_HID_23fa3 = 0x23fa3,\n+\tBNXT_ULP_CLASS_HID_23af7 = 0x23af7,\n+\tBNXT_ULP_CLASS_HID_24e07 = 0x24e07,\n+\tBNXT_ULP_CLASS_HID_2322f = 0x2322f,\n+\tBNXT_ULP_CLASS_HID_21f1f = 0x21f1f,\n+\tBNXT_ULP_CLASS_HID_21a53 = 0x21a53,\n+\tBNXT_ULP_CLASS_HID_22d63 = 0x22d63,\n+\tBNXT_ULP_CLASS_HID_255c3 = 0x255c3,\n+\tBNXT_ULP_CLASS_HID_242b3 = 0x242b3,\n+\tBNXT_ULP_CLASS_HID_23dc7 = 0x23dc7,\n+\tBNXT_ULP_CLASS_HID_25117 = 0x25117,\n+\tBNXT_ULP_CLASS_HID_22c13 = 0x22c13,\n+\tBNXT_ULP_CLASS_HID_218c3 = 0x218c3,\n+\tBNXT_ULP_CLASS_HID_21417 = 0x21417,\n+\tBNXT_ULP_CLASS_HID_22727 = 0x22727,\n+\tBNXT_ULP_CLASS_HID_24f87 = 0x24f87,\n+\tBNXT_ULP_CLASS_HID_23c77 = 0x23c77,\n+\tBNXT_ULP_CLASS_HID_2378b = 0x2378b,\n+\tBNXT_ULP_CLASS_HID_24adb = 0x24adb,\n+\tBNXT_ULP_CLASS_HID_257b = 0x257b,\n+\tBNXT_ULP_CLASS_HID_2bb7 = 0x2bb7,\n+\tBNXT_ULP_CLASS_HID_4f2b = 0x4f2b,\n+\tBNXT_ULP_CLASS_HID_1613 = 0x1613,\n+\tBNXT_ULP_CLASS_HID_3987 = 0x3987,\n+\tBNXT_ULP_CLASS_HID_48ef = 0x48ef,\n+\tBNXT_ULP_CLASS_HID_0fd7 = 0x0fd7,\n+\tBNXT_ULP_CLASS_HID_334b = 0x334b,\n+\tBNXT_ULP_CLASS_HID_25797 = 0x25797,\n+\tBNXT_ULP_CLASS_HID_285eb = 0x285eb,\n+\tBNXT_ULP_CLASS_HID_310eb = 0x310eb,\n+\tBNXT_ULP_CLASS_HID_39beb = 0x39beb,\n+\tBNXT_ULP_CLASS_HID_24447 = 0x24447,\n+\tBNXT_ULP_CLASS_HID_2cf47 = 0x2cf47,\n+\tBNXT_ULP_CLASS_HID_35a47 = 0x35a47,\n+\tBNXT_ULP_CLASS_HID_3889b = 0x3889b,\n+\tBNXT_ULP_CLASS_HID_23f9b = 0x23f9b,\n+\tBNXT_ULP_CLASS_HID_2ca9b = 0x2ca9b,\n+\tBNXT_ULP_CLASS_HID_3559b = 0x3559b,\n+\tBNXT_ULP_CLASS_HID_383ef = 0x383ef,\n+\tBNXT_ULP_CLASS_HID_252eb = 0x252eb,\n+\tBNXT_ULP_CLASS_HID_2813f = 0x2813f,\n+\tBNXT_ULP_CLASS_HID_30c3f = 0x30c3f,\n+\tBNXT_ULP_CLASS_HID_3973f = 0x3973f,\n+\tBNXT_ULP_CLASS_HID_21e5f = 0x21e5f,\n+\tBNXT_ULP_CLASS_HID_2a95f = 0x2a95f,\n+\tBNXT_ULP_CLASS_HID_3345f = 0x3345f,\n+\tBNXT_ULP_CLASS_HID_3bf5f = 0x3bf5f,\n+\tBNXT_ULP_CLASS_HID_20b0f = 0x20b0f,\n+\tBNXT_ULP_CLASS_HID_2960f = 0x2960f,\n+\tBNXT_ULP_CLASS_HID_3210f = 0x3210f,\n+\tBNXT_ULP_CLASS_HID_3ac0f = 0x3ac0f,\n+\tBNXT_ULP_CLASS_HID_20643 = 0x20643,\n+\tBNXT_ULP_CLASS_HID_29143 = 0x29143,\n+\tBNXT_ULP_CLASS_HID_31c43 = 0x31c43,\n+\tBNXT_ULP_CLASS_HID_3a743 = 0x3a743,\n+\tBNXT_ULP_CLASS_HID_21993 = 0x21993,\n+\tBNXT_ULP_CLASS_HID_2a493 = 0x2a493,\n+\tBNXT_ULP_CLASS_HID_32f93 = 0x32f93,\n+\tBNXT_ULP_CLASS_HID_3ba93 = 0x3ba93,\n+\tBNXT_ULP_CLASS_HID_24233 = 0x24233,\n+\tBNXT_ULP_CLASS_HID_2cd33 = 0x2cd33,\n+\tBNXT_ULP_CLASS_HID_35833 = 0x35833,\n+\tBNXT_ULP_CLASS_HID_38607 = 0x38607,\n+\tBNXT_ULP_CLASS_HID_22ee3 = 0x22ee3,\n+\tBNXT_ULP_CLASS_HID_2b9e3 = 0x2b9e3,\n+\tBNXT_ULP_CLASS_HID_344e3 = 0x344e3,\n+\tBNXT_ULP_CLASS_HID_3cfe3 = 0x3cfe3,\n+\tBNXT_ULP_CLASS_HID_22a37 = 0x22a37,\n+\tBNXT_ULP_CLASS_HID_2b537 = 0x2b537,\n+\tBNXT_ULP_CLASS_HID_34037 = 0x34037,\n+\tBNXT_ULP_CLASS_HID_3cb37 = 0x3cb37,\n+\tBNXT_ULP_CLASS_HID_23d07 = 0x23d07,\n+\tBNXT_ULP_CLASS_HID_2c807 = 0x2c807,\n+\tBNXT_ULP_CLASS_HID_35307 = 0x35307,\n+\tBNXT_ULP_CLASS_HID_3815b = 0x3815b,\n+\tBNXT_ULP_CLASS_HID_208fb = 0x208fb,\n+\tBNXT_ULP_CLASS_HID_293fb = 0x293fb,\n+\tBNXT_ULP_CLASS_HID_31efb = 0x31efb,\n+\tBNXT_ULP_CLASS_HID_3a9fb = 0x3a9fb,\n+\tBNXT_ULP_CLASS_HID_25257 = 0x25257,\n+\tBNXT_ULP_CLASS_HID_280ab = 0x280ab,\n+\tBNXT_ULP_CLASS_HID_30bab = 0x30bab,\n+\tBNXT_ULP_CLASS_HID_396ab = 0x396ab,\n+\tBNXT_ULP_CLASS_HID_24dab = 0x24dab,\n+\tBNXT_ULP_CLASS_HID_2d8ab = 0x2d8ab,\n+\tBNXT_ULP_CLASS_HID_306ff = 0x306ff,\n+\tBNXT_ULP_CLASS_HID_391ff = 0x391ff,\n+\tBNXT_ULP_CLASS_HID_203cf = 0x203cf,\n+\tBNXT_ULP_CLASS_HID_28ecf = 0x28ecf,\n+\tBNXT_ULP_CLASS_HID_319cf = 0x319cf,\n+\tBNXT_ULP_CLASS_HID_3a4cf = 0x3a4cf,\n+\tBNXT_ULP_CLASS_HID_2515b = 0x2515b,\n+\tBNXT_ULP_CLASS_HID_2dc5b = 0x2dc5b,\n+\tBNXT_ULP_CLASS_HID_30aaf = 0x30aaf,\n+\tBNXT_ULP_CLASS_HID_395af = 0x395af,\n+\tBNXT_ULP_CLASS_HID_23e0b = 0x23e0b,\n+\tBNXT_ULP_CLASS_HID_2c90b = 0x2c90b,\n+\tBNXT_ULP_CLASS_HID_3540b = 0x3540b,\n+\tBNXT_ULP_CLASS_HID_3825f = 0x3825f,\n+\tBNXT_ULP_CLASS_HID_2395f = 0x2395f,\n+\tBNXT_ULP_CLASS_HID_2c45f = 0x2c45f,\n+\tBNXT_ULP_CLASS_HID_34f5f = 0x34f5f,\n+\tBNXT_ULP_CLASS_HID_3da5f = 0x3da5f,\n+\tBNXT_ULP_CLASS_HID_24caf = 0x24caf,\n+\tBNXT_ULP_CLASS_HID_2d7af = 0x2d7af,\n+\tBNXT_ULP_CLASS_HID_305e3 = 0x305e3,\n+\tBNXT_ULP_CLASS_HID_390e3 = 0x390e3,\n+\tBNXT_ULP_CLASS_HID_21803 = 0x21803,\n+\tBNXT_ULP_CLASS_HID_2a303 = 0x2a303,\n+\tBNXT_ULP_CLASS_HID_32e03 = 0x32e03,\n+\tBNXT_ULP_CLASS_HID_3b903 = 0x3b903,\n+\tBNXT_ULP_CLASS_HID_20533 = 0x20533,\n+\tBNXT_ULP_CLASS_HID_29033 = 0x29033,\n+\tBNXT_ULP_CLASS_HID_31b33 = 0x31b33,\n+\tBNXT_ULP_CLASS_HID_3a633 = 0x3a633,\n+\tBNXT_ULP_CLASS_HID_20007 = 0x20007,\n+\tBNXT_ULP_CLASS_HID_28b07 = 0x28b07,\n+\tBNXT_ULP_CLASS_HID_31607 = 0x31607,\n+\tBNXT_ULP_CLASS_HID_3a107 = 0x3a107,\n+\tBNXT_ULP_CLASS_HID_21357 = 0x21357,\n+\tBNXT_ULP_CLASS_HID_29e57 = 0x29e57,\n+\tBNXT_ULP_CLASS_HID_32957 = 0x32957,\n+\tBNXT_ULP_CLASS_HID_3b457 = 0x3b457,\n+\tBNXT_ULP_CLASS_HID_23bf7 = 0x23bf7,\n+\tBNXT_ULP_CLASS_HID_2c6f7 = 0x2c6f7,\n+\tBNXT_ULP_CLASS_HID_351f7 = 0x351f7,\n+\tBNXT_ULP_CLASS_HID_3dcf7 = 0x3dcf7,\n+\tBNXT_ULP_CLASS_HID_228a7 = 0x228a7,\n+\tBNXT_ULP_CLASS_HID_2b3a7 = 0x2b3a7,\n+\tBNXT_ULP_CLASS_HID_33ea7 = 0x33ea7,\n+\tBNXT_ULP_CLASS_HID_3c9a7 = 0x3c9a7,\n+\tBNXT_ULP_CLASS_HID_223fb = 0x223fb,\n+\tBNXT_ULP_CLASS_HID_2aefb = 0x2aefb,\n+\tBNXT_ULP_CLASS_HID_339fb = 0x339fb,\n+\tBNXT_ULP_CLASS_HID_3c4fb = 0x3c4fb,\n+\tBNXT_ULP_CLASS_HID_236cb = 0x236cb,\n+\tBNXT_ULP_CLASS_HID_2c1cb = 0x2c1cb,\n+\tBNXT_ULP_CLASS_HID_34ccb = 0x34ccb,\n+\tBNXT_ULP_CLASS_HID_3d7cb = 0x3d7cb,\n+\tBNXT_ULP_CLASS_HID_202bf = 0x202bf,\n+\tBNXT_ULP_CLASS_HID_28dbf = 0x28dbf,\n+\tBNXT_ULP_CLASS_HID_318bf = 0x318bf,\n+\tBNXT_ULP_CLASS_HID_3a3bf = 0x3a3bf,\n+\tBNXT_ULP_CLASS_HID_24c1b = 0x24c1b,\n+\tBNXT_ULP_CLASS_HID_2d71b = 0x2d71b,\n+\tBNXT_ULP_CLASS_HID_3056f = 0x3056f,\n+\tBNXT_ULP_CLASS_HID_3906f = 0x3906f,\n+\tBNXT_ULP_CLASS_HID_2476f = 0x2476f,\n+\tBNXT_ULP_CLASS_HID_2d26f = 0x2d26f,\n+\tBNXT_ULP_CLASS_HID_300a3 = 0x300a3,\n+\tBNXT_ULP_CLASS_HID_38ba3 = 0x38ba3,\n+\tBNXT_ULP_CLASS_HID_25abf = 0x25abf,\n+\tBNXT_ULP_CLASS_HID_288f3 = 0x288f3,\n+\tBNXT_ULP_CLASS_HID_313f3 = 0x313f3,\n+\tBNXT_ULP_CLASS_HID_39ef3 = 0x39ef3,\n+\tBNXT_ULP_CLASS_HID_24b1f = 0x24b1f,\n+\tBNXT_ULP_CLASS_HID_2d61f = 0x2d61f,\n+\tBNXT_ULP_CLASS_HID_30453 = 0x30453,\n+\tBNXT_ULP_CLASS_HID_38f53 = 0x38f53,\n+\tBNXT_ULP_CLASS_HID_237cf = 0x237cf,\n+\tBNXT_ULP_CLASS_HID_2c2cf = 0x2c2cf,\n+\tBNXT_ULP_CLASS_HID_34dcf = 0x34dcf,\n+\tBNXT_ULP_CLASS_HID_3d8cf = 0x3d8cf,\n+\tBNXT_ULP_CLASS_HID_23303 = 0x23303,\n+\tBNXT_ULP_CLASS_HID_2be03 = 0x2be03,\n+\tBNXT_ULP_CLASS_HID_34903 = 0x34903,\n+\tBNXT_ULP_CLASS_HID_3d403 = 0x3d403,\n+\tBNXT_ULP_CLASS_HID_24653 = 0x24653,\n+\tBNXT_ULP_CLASS_HID_2d153 = 0x2d153,\n+\tBNXT_ULP_CLASS_HID_35c53 = 0x35c53,\n+\tBNXT_ULP_CLASS_HID_38aa7 = 0x38aa7,\n+\tBNXT_ULP_CLASS_HID_211c7 = 0x211c7,\n+\tBNXT_ULP_CLASS_HID_29cc7 = 0x29cc7,\n+\tBNXT_ULP_CLASS_HID_327c7 = 0x327c7,\n+\tBNXT_ULP_CLASS_HID_3b2c7 = 0x3b2c7,\n+\tBNXT_ULP_CLASS_HID_25ba3 = 0x25ba3,\n+\tBNXT_ULP_CLASS_HID_289f7 = 0x289f7,\n+\tBNXT_ULP_CLASS_HID_314f7 = 0x314f7,\n+\tBNXT_ULP_CLASS_HID_39ff7 = 0x39ff7,\n+\tBNXT_ULP_CLASS_HID_256f7 = 0x256f7,\n+\tBNXT_ULP_CLASS_HID_284cb = 0x284cb,\n+\tBNXT_ULP_CLASS_HID_30fcb = 0x30fcb,\n+\tBNXT_ULP_CLASS_HID_39acb = 0x39acb,\n+\tBNXT_ULP_CLASS_HID_20d1b = 0x20d1b,\n+\tBNXT_ULP_CLASS_HID_2981b = 0x2981b,\n+\tBNXT_ULP_CLASS_HID_3231b = 0x3231b,\n+\tBNXT_ULP_CLASS_HID_3ae1b = 0x3ae1b,\n+\tBNXT_ULP_CLASS_HID_235bb = 0x235bb,\n+\tBNXT_ULP_CLASS_HID_2c0bb = 0x2c0bb,\n+\tBNXT_ULP_CLASS_HID_34bbb = 0x34bbb,\n+\tBNXT_ULP_CLASS_HID_3d6bb = 0x3d6bb,\n+\tBNXT_ULP_CLASS_HID_2226b = 0x2226b,\n+\tBNXT_ULP_CLASS_HID_2ad6b = 0x2ad6b,\n+\tBNXT_ULP_CLASS_HID_3386b = 0x3386b,\n+\tBNXT_ULP_CLASS_HID_3c36b = 0x3c36b,\n+\tBNXT_ULP_CLASS_HID_21dbf = 0x21dbf,\n+\tBNXT_ULP_CLASS_HID_2a8bf = 0x2a8bf,\n+\tBNXT_ULP_CLASS_HID_333bf = 0x333bf,\n+\tBNXT_ULP_CLASS_HID_3bebf = 0x3bebf,\n+\tBNXT_ULP_CLASS_HID_2308f = 0x2308f,\n+\tBNXT_ULP_CLASS_HID_2bb8f = 0x2bb8f,\n+\tBNXT_ULP_CLASS_HID_3468f = 0x3468f,\n+\tBNXT_ULP_CLASS_HID_3d18f = 0x3d18f,\n+\tBNXT_ULP_CLASS_HID_2592f = 0x2592f,\n+\tBNXT_ULP_CLASS_HID_28763 = 0x28763,\n+\tBNXT_ULP_CLASS_HID_31263 = 0x31263,\n+\tBNXT_ULP_CLASS_HID_39d63 = 0x39d63,\n+\tBNXT_ULP_CLASS_HID_245df = 0x245df,\n+\tBNXT_ULP_CLASS_HID_2d0df = 0x2d0df,\n+\tBNXT_ULP_CLASS_HID_35bdf = 0x35bdf,\n+\tBNXT_ULP_CLASS_HID_38a13 = 0x38a13,\n+\tBNXT_ULP_CLASS_HID_24113 = 0x24113,\n+\tBNXT_ULP_CLASS_HID_2cc13 = 0x2cc13,\n+\tBNXT_ULP_CLASS_HID_35713 = 0x35713,\n+\tBNXT_ULP_CLASS_HID_38567 = 0x38567,\n+\tBNXT_ULP_CLASS_HID_25463 = 0x25463,\n+\tBNXT_ULP_CLASS_HID_282b7 = 0x282b7,\n+\tBNXT_ULP_CLASS_HID_30db7 = 0x30db7,\n+\tBNXT_ULP_CLASS_HID_398b7 = 0x398b7,\n+\tBNXT_ULP_CLASS_HID_244c3 = 0x244c3,\n+\tBNXT_ULP_CLASS_HID_2cfc3 = 0x2cfc3,\n+\tBNXT_ULP_CLASS_HID_35ac3 = 0x35ac3,\n+\tBNXT_ULP_CLASS_HID_38917 = 0x38917,\n+\tBNXT_ULP_CLASS_HID_231f3 = 0x231f3,\n+\tBNXT_ULP_CLASS_HID_2bcf3 = 0x2bcf3,\n+\tBNXT_ULP_CLASS_HID_347f3 = 0x347f3,\n+\tBNXT_ULP_CLASS_HID_3d2f3 = 0x3d2f3,\n+\tBNXT_ULP_CLASS_HID_22cc7 = 0x22cc7,\n+\tBNXT_ULP_CLASS_HID_2b7c7 = 0x2b7c7,\n+\tBNXT_ULP_CLASS_HID_342c7 = 0x342c7,\n+\tBNXT_ULP_CLASS_HID_3cdc7 = 0x3cdc7,\n+\tBNXT_ULP_CLASS_HID_24017 = 0x24017,\n+\tBNXT_ULP_CLASS_HID_2cb17 = 0x2cb17,\n+\tBNXT_ULP_CLASS_HID_35617 = 0x35617,\n+\tBNXT_ULP_CLASS_HID_3846b = 0x3846b,\n+\tBNXT_ULP_CLASS_HID_20b8b = 0x20b8b,\n+\tBNXT_ULP_CLASS_HID_2968b = 0x2968b,\n+\tBNXT_ULP_CLASS_HID_3218b = 0x3218b,\n+\tBNXT_ULP_CLASS_HID_3ac8b = 0x3ac8b,\n+\tBNXT_ULP_CLASS_HID_25567 = 0x25567,\n+\tBNXT_ULP_CLASS_HID_283bb = 0x283bb,\n+\tBNXT_ULP_CLASS_HID_30ebb = 0x30ebb,\n+\tBNXT_ULP_CLASS_HID_399bb = 0x399bb,\n+\tBNXT_ULP_CLASS_HID_250bb = 0x250bb,\n+\tBNXT_ULP_CLASS_HID_2dbbb = 0x2dbbb,\n+\tBNXT_ULP_CLASS_HID_3098f = 0x3098f,\n+\tBNXT_ULP_CLASS_HID_3948f = 0x3948f,\n+\tBNXT_ULP_CLASS_HID_206df = 0x206df,\n+\tBNXT_ULP_CLASS_HID_291df = 0x291df,\n+\tBNXT_ULP_CLASS_HID_31cdf = 0x31cdf,\n+\tBNXT_ULP_CLASS_HID_3a7df = 0x3a7df,\n+\tBNXT_ULP_CLASS_HID_22f7f = 0x22f7f,\n+\tBNXT_ULP_CLASS_HID_2ba7f = 0x2ba7f,\n+\tBNXT_ULP_CLASS_HID_3457f = 0x3457f,\n+\tBNXT_ULP_CLASS_HID_3d07f = 0x3d07f,\n+\tBNXT_ULP_CLASS_HID_21c2f = 0x21c2f,\n+\tBNXT_ULP_CLASS_HID_2a72f = 0x2a72f,\n+\tBNXT_ULP_CLASS_HID_3322f = 0x3322f,\n+\tBNXT_ULP_CLASS_HID_3bd2f = 0x3bd2f,\n+\tBNXT_ULP_CLASS_HID_21763 = 0x21763,\n+\tBNXT_ULP_CLASS_HID_2a263 = 0x2a263,\n+\tBNXT_ULP_CLASS_HID_32d63 = 0x32d63,\n+\tBNXT_ULP_CLASS_HID_3b863 = 0x3b863,\n+\tBNXT_ULP_CLASS_HID_22ab3 = 0x22ab3,\n+\tBNXT_ULP_CLASS_HID_2b5b3 = 0x2b5b3,\n+\tBNXT_ULP_CLASS_HID_340b3 = 0x340b3,\n+\tBNXT_ULP_CLASS_HID_3cbb3 = 0x3cbb3,\n+\tBNXT_ULP_CLASS_HID_252d3 = 0x252d3,\n+\tBNXT_ULP_CLASS_HID_28127 = 0x28127,\n+\tBNXT_ULP_CLASS_HID_30c27 = 0x30c27,\n+\tBNXT_ULP_CLASS_HID_39727 = 0x39727,\n+\tBNXT_ULP_CLASS_HID_23f83 = 0x23f83,\n+\tBNXT_ULP_CLASS_HID_2ca83 = 0x2ca83,\n+\tBNXT_ULP_CLASS_HID_35583 = 0x35583,\n+\tBNXT_ULP_CLASS_HID_383d7 = 0x383d7,\n+\tBNXT_ULP_CLASS_HID_23ad7 = 0x23ad7,\n+\tBNXT_ULP_CLASS_HID_2c5d7 = 0x2c5d7,\n+\tBNXT_ULP_CLASS_HID_350d7 = 0x350d7,\n+\tBNXT_ULP_CLASS_HID_3dbd7 = 0x3dbd7,\n+\tBNXT_ULP_CLASS_HID_24e27 = 0x24e27,\n+\tBNXT_ULP_CLASS_HID_2d927 = 0x2d927,\n+\tBNXT_ULP_CLASS_HID_3077b = 0x3077b,\n+\tBNXT_ULP_CLASS_HID_3927b = 0x3927b,\n+\tBNXT_ULP_CLASS_HID_2320f = 0x2320f,\n+\tBNXT_ULP_CLASS_HID_2bd0f = 0x2bd0f,\n+\tBNXT_ULP_CLASS_HID_3480f = 0x3480f,\n+\tBNXT_ULP_CLASS_HID_3d30f = 0x3d30f,\n+\tBNXT_ULP_CLASS_HID_21f3f = 0x21f3f,\n+\tBNXT_ULP_CLASS_HID_2aa3f = 0x2aa3f,\n+\tBNXT_ULP_CLASS_HID_3353f = 0x3353f,\n+\tBNXT_ULP_CLASS_HID_3c03f = 0x3c03f,\n+\tBNXT_ULP_CLASS_HID_21a73 = 0x21a73,\n+\tBNXT_ULP_CLASS_HID_2a573 = 0x2a573,\n+\tBNXT_ULP_CLASS_HID_33073 = 0x33073,\n+\tBNXT_ULP_CLASS_HID_3bb73 = 0x3bb73,\n+\tBNXT_ULP_CLASS_HID_22d43 = 0x22d43,\n+\tBNXT_ULP_CLASS_HID_2b843 = 0x2b843,\n+\tBNXT_ULP_CLASS_HID_34343 = 0x34343,\n+\tBNXT_ULP_CLASS_HID_3ce43 = 0x3ce43,\n+\tBNXT_ULP_CLASS_HID_255e3 = 0x255e3,\n+\tBNXT_ULP_CLASS_HID_28437 = 0x28437,\n+\tBNXT_ULP_CLASS_HID_30f37 = 0x30f37,\n+\tBNXT_ULP_CLASS_HID_39a37 = 0x39a37,\n+\tBNXT_ULP_CLASS_HID_24293 = 0x24293,\n+\tBNXT_ULP_CLASS_HID_2cd93 = 0x2cd93,\n+\tBNXT_ULP_CLASS_HID_35893 = 0x35893,\n+\tBNXT_ULP_CLASS_HID_386e7 = 0x386e7,\n+\tBNXT_ULP_CLASS_HID_23de7 = 0x23de7,\n+\tBNXT_ULP_CLASS_HID_2c8e7 = 0x2c8e7,\n+\tBNXT_ULP_CLASS_HID_353e7 = 0x353e7,\n+\tBNXT_ULP_CLASS_HID_3823b = 0x3823b,\n+\tBNXT_ULP_CLASS_HID_25137 = 0x25137,\n+\tBNXT_ULP_CLASS_HID_2dc37 = 0x2dc37,\n+\tBNXT_ULP_CLASS_HID_30a0b = 0x30a0b,\n+\tBNXT_ULP_CLASS_HID_3950b = 0x3950b,\n+\tBNXT_ULP_CLASS_HID_22c33 = 0x22c33,\n+\tBNXT_ULP_CLASS_HID_2b733 = 0x2b733,\n+\tBNXT_ULP_CLASS_HID_34233 = 0x34233,\n+\tBNXT_ULP_CLASS_HID_3cd33 = 0x3cd33,\n+\tBNXT_ULP_CLASS_HID_218e3 = 0x218e3,\n+\tBNXT_ULP_CLASS_HID_2a3e3 = 0x2a3e3,\n+\tBNXT_ULP_CLASS_HID_32ee3 = 0x32ee3,\n+\tBNXT_ULP_CLASS_HID_3b9e3 = 0x3b9e3,\n+\tBNXT_ULP_CLASS_HID_21437 = 0x21437,\n+\tBNXT_ULP_CLASS_HID_29f37 = 0x29f37,\n+\tBNXT_ULP_CLASS_HID_32a37 = 0x32a37,\n+\tBNXT_ULP_CLASS_HID_3b537 = 0x3b537,\n+\tBNXT_ULP_CLASS_HID_22707 = 0x22707,\n+\tBNXT_ULP_CLASS_HID_2b207 = 0x2b207,\n+\tBNXT_ULP_CLASS_HID_33d07 = 0x33d07,\n+\tBNXT_ULP_CLASS_HID_3c807 = 0x3c807,\n+\tBNXT_ULP_CLASS_HID_24fa7 = 0x24fa7,\n+\tBNXT_ULP_CLASS_HID_2daa7 = 0x2daa7,\n+\tBNXT_ULP_CLASS_HID_308fb = 0x308fb,\n+\tBNXT_ULP_CLASS_HID_393fb = 0x393fb,\n+\tBNXT_ULP_CLASS_HID_23c57 = 0x23c57,\n+\tBNXT_ULP_CLASS_HID_2c757 = 0x2c757,\n+\tBNXT_ULP_CLASS_HID_35257 = 0x35257,\n+\tBNXT_ULP_CLASS_HID_380ab = 0x380ab,\n+\tBNXT_ULP_CLASS_HID_237ab = 0x237ab,\n+\tBNXT_ULP_CLASS_HID_2c2ab = 0x2c2ab,\n+\tBNXT_ULP_CLASS_HID_34dab = 0x34dab,\n+\tBNXT_ULP_CLASS_HID_3d8ab = 0x3d8ab,\n+\tBNXT_ULP_CLASS_HID_24afb = 0x24afb,\n+\tBNXT_ULP_CLASS_HID_2d5fb = 0x2d5fb,\n+\tBNXT_ULP_CLASS_HID_303cf = 0x303cf,\n+\tBNXT_ULP_CLASS_HID_38ecf = 0x38ecf,\n+\tBNXT_ULP_CLASS_HID_255b = 0x255b,\n+\tBNXT_ULP_CLASS_HID_2b97 = 0x2b97,\n+\tBNXT_ULP_CLASS_HID_4f0b = 0x4f0b,\n+\tBNXT_ULP_CLASS_HID_1633 = 0x1633,\n+\tBNXT_ULP_CLASS_HID_39a7 = 0x39a7,\n+\tBNXT_ULP_CLASS_HID_48cf = 0x48cf,\n+\tBNXT_ULP_CLASS_HID_0ff7 = 0x0ff7,\n+\tBNXT_ULP_CLASS_HID_336b = 0x336b,\n+\tBNXT_ULP_CLASS_HID_257f7 = 0x257f7,\n+\tBNXT_ULP_CLASS_HID_2858b = 0x2858b,\n+\tBNXT_ULP_CLASS_HID_3108b = 0x3108b,\n+\tBNXT_ULP_CLASS_HID_39b8b = 0x39b8b,\n+\tBNXT_ULP_CLASS_HID_24427 = 0x24427,\n+\tBNXT_ULP_CLASS_HID_2cf27 = 0x2cf27,\n+\tBNXT_ULP_CLASS_HID_35a27 = 0x35a27,\n+\tBNXT_ULP_CLASS_HID_388fb = 0x388fb,\n+\tBNXT_ULP_CLASS_HID_23ffb = 0x23ffb,\n+\tBNXT_ULP_CLASS_HID_2cafb = 0x2cafb,\n+\tBNXT_ULP_CLASS_HID_355fb = 0x355fb,\n+\tBNXT_ULP_CLASS_HID_3838f = 0x3838f,\n+\tBNXT_ULP_CLASS_HID_2528b = 0x2528b,\n+\tBNXT_ULP_CLASS_HID_2815f = 0x2815f,\n+\tBNXT_ULP_CLASS_HID_30c5f = 0x30c5f,\n+\tBNXT_ULP_CLASS_HID_3975f = 0x3975f,\n+\tBNXT_ULP_CLASS_HID_21e3f = 0x21e3f,\n+\tBNXT_ULP_CLASS_HID_2a93f = 0x2a93f,\n+\tBNXT_ULP_CLASS_HID_3343f = 0x3343f,\n+\tBNXT_ULP_CLASS_HID_3bf3f = 0x3bf3f,\n+\tBNXT_ULP_CLASS_HID_20b6f = 0x20b6f,\n+\tBNXT_ULP_CLASS_HID_2966f = 0x2966f,\n+\tBNXT_ULP_CLASS_HID_3216f = 0x3216f,\n+\tBNXT_ULP_CLASS_HID_3ac6f = 0x3ac6f,\n+\tBNXT_ULP_CLASS_HID_20623 = 0x20623,\n+\tBNXT_ULP_CLASS_HID_29123 = 0x29123,\n+\tBNXT_ULP_CLASS_HID_31c23 = 0x31c23,\n+\tBNXT_ULP_CLASS_HID_3a723 = 0x3a723,\n+\tBNXT_ULP_CLASS_HID_219f3 = 0x219f3,\n+\tBNXT_ULP_CLASS_HID_2a4f3 = 0x2a4f3,\n+\tBNXT_ULP_CLASS_HID_32ff3 = 0x32ff3,\n+\tBNXT_ULP_CLASS_HID_3baf3 = 0x3baf3,\n+\tBNXT_ULP_CLASS_HID_24253 = 0x24253,\n+\tBNXT_ULP_CLASS_HID_2cd53 = 0x2cd53,\n+\tBNXT_ULP_CLASS_HID_35853 = 0x35853,\n+\tBNXT_ULP_CLASS_HID_38667 = 0x38667,\n+\tBNXT_ULP_CLASS_HID_22e83 = 0x22e83,\n+\tBNXT_ULP_CLASS_HID_2b983 = 0x2b983,\n+\tBNXT_ULP_CLASS_HID_34483 = 0x34483,\n+\tBNXT_ULP_CLASS_HID_3cf83 = 0x3cf83,\n+\tBNXT_ULP_CLASS_HID_22a57 = 0x22a57,\n+\tBNXT_ULP_CLASS_HID_2b557 = 0x2b557,\n+\tBNXT_ULP_CLASS_HID_34057 = 0x34057,\n+\tBNXT_ULP_CLASS_HID_3cb57 = 0x3cb57,\n+\tBNXT_ULP_CLASS_HID_23d67 = 0x23d67,\n+\tBNXT_ULP_CLASS_HID_2c867 = 0x2c867,\n+\tBNXT_ULP_CLASS_HID_35367 = 0x35367,\n+\tBNXT_ULP_CLASS_HID_3813b = 0x3813b,\n+\tBNXT_ULP_CLASS_HID_2089b = 0x2089b,\n+\tBNXT_ULP_CLASS_HID_2939b = 0x2939b,\n+\tBNXT_ULP_CLASS_HID_31e9b = 0x31e9b,\n+\tBNXT_ULP_CLASS_HID_3a99b = 0x3a99b,\n+\tBNXT_ULP_CLASS_HID_25237 = 0x25237,\n+\tBNXT_ULP_CLASS_HID_280cb = 0x280cb,\n+\tBNXT_ULP_CLASS_HID_30bcb = 0x30bcb,\n+\tBNXT_ULP_CLASS_HID_396cb = 0x396cb,\n+\tBNXT_ULP_CLASS_HID_24dcb = 0x24dcb,\n+\tBNXT_ULP_CLASS_HID_2d8cb = 0x2d8cb,\n+\tBNXT_ULP_CLASS_HID_3069f = 0x3069f,\n+\tBNXT_ULP_CLASS_HID_3919f = 0x3919f,\n+\tBNXT_ULP_CLASS_HID_203af = 0x203af,\n+\tBNXT_ULP_CLASS_HID_28eaf = 0x28eaf,\n+\tBNXT_ULP_CLASS_HID_319af = 0x319af,\n+\tBNXT_ULP_CLASS_HID_3a4af = 0x3a4af,\n+\tBNXT_ULP_CLASS_HID_2513b = 0x2513b,\n+\tBNXT_ULP_CLASS_HID_2dc3b = 0x2dc3b,\n+\tBNXT_ULP_CLASS_HID_30acf = 0x30acf,\n+\tBNXT_ULP_CLASS_HID_395cf = 0x395cf,\n+\tBNXT_ULP_CLASS_HID_23e6b = 0x23e6b,\n+\tBNXT_ULP_CLASS_HID_2c96b = 0x2c96b,\n+\tBNXT_ULP_CLASS_HID_3546b = 0x3546b,\n+\tBNXT_ULP_CLASS_HID_3823f = 0x3823f,\n+\tBNXT_ULP_CLASS_HID_2393f = 0x2393f,\n+\tBNXT_ULP_CLASS_HID_2c43f = 0x2c43f,\n+\tBNXT_ULP_CLASS_HID_34f3f = 0x34f3f,\n+\tBNXT_ULP_CLASS_HID_3da3f = 0x3da3f,\n+\tBNXT_ULP_CLASS_HID_24ccf = 0x24ccf,\n+\tBNXT_ULP_CLASS_HID_2d7cf = 0x2d7cf,\n+\tBNXT_ULP_CLASS_HID_30583 = 0x30583,\n+\tBNXT_ULP_CLASS_HID_39083 = 0x39083,\n+\tBNXT_ULP_CLASS_HID_21863 = 0x21863,\n+\tBNXT_ULP_CLASS_HID_2a363 = 0x2a363,\n+\tBNXT_ULP_CLASS_HID_32e63 = 0x32e63,\n+\tBNXT_ULP_CLASS_HID_3b963 = 0x3b963,\n+\tBNXT_ULP_CLASS_HID_20553 = 0x20553,\n+\tBNXT_ULP_CLASS_HID_29053 = 0x29053,\n+\tBNXT_ULP_CLASS_HID_31b53 = 0x31b53,\n+\tBNXT_ULP_CLASS_HID_3a653 = 0x3a653,\n+\tBNXT_ULP_CLASS_HID_20067 = 0x20067,\n+\tBNXT_ULP_CLASS_HID_28b67 = 0x28b67,\n+\tBNXT_ULP_CLASS_HID_31667 = 0x31667,\n+\tBNXT_ULP_CLASS_HID_3a167 = 0x3a167,\n+\tBNXT_ULP_CLASS_HID_21337 = 0x21337,\n+\tBNXT_ULP_CLASS_HID_29e37 = 0x29e37,\n+\tBNXT_ULP_CLASS_HID_32937 = 0x32937,\n+\tBNXT_ULP_CLASS_HID_3b437 = 0x3b437,\n+\tBNXT_ULP_CLASS_HID_23b97 = 0x23b97,\n+\tBNXT_ULP_CLASS_HID_2c697 = 0x2c697,\n+\tBNXT_ULP_CLASS_HID_35197 = 0x35197,\n+\tBNXT_ULP_CLASS_HID_3dc97 = 0x3dc97,\n+\tBNXT_ULP_CLASS_HID_228c7 = 0x228c7,\n+\tBNXT_ULP_CLASS_HID_2b3c7 = 0x2b3c7,\n+\tBNXT_ULP_CLASS_HID_33ec7 = 0x33ec7,\n+\tBNXT_ULP_CLASS_HID_3c9c7 = 0x3c9c7,\n+\tBNXT_ULP_CLASS_HID_2239b = 0x2239b,\n+\tBNXT_ULP_CLASS_HID_2ae9b = 0x2ae9b,\n+\tBNXT_ULP_CLASS_HID_3399b = 0x3399b,\n+\tBNXT_ULP_CLASS_HID_3c49b = 0x3c49b,\n+\tBNXT_ULP_CLASS_HID_236ab = 0x236ab,\n+\tBNXT_ULP_CLASS_HID_2c1ab = 0x2c1ab,\n+\tBNXT_ULP_CLASS_HID_34cab = 0x34cab,\n+\tBNXT_ULP_CLASS_HID_3d7ab = 0x3d7ab,\n+\tBNXT_ULP_CLASS_HID_202df = 0x202df,\n+\tBNXT_ULP_CLASS_HID_28ddf = 0x28ddf,\n+\tBNXT_ULP_CLASS_HID_318df = 0x318df,\n+\tBNXT_ULP_CLASS_HID_3a3df = 0x3a3df,\n+\tBNXT_ULP_CLASS_HID_24c7b = 0x24c7b,\n+\tBNXT_ULP_CLASS_HID_2d77b = 0x2d77b,\n+\tBNXT_ULP_CLASS_HID_3050f = 0x3050f,\n+\tBNXT_ULP_CLASS_HID_3900f = 0x3900f,\n+\tBNXT_ULP_CLASS_HID_2470f = 0x2470f,\n+\tBNXT_ULP_CLASS_HID_2d20f = 0x2d20f,\n+\tBNXT_ULP_CLASS_HID_300c3 = 0x300c3,\n+\tBNXT_ULP_CLASS_HID_38bc3 = 0x38bc3,\n+\tBNXT_ULP_CLASS_HID_25adf = 0x25adf,\n+\tBNXT_ULP_CLASS_HID_28893 = 0x28893,\n+\tBNXT_ULP_CLASS_HID_31393 = 0x31393,\n+\tBNXT_ULP_CLASS_HID_39e93 = 0x39e93,\n+\tBNXT_ULP_CLASS_HID_24b7f = 0x24b7f,\n+\tBNXT_ULP_CLASS_HID_2d67f = 0x2d67f,\n+\tBNXT_ULP_CLASS_HID_30433 = 0x30433,\n+\tBNXT_ULP_CLASS_HID_38f33 = 0x38f33,\n+\tBNXT_ULP_CLASS_HID_237af = 0x237af,\n+\tBNXT_ULP_CLASS_HID_2c2af = 0x2c2af,\n+\tBNXT_ULP_CLASS_HID_34daf = 0x34daf,\n+\tBNXT_ULP_CLASS_HID_3d8af = 0x3d8af,\n+\tBNXT_ULP_CLASS_HID_23363 = 0x23363,\n+\tBNXT_ULP_CLASS_HID_2be63 = 0x2be63,\n+\tBNXT_ULP_CLASS_HID_34963 = 0x34963,\n+\tBNXT_ULP_CLASS_HID_3d463 = 0x3d463,\n+\tBNXT_ULP_CLASS_HID_24633 = 0x24633,\n+\tBNXT_ULP_CLASS_HID_2d133 = 0x2d133,\n+\tBNXT_ULP_CLASS_HID_35c33 = 0x35c33,\n+\tBNXT_ULP_CLASS_HID_38ac7 = 0x38ac7,\n+\tBNXT_ULP_CLASS_HID_211a7 = 0x211a7,\n+\tBNXT_ULP_CLASS_HID_29ca7 = 0x29ca7,\n+\tBNXT_ULP_CLASS_HID_327a7 = 0x327a7,\n+\tBNXT_ULP_CLASS_HID_3b2a7 = 0x3b2a7,\n+\tBNXT_ULP_CLASS_HID_25bc3 = 0x25bc3,\n+\tBNXT_ULP_CLASS_HID_28997 = 0x28997,\n+\tBNXT_ULP_CLASS_HID_31497 = 0x31497,\n+\tBNXT_ULP_CLASS_HID_39f97 = 0x39f97,\n+\tBNXT_ULP_CLASS_HID_25697 = 0x25697,\n+\tBNXT_ULP_CLASS_HID_284ab = 0x284ab,\n+\tBNXT_ULP_CLASS_HID_30fab = 0x30fab,\n+\tBNXT_ULP_CLASS_HID_39aab = 0x39aab,\n+\tBNXT_ULP_CLASS_HID_20d7b = 0x20d7b,\n+\tBNXT_ULP_CLASS_HID_2987b = 0x2987b,\n+\tBNXT_ULP_CLASS_HID_3237b = 0x3237b,\n+\tBNXT_ULP_CLASS_HID_3ae7b = 0x3ae7b,\n+\tBNXT_ULP_CLASS_HID_235db = 0x235db,\n+\tBNXT_ULP_CLASS_HID_2c0db = 0x2c0db,\n+\tBNXT_ULP_CLASS_HID_34bdb = 0x34bdb,\n+\tBNXT_ULP_CLASS_HID_3d6db = 0x3d6db,\n+\tBNXT_ULP_CLASS_HID_2220b = 0x2220b,\n+\tBNXT_ULP_CLASS_HID_2ad0b = 0x2ad0b,\n+\tBNXT_ULP_CLASS_HID_3380b = 0x3380b,\n+\tBNXT_ULP_CLASS_HID_3c30b = 0x3c30b,\n+\tBNXT_ULP_CLASS_HID_21ddf = 0x21ddf,\n+\tBNXT_ULP_CLASS_HID_2a8df = 0x2a8df,\n+\tBNXT_ULP_CLASS_HID_333df = 0x333df,\n+\tBNXT_ULP_CLASS_HID_3bedf = 0x3bedf,\n+\tBNXT_ULP_CLASS_HID_230ef = 0x230ef,\n+\tBNXT_ULP_CLASS_HID_2bbef = 0x2bbef,\n+\tBNXT_ULP_CLASS_HID_346ef = 0x346ef,\n+\tBNXT_ULP_CLASS_HID_3d1ef = 0x3d1ef,\n+\tBNXT_ULP_CLASS_HID_2594f = 0x2594f,\n+\tBNXT_ULP_CLASS_HID_28703 = 0x28703,\n+\tBNXT_ULP_CLASS_HID_31203 = 0x31203,\n+\tBNXT_ULP_CLASS_HID_39d03 = 0x39d03,\n+\tBNXT_ULP_CLASS_HID_245bf = 0x245bf,\n+\tBNXT_ULP_CLASS_HID_2d0bf = 0x2d0bf,\n+\tBNXT_ULP_CLASS_HID_35bbf = 0x35bbf,\n+\tBNXT_ULP_CLASS_HID_38a73 = 0x38a73,\n+\tBNXT_ULP_CLASS_HID_24173 = 0x24173,\n+\tBNXT_ULP_CLASS_HID_2cc73 = 0x2cc73,\n+\tBNXT_ULP_CLASS_HID_35773 = 0x35773,\n+\tBNXT_ULP_CLASS_HID_38507 = 0x38507,\n+\tBNXT_ULP_CLASS_HID_25403 = 0x25403,\n+\tBNXT_ULP_CLASS_HID_282d7 = 0x282d7,\n+\tBNXT_ULP_CLASS_HID_30dd7 = 0x30dd7,\n+\tBNXT_ULP_CLASS_HID_398d7 = 0x398d7,\n+\tBNXT_ULP_CLASS_HID_244a3 = 0x244a3,\n+\tBNXT_ULP_CLASS_HID_2cfa3 = 0x2cfa3,\n+\tBNXT_ULP_CLASS_HID_35aa3 = 0x35aa3,\n+\tBNXT_ULP_CLASS_HID_38977 = 0x38977,\n+\tBNXT_ULP_CLASS_HID_23193 = 0x23193,\n+\tBNXT_ULP_CLASS_HID_2bc93 = 0x2bc93,\n+\tBNXT_ULP_CLASS_HID_34793 = 0x34793,\n+\tBNXT_ULP_CLASS_HID_3d293 = 0x3d293,\n+\tBNXT_ULP_CLASS_HID_22ca7 = 0x22ca7,\n+\tBNXT_ULP_CLASS_HID_2b7a7 = 0x2b7a7,\n+\tBNXT_ULP_CLASS_HID_342a7 = 0x342a7,\n+\tBNXT_ULP_CLASS_HID_3cda7 = 0x3cda7,\n+\tBNXT_ULP_CLASS_HID_24077 = 0x24077,\n+\tBNXT_ULP_CLASS_HID_2cb77 = 0x2cb77,\n+\tBNXT_ULP_CLASS_HID_35677 = 0x35677,\n+\tBNXT_ULP_CLASS_HID_3840b = 0x3840b,\n+\tBNXT_ULP_CLASS_HID_20beb = 0x20beb,\n+\tBNXT_ULP_CLASS_HID_296eb = 0x296eb,\n+\tBNXT_ULP_CLASS_HID_321eb = 0x321eb,\n+\tBNXT_ULP_CLASS_HID_3aceb = 0x3aceb,\n+\tBNXT_ULP_CLASS_HID_25507 = 0x25507,\n+\tBNXT_ULP_CLASS_HID_283db = 0x283db,\n+\tBNXT_ULP_CLASS_HID_30edb = 0x30edb,\n+\tBNXT_ULP_CLASS_HID_399db = 0x399db,\n+\tBNXT_ULP_CLASS_HID_250db = 0x250db,\n+\tBNXT_ULP_CLASS_HID_2dbdb = 0x2dbdb,\n+\tBNXT_ULP_CLASS_HID_309ef = 0x309ef,\n+\tBNXT_ULP_CLASS_HID_394ef = 0x394ef,\n+\tBNXT_ULP_CLASS_HID_206bf = 0x206bf,\n+\tBNXT_ULP_CLASS_HID_291bf = 0x291bf,\n+\tBNXT_ULP_CLASS_HID_31cbf = 0x31cbf,\n+\tBNXT_ULP_CLASS_HID_3a7bf = 0x3a7bf,\n+\tBNXT_ULP_CLASS_HID_22f1f = 0x22f1f,\n+\tBNXT_ULP_CLASS_HID_2ba1f = 0x2ba1f,\n+\tBNXT_ULP_CLASS_HID_3451f = 0x3451f,\n+\tBNXT_ULP_CLASS_HID_3d01f = 0x3d01f,\n+\tBNXT_ULP_CLASS_HID_21c4f = 0x21c4f,\n+\tBNXT_ULP_CLASS_HID_2a74f = 0x2a74f,\n+\tBNXT_ULP_CLASS_HID_3324f = 0x3324f,\n+\tBNXT_ULP_CLASS_HID_3bd4f = 0x3bd4f,\n+\tBNXT_ULP_CLASS_HID_21703 = 0x21703,\n+\tBNXT_ULP_CLASS_HID_2a203 = 0x2a203,\n+\tBNXT_ULP_CLASS_HID_32d03 = 0x32d03,\n+\tBNXT_ULP_CLASS_HID_3b803 = 0x3b803,\n+\tBNXT_ULP_CLASS_HID_22ad3 = 0x22ad3,\n+\tBNXT_ULP_CLASS_HID_2b5d3 = 0x2b5d3,\n+\tBNXT_ULP_CLASS_HID_340d3 = 0x340d3,\n+\tBNXT_ULP_CLASS_HID_3cbd3 = 0x3cbd3,\n+\tBNXT_ULP_CLASS_HID_252b3 = 0x252b3,\n+\tBNXT_ULP_CLASS_HID_28147 = 0x28147,\n+\tBNXT_ULP_CLASS_HID_30c47 = 0x30c47,\n+\tBNXT_ULP_CLASS_HID_39747 = 0x39747,\n+\tBNXT_ULP_CLASS_HID_23fe3 = 0x23fe3,\n+\tBNXT_ULP_CLASS_HID_2cae3 = 0x2cae3,\n+\tBNXT_ULP_CLASS_HID_355e3 = 0x355e3,\n+\tBNXT_ULP_CLASS_HID_383b7 = 0x383b7,\n+\tBNXT_ULP_CLASS_HID_23ab7 = 0x23ab7,\n+\tBNXT_ULP_CLASS_HID_2c5b7 = 0x2c5b7,\n+\tBNXT_ULP_CLASS_HID_350b7 = 0x350b7,\n+\tBNXT_ULP_CLASS_HID_3dbb7 = 0x3dbb7,\n+\tBNXT_ULP_CLASS_HID_24e47 = 0x24e47,\n+\tBNXT_ULP_CLASS_HID_2d947 = 0x2d947,\n+\tBNXT_ULP_CLASS_HID_3071b = 0x3071b,\n+\tBNXT_ULP_CLASS_HID_3921b = 0x3921b,\n+\tBNXT_ULP_CLASS_HID_2326f = 0x2326f,\n+\tBNXT_ULP_CLASS_HID_2bd6f = 0x2bd6f,\n+\tBNXT_ULP_CLASS_HID_3486f = 0x3486f,\n+\tBNXT_ULP_CLASS_HID_3d36f = 0x3d36f,\n+\tBNXT_ULP_CLASS_HID_21f5f = 0x21f5f,\n+\tBNXT_ULP_CLASS_HID_2aa5f = 0x2aa5f,\n+\tBNXT_ULP_CLASS_HID_3355f = 0x3355f,\n+\tBNXT_ULP_CLASS_HID_3c05f = 0x3c05f,\n+\tBNXT_ULP_CLASS_HID_21a13 = 0x21a13,\n+\tBNXT_ULP_CLASS_HID_2a513 = 0x2a513,\n+\tBNXT_ULP_CLASS_HID_33013 = 0x33013,\n+\tBNXT_ULP_CLASS_HID_3bb13 = 0x3bb13,\n+\tBNXT_ULP_CLASS_HID_22d23 = 0x22d23,\n+\tBNXT_ULP_CLASS_HID_2b823 = 0x2b823,\n+\tBNXT_ULP_CLASS_HID_34323 = 0x34323,\n+\tBNXT_ULP_CLASS_HID_3ce23 = 0x3ce23,\n+\tBNXT_ULP_CLASS_HID_25583 = 0x25583,\n+\tBNXT_ULP_CLASS_HID_28457 = 0x28457,\n+\tBNXT_ULP_CLASS_HID_30f57 = 0x30f57,\n+\tBNXT_ULP_CLASS_HID_39a57 = 0x39a57,\n+\tBNXT_ULP_CLASS_HID_242f3 = 0x242f3,\n+\tBNXT_ULP_CLASS_HID_2cdf3 = 0x2cdf3,\n+\tBNXT_ULP_CLASS_HID_358f3 = 0x358f3,\n+\tBNXT_ULP_CLASS_HID_38687 = 0x38687,\n+\tBNXT_ULP_CLASS_HID_23d87 = 0x23d87,\n+\tBNXT_ULP_CLASS_HID_2c887 = 0x2c887,\n+\tBNXT_ULP_CLASS_HID_35387 = 0x35387,\n+\tBNXT_ULP_CLASS_HID_3825b = 0x3825b,\n+\tBNXT_ULP_CLASS_HID_25157 = 0x25157,\n+\tBNXT_ULP_CLASS_HID_2dc57 = 0x2dc57,\n+\tBNXT_ULP_CLASS_HID_30a6b = 0x30a6b,\n+\tBNXT_ULP_CLASS_HID_3956b = 0x3956b,\n+\tBNXT_ULP_CLASS_HID_22c53 = 0x22c53,\n+\tBNXT_ULP_CLASS_HID_2b753 = 0x2b753,\n+\tBNXT_ULP_CLASS_HID_34253 = 0x34253,\n+\tBNXT_ULP_CLASS_HID_3cd53 = 0x3cd53,\n+\tBNXT_ULP_CLASS_HID_21883 = 0x21883,\n+\tBNXT_ULP_CLASS_HID_2a383 = 0x2a383,\n+\tBNXT_ULP_CLASS_HID_32e83 = 0x32e83,\n+\tBNXT_ULP_CLASS_HID_3b983 = 0x3b983,\n+\tBNXT_ULP_CLASS_HID_21457 = 0x21457,\n+\tBNXT_ULP_CLASS_HID_29f57 = 0x29f57,\n+\tBNXT_ULP_CLASS_HID_32a57 = 0x32a57,\n+\tBNXT_ULP_CLASS_HID_3b557 = 0x3b557,\n+\tBNXT_ULP_CLASS_HID_22767 = 0x22767,\n+\tBNXT_ULP_CLASS_HID_2b267 = 0x2b267,\n+\tBNXT_ULP_CLASS_HID_33d67 = 0x33d67,\n+\tBNXT_ULP_CLASS_HID_3c867 = 0x3c867,\n+\tBNXT_ULP_CLASS_HID_24fc7 = 0x24fc7,\n+\tBNXT_ULP_CLASS_HID_2dac7 = 0x2dac7,\n+\tBNXT_ULP_CLASS_HID_3089b = 0x3089b,\n+\tBNXT_ULP_CLASS_HID_3939b = 0x3939b,\n+\tBNXT_ULP_CLASS_HID_23c37 = 0x23c37,\n+\tBNXT_ULP_CLASS_HID_2c737 = 0x2c737,\n+\tBNXT_ULP_CLASS_HID_35237 = 0x35237,\n+\tBNXT_ULP_CLASS_HID_380cb = 0x380cb,\n+\tBNXT_ULP_CLASS_HID_237cb = 0x237cb,\n+\tBNXT_ULP_CLASS_HID_2c2cb = 0x2c2cb,\n+\tBNXT_ULP_CLASS_HID_34dcb = 0x34dcb,\n+\tBNXT_ULP_CLASS_HID_3d8cb = 0x3d8cb,\n+\tBNXT_ULP_CLASS_HID_24a9b = 0x24a9b,\n+\tBNXT_ULP_CLASS_HID_2d59b = 0x2d59b,\n+\tBNXT_ULP_CLASS_HID_303af = 0x303af,\n+\tBNXT_ULP_CLASS_HID_38eaf = 0x38eaf,\n+\tBNXT_ULP_CLASS_HID_253b = 0x253b,\n+\tBNXT_ULP_CLASS_HID_2bf7 = 0x2bf7,\n+\tBNXT_ULP_CLASS_HID_4f6b = 0x4f6b,\n+\tBNXT_ULP_CLASS_HID_1653 = 0x1653,\n+\tBNXT_ULP_CLASS_HID_39c7 = 0x39c7,\n+\tBNXT_ULP_CLASS_HID_48af = 0x48af,\n+\tBNXT_ULP_CLASS_HID_0f97 = 0x0f97,\n+\tBNXT_ULP_CLASS_HID_330b = 0x330b,\n+\tBNXT_ULP_CLASS_HID_374e = 0x374e,\n+\tBNXT_ULP_CLASS_HID_11ee = 0x11ee,\n+\tBNXT_ULP_CLASS_HID_423a = 0x423a,\n+\tBNXT_ULP_CLASS_HID_0cd6 = 0x0cd6,\n+\tBNXT_ULP_CLASS_HID_310a = 0x310a,\n+\tBNXT_ULP_CLASS_HID_469e = 0x469e,\n+\tBNXT_ULP_CLASS_HID_5ce6 = 0x5ce6,\n+\tBNXT_ULP_CLASS_HID_0692 = 0x0692,\n+\tBNXT_ULP_CLASS_HID_1c7e = 0x1c7e,\n+\tBNXT_ULP_CLASS_HID_55c2 = 0x55c2,\n+\tBNXT_ULP_CLASS_HID_2b2a = 0x2b2a,\n+\tBNXT_ULP_CLASS_HID_15c6 = 0x15c6,\n+\tBNXT_ULP_CLASS_HID_163a = 0x163a,\n+\tBNXT_ULP_CLASS_HID_2f8e = 0x2f8e,\n+\tBNXT_ULP_CLASS_HID_2516 = 0x2516,\n+\tBNXT_ULP_CLASS_HID_4b76 = 0x4b76,\n+\tBNXT_ULP_CLASS_HID_10e6 = 0x10e6,\n+\tBNXT_ULP_CLASS_HID_264a = 0x264a,\n+\tBNXT_ULP_CLASS_HID_3fd2 = 0x3fd2,\n+\tBNXT_ULP_CLASS_HID_4532 = 0x4532,\n+\tBNXT_ULP_CLASS_HID_4996 = 0x4996,\n+\tBNXT_ULP_CLASS_HID_2036 = 0x2036,\n+\tBNXT_ULP_CLASS_HID_399e = 0x399e,\n+\tBNXT_ULP_CLASS_HID_5ffe = 0x5ffe,\n+\tBNXT_ULP_CLASS_HID_34fe = 0x34fe,\n+\tBNXT_ULP_CLASS_HID_3a32 = 0x3a32,\n+\tBNXT_ULP_CLASS_HID_376e = 0x376e,\n+\tBNXT_ULP_CLASS_HID_12d6e = 0x12d6e,\n+\tBNXT_ULP_CLASS_HID_2436e = 0x2436e,\n+\tBNXT_ULP_CLASS_HID_31dba = 0x31dba,\n+\tBNXT_ULP_CLASS_HID_11ce = 0x11ce,\n+\tBNXT_ULP_CLASS_HID_107ce = 0x107ce,\n+\tBNXT_ULP_CLASS_HID_23dce = 0x23dce,\n+\tBNXT_ULP_CLASS_HID_353ce = 0x353ce,\n+\tBNXT_ULP_CLASS_HID_421a = 0x421a,\n+\tBNXT_ULP_CLASS_HID_11d56 = 0x11d56,\n+\tBNXT_ULP_CLASS_HID_23356 = 0x23356,\n+\tBNXT_ULP_CLASS_HID_32956 = 0x32956,\n+\tBNXT_ULP_CLASS_HID_0cf6 = 0x0cf6,\n+\tBNXT_ULP_CLASS_HID_122f6 = 0x122f6,\n+\tBNXT_ULP_CLASS_HID_258f6 = 0x258f6,\n+\tBNXT_ULP_CLASS_HID_313c2 = 0x313c2,\n+\tBNXT_ULP_CLASS_HID_312a = 0x312a,\n+\tBNXT_ULP_CLASS_HID_1272a = 0x1272a,\n+\tBNXT_ULP_CLASS_HID_25d2a = 0x25d2a,\n+\tBNXT_ULP_CLASS_HID_31466 = 0x31466,\n+\tBNXT_ULP_CLASS_HID_46be = 0x46be,\n+\tBNXT_ULP_CLASS_HID_1018a = 0x1018a,\n+\tBNXT_ULP_CLASS_HID_2378a = 0x2378a,\n+\tBNXT_ULP_CLASS_HID_32d8a = 0x32d8a,\n+\tBNXT_ULP_CLASS_HID_5cc6 = 0x5cc6,\n+\tBNXT_ULP_CLASS_HID_11712 = 0x11712,\n+\tBNXT_ULP_CLASS_HID_20d12 = 0x20d12,\n+\tBNXT_ULP_CLASS_HID_32312 = 0x32312,\n+\tBNXT_ULP_CLASS_HID_06b2 = 0x06b2,\n+\tBNXT_ULP_CLASS_HID_13cb2 = 0x13cb2,\n+\tBNXT_ULP_CLASS_HID_252b2 = 0x252b2,\n+\tBNXT_ULP_CLASS_HID_348b2 = 0x348b2,\n+\tBNXT_ULP_CLASS_HID_1c5e = 0x1c5e,\n+\tBNXT_ULP_CLASS_HID_1325e = 0x1325e,\n+\tBNXT_ULP_CLASS_HID_2285e = 0x2285e,\n+\tBNXT_ULP_CLASS_HID_35e5e = 0x35e5e,\n+\tBNXT_ULP_CLASS_HID_55e2 = 0x55e2,\n+\tBNXT_ULP_CLASS_HID_14be2 = 0x14be2,\n+\tBNXT_ULP_CLASS_HID_2023e = 0x2023e,\n+\tBNXT_ULP_CLASS_HID_3383e = 0x3383e,\n+\tBNXT_ULP_CLASS_HID_2b0a = 0x2b0a,\n+\tBNXT_ULP_CLASS_HID_1410a = 0x1410a,\n+\tBNXT_ULP_CLASS_HID_21846 = 0x21846,\n+\tBNXT_ULP_CLASS_HID_30e46 = 0x30e46,\n+\tBNXT_ULP_CLASS_HID_15e6 = 0x15e6,\n+\tBNXT_ULP_CLASS_HID_10be6 = 0x10be6,\n+\tBNXT_ULP_CLASS_HID_221e6 = 0x221e6,\n+\tBNXT_ULP_CLASS_HID_357e6 = 0x357e6,\n+\tBNXT_ULP_CLASS_HID_161a = 0x161a,\n+\tBNXT_ULP_CLASS_HID_10c1a = 0x10c1a,\n+\tBNXT_ULP_CLASS_HID_2221a = 0x2221a,\n+\tBNXT_ULP_CLASS_HID_3581a = 0x3581a,\n+\tBNXT_ULP_CLASS_HID_2fae = 0x2fae,\n+\tBNXT_ULP_CLASS_HID_145ae = 0x145ae,\n+\tBNXT_ULP_CLASS_HID_21cfa = 0x21cfa,\n+\tBNXT_ULP_CLASS_HID_332fa = 0x332fa,\n+\tBNXT_ULP_CLASS_HID_2536 = 0x2536,\n+\tBNXT_ULP_CLASS_HID_15b36 = 0x15b36,\n+\tBNXT_ULP_CLASS_HID_21202 = 0x21202,\n+\tBNXT_ULP_CLASS_HID_30802 = 0x30802,\n+\tBNXT_ULP_CLASS_HID_4b56 = 0x4b56,\n+\tBNXT_ULP_CLASS_HID_105a2 = 0x105a2,\n+\tBNXT_ULP_CLASS_HID_23ba2 = 0x23ba2,\n+\tBNXT_ULP_CLASS_HID_351a2 = 0x351a2,\n+\tBNXT_ULP_CLASS_HID_10c6 = 0x10c6,\n+\tBNXT_ULP_CLASS_HID_106c6 = 0x106c6,\n+\tBNXT_ULP_CLASS_HID_23cc6 = 0x23cc6,\n+\tBNXT_ULP_CLASS_HID_352c6 = 0x352c6,\n+\tBNXT_ULP_CLASS_HID_266a = 0x266a,\n+\tBNXT_ULP_CLASS_HID_15c6a = 0x15c6a,\n+\tBNXT_ULP_CLASS_HID_216a6 = 0x216a6,\n+\tBNXT_ULP_CLASS_HID_30ca6 = 0x30ca6,\n+\tBNXT_ULP_CLASS_HID_3ff2 = 0x3ff2,\n+\tBNXT_ULP_CLASS_HID_155f2 = 0x155f2,\n+\tBNXT_ULP_CLASS_HID_24bf2 = 0x24bf2,\n+\tBNXT_ULP_CLASS_HID_302ce = 0x302ce,\n+\tBNXT_ULP_CLASS_HID_4512 = 0x4512,\n+\tBNXT_ULP_CLASS_HID_11c6e = 0x11c6e,\n+\tBNXT_ULP_CLASS_HID_2326e = 0x2326e,\n+\tBNXT_ULP_CLASS_HID_3286e = 0x3286e,\n+\tBNXT_ULP_CLASS_HID_49b6 = 0x49b6,\n+\tBNXT_ULP_CLASS_HID_10082 = 0x10082,\n+\tBNXT_ULP_CLASS_HID_23682 = 0x23682,\n+\tBNXT_ULP_CLASS_HID_32c82 = 0x32c82,\n+\tBNXT_ULP_CLASS_HID_2016 = 0x2016,\n+\tBNXT_ULP_CLASS_HID_15616 = 0x15616,\n+\tBNXT_ULP_CLASS_HID_21162 = 0x21162,\n+\tBNXT_ULP_CLASS_HID_30762 = 0x30762,\n+\tBNXT_ULP_CLASS_HID_39be = 0x39be,\n+\tBNXT_ULP_CLASS_HID_12fbe = 0x12fbe,\n+\tBNXT_ULP_CLASS_HID_245be = 0x245be,\n+\tBNXT_ULP_CLASS_HID_31c8a = 0x31c8a,\n+\tBNXT_ULP_CLASS_HID_5fde = 0x5fde,\n+\tBNXT_ULP_CLASS_HID_1162a = 0x1162a,\n+\tBNXT_ULP_CLASS_HID_20c2a = 0x20c2a,\n+\tBNXT_ULP_CLASS_HID_3222a = 0x3222a,\n+\tBNXT_ULP_CLASS_HID_34de = 0x34de,\n+\tBNXT_ULP_CLASS_HID_3a12 = 0x3a12,\n+\tBNXT_ULP_CLASS_HID_370e = 0x370e,\n+\tBNXT_ULP_CLASS_HID_12d0e = 0x12d0e,\n+\tBNXT_ULP_CLASS_HID_2430e = 0x2430e,\n+\tBNXT_ULP_CLASS_HID_31dda = 0x31dda,\n+\tBNXT_ULP_CLASS_HID_11ae = 0x11ae,\n+\tBNXT_ULP_CLASS_HID_107ae = 0x107ae,\n+\tBNXT_ULP_CLASS_HID_23dae = 0x23dae,\n+\tBNXT_ULP_CLASS_HID_353ae = 0x353ae,\n+\tBNXT_ULP_CLASS_HID_427a = 0x427a,\n+\tBNXT_ULP_CLASS_HID_11d36 = 0x11d36,\n+\tBNXT_ULP_CLASS_HID_23336 = 0x23336,\n+\tBNXT_ULP_CLASS_HID_32936 = 0x32936,\n+\tBNXT_ULP_CLASS_HID_0c96 = 0x0c96,\n+\tBNXT_ULP_CLASS_HID_12296 = 0x12296,\n+\tBNXT_ULP_CLASS_HID_25896 = 0x25896,\n+\tBNXT_ULP_CLASS_HID_313a2 = 0x313a2,\n+\tBNXT_ULP_CLASS_HID_314a = 0x314a,\n+\tBNXT_ULP_CLASS_HID_1274a = 0x1274a,\n+\tBNXT_ULP_CLASS_HID_25d4a = 0x25d4a,\n+\tBNXT_ULP_CLASS_HID_31406 = 0x31406,\n+\tBNXT_ULP_CLASS_HID_46de = 0x46de,\n+\tBNXT_ULP_CLASS_HID_101ea = 0x101ea,\n+\tBNXT_ULP_CLASS_HID_237ea = 0x237ea,\n+\tBNXT_ULP_CLASS_HID_32dea = 0x32dea,\n+\tBNXT_ULP_CLASS_HID_5ca6 = 0x5ca6,\n+\tBNXT_ULP_CLASS_HID_11772 = 0x11772,\n+\tBNXT_ULP_CLASS_HID_20d72 = 0x20d72,\n+\tBNXT_ULP_CLASS_HID_32372 = 0x32372,\n+\tBNXT_ULP_CLASS_HID_06d2 = 0x06d2,\n+\tBNXT_ULP_CLASS_HID_13cd2 = 0x13cd2,\n+\tBNXT_ULP_CLASS_HID_252d2 = 0x252d2,\n+\tBNXT_ULP_CLASS_HID_348d2 = 0x348d2,\n+\tBNXT_ULP_CLASS_HID_1c3e = 0x1c3e,\n+\tBNXT_ULP_CLASS_HID_1323e = 0x1323e,\n+\tBNXT_ULP_CLASS_HID_2283e = 0x2283e,\n+\tBNXT_ULP_CLASS_HID_35e3e = 0x35e3e,\n+\tBNXT_ULP_CLASS_HID_5582 = 0x5582,\n+\tBNXT_ULP_CLASS_HID_14b82 = 0x14b82,\n+\tBNXT_ULP_CLASS_HID_2025e = 0x2025e,\n+\tBNXT_ULP_CLASS_HID_3385e = 0x3385e,\n+\tBNXT_ULP_CLASS_HID_2b6a = 0x2b6a,\n+\tBNXT_ULP_CLASS_HID_1416a = 0x1416a,\n+\tBNXT_ULP_CLASS_HID_21826 = 0x21826,\n+\tBNXT_ULP_CLASS_HID_30e26 = 0x30e26,\n+\tBNXT_ULP_CLASS_HID_1586 = 0x1586,\n+\tBNXT_ULP_CLASS_HID_10b86 = 0x10b86,\n+\tBNXT_ULP_CLASS_HID_22186 = 0x22186,\n+\tBNXT_ULP_CLASS_HID_35786 = 0x35786,\n+\tBNXT_ULP_CLASS_HID_167a = 0x167a,\n+\tBNXT_ULP_CLASS_HID_10c7a = 0x10c7a,\n+\tBNXT_ULP_CLASS_HID_2227a = 0x2227a,\n+\tBNXT_ULP_CLASS_HID_3587a = 0x3587a,\n+\tBNXT_ULP_CLASS_HID_2fce = 0x2fce,\n+\tBNXT_ULP_CLASS_HID_145ce = 0x145ce,\n+\tBNXT_ULP_CLASS_HID_21c9a = 0x21c9a,\n+\tBNXT_ULP_CLASS_HID_3329a = 0x3329a,\n+\tBNXT_ULP_CLASS_HID_2556 = 0x2556,\n+\tBNXT_ULP_CLASS_HID_15b56 = 0x15b56,\n+\tBNXT_ULP_CLASS_HID_21262 = 0x21262,\n+\tBNXT_ULP_CLASS_HID_30862 = 0x30862,\n+\tBNXT_ULP_CLASS_HID_4b36 = 0x4b36,\n+\tBNXT_ULP_CLASS_HID_105c2 = 0x105c2,\n+\tBNXT_ULP_CLASS_HID_23bc2 = 0x23bc2,\n+\tBNXT_ULP_CLASS_HID_351c2 = 0x351c2,\n+\tBNXT_ULP_CLASS_HID_10a6 = 0x10a6,\n+\tBNXT_ULP_CLASS_HID_106a6 = 0x106a6,\n+\tBNXT_ULP_CLASS_HID_23ca6 = 0x23ca6,\n+\tBNXT_ULP_CLASS_HID_352a6 = 0x352a6,\n+\tBNXT_ULP_CLASS_HID_260a = 0x260a,\n+\tBNXT_ULP_CLASS_HID_15c0a = 0x15c0a,\n+\tBNXT_ULP_CLASS_HID_216c6 = 0x216c6,\n+\tBNXT_ULP_CLASS_HID_30cc6 = 0x30cc6,\n+\tBNXT_ULP_CLASS_HID_3f92 = 0x3f92,\n+\tBNXT_ULP_CLASS_HID_15592 = 0x15592,\n+\tBNXT_ULP_CLASS_HID_24b92 = 0x24b92,\n+\tBNXT_ULP_CLASS_HID_302ae = 0x302ae,\n+\tBNXT_ULP_CLASS_HID_4572 = 0x4572,\n+\tBNXT_ULP_CLASS_HID_11c0e = 0x11c0e,\n+\tBNXT_ULP_CLASS_HID_2320e = 0x2320e,\n+\tBNXT_ULP_CLASS_HID_3280e = 0x3280e,\n+\tBNXT_ULP_CLASS_HID_49d6 = 0x49d6,\n+\tBNXT_ULP_CLASS_HID_100e2 = 0x100e2,\n+\tBNXT_ULP_CLASS_HID_236e2 = 0x236e2,\n+\tBNXT_ULP_CLASS_HID_32ce2 = 0x32ce2,\n+\tBNXT_ULP_CLASS_HID_2076 = 0x2076,\n+\tBNXT_ULP_CLASS_HID_15676 = 0x15676,\n+\tBNXT_ULP_CLASS_HID_21102 = 0x21102,\n+\tBNXT_ULP_CLASS_HID_30702 = 0x30702,\n+\tBNXT_ULP_CLASS_HID_39de = 0x39de,\n+\tBNXT_ULP_CLASS_HID_12fde = 0x12fde,\n+\tBNXT_ULP_CLASS_HID_245de = 0x245de,\n+\tBNXT_ULP_CLASS_HID_31cea = 0x31cea,\n+\tBNXT_ULP_CLASS_HID_5fbe = 0x5fbe,\n+\tBNXT_ULP_CLASS_HID_1164a = 0x1164a,\n+\tBNXT_ULP_CLASS_HID_20c4a = 0x20c4a,\n+\tBNXT_ULP_CLASS_HID_3224a = 0x3224a,\n+\tBNXT_ULP_CLASS_HID_34be = 0x34be,\n+\tBNXT_ULP_CLASS_HID_3a72 = 0x3a72,\n+\tBNXT_ULP_CLASS_HID_09ea = 0x09ea,\n+\tBNXT_ULP_CLASS_HID_2912 = 0x2912,\n+\tBNXT_ULP_CLASS_HID_03b2 = 0x03b2,\n+\tBNXT_ULP_CLASS_HID_5f7e = 0x5f7e,\n+\tBNXT_ULP_CLASS_HID_03a6 = 0x03a6,\n+\tBNXT_ULP_CLASS_HID_23ce = 0x23ce,\n+\tBNXT_ULP_CLASS_HID_1a6e = 0x1a6e,\n+\tBNXT_ULP_CLASS_HID_593a = 0x593a,\n+\tBNXT_ULP_CLASS_HID_4dce = 0x4dce,\n+\tBNXT_ULP_CLASS_HID_0e02 = 0x0e02,\n+\tBNXT_ULP_CLASS_HID_4796 = 0x4796,\n+\tBNXT_ULP_CLASS_HID_246e = 0x246e,\n+\tBNXT_ULP_CLASS_HID_478a = 0x478a,\n+\tBNXT_ULP_CLASS_HID_08fe = 0x08fe,\n+\tBNXT_ULP_CLASS_HID_5e52 = 0x5e52,\n+\tBNXT_ULP_CLASS_HID_3e2a = 0x3e2a,\n+\tBNXT_ULP_CLASS_HID_5e46 = 0x5e46,\n+\tBNXT_ULP_CLASS_HID_02ba = 0x02ba,\n+\tBNXT_ULP_CLASS_HID_580e = 0x580e,\n+\tBNXT_ULP_CLASS_HID_38e6 = 0x38e6,\n+\tBNXT_ULP_CLASS_HID_5802 = 0x5802,\n+\tBNXT_ULP_CLASS_HID_1d76 = 0x1d76,\n+\tBNXT_ULP_CLASS_HID_52ca = 0x52ca,\n+\tBNXT_ULP_CLASS_HID_32a2 = 0x32a2,\n+\tBNXT_ULP_CLASS_HID_34f6 = 0x34f6,\n+\tBNXT_ULP_CLASS_HID_3a3a = 0x3a3a,\n+\tBNXT_ULP_CLASS_HID_09ca = 0x09ca,\n+\tBNXT_ULP_CLASS_HID_0216 = 0x0216,\n+\tBNXT_ULP_CLASS_HID_1f62 = 0x1f62,\n+\tBNXT_ULP_CLASS_HID_1bae = 0x1bae,\n+\tBNXT_ULP_CLASS_HID_2932 = 0x2932,\n+\tBNXT_ULP_CLASS_HID_227e = 0x227e,\n+\tBNXT_ULP_CLASS_HID_3f4a = 0x3f4a,\n+\tBNXT_ULP_CLASS_HID_3b96 = 0x3b96,\n+\tBNXT_ULP_CLASS_HID_0392 = 0x0392,\n+\tBNXT_ULP_CLASS_HID_1cde = 0x1cde,\n+\tBNXT_ULP_CLASS_HID_192a = 0x192a,\n+\tBNXT_ULP_CLASS_HID_1276 = 0x1276,\n+\tBNXT_ULP_CLASS_HID_5f5e = 0x5f5e,\n+\tBNXT_ULP_CLASS_HID_5baa = 0x5baa,\n+\tBNXT_ULP_CLASS_HID_54f6 = 0x54f6,\n+\tBNXT_ULP_CLASS_HID_51c2 = 0x51c2,\n+\tBNXT_ULP_CLASS_HID_0386 = 0x0386,\n+\tBNXT_ULP_CLASS_HID_1cd2 = 0x1cd2,\n+\tBNXT_ULP_CLASS_HID_191e = 0x191e,\n+\tBNXT_ULP_CLASS_HID_126a = 0x126a,\n+\tBNXT_ULP_CLASS_HID_23ee = 0x23ee,\n+\tBNXT_ULP_CLASS_HID_3c3a = 0x3c3a,\n+\tBNXT_ULP_CLASS_HID_3906 = 0x3906,\n+\tBNXT_ULP_CLASS_HID_3252 = 0x3252,\n+\tBNXT_ULP_CLASS_HID_1a4e = 0x1a4e,\n+\tBNXT_ULP_CLASS_HID_169a = 0x169a,\n+\tBNXT_ULP_CLASS_HID_13e6 = 0x13e6,\n+\tBNXT_ULP_CLASS_HID_4be6 = 0x4be6,\n+\tBNXT_ULP_CLASS_HID_591a = 0x591a,\n+\tBNXT_ULP_CLASS_HID_5266 = 0x5266,\n+\tBNXT_ULP_CLASS_HID_2eb2 = 0x2eb2,\n+\tBNXT_ULP_CLASS_HID_2bfe = 0x2bfe,\n+\tBNXT_ULP_CLASS_HID_4dee = 0x4dee,\n+\tBNXT_ULP_CLASS_HID_463a = 0x463a,\n+\tBNXT_ULP_CLASS_HID_4306 = 0x4306,\n+\tBNXT_ULP_CLASS_HID_5c52 = 0x5c52,\n+\tBNXT_ULP_CLASS_HID_0e22 = 0x0e22,\n+\tBNXT_ULP_CLASS_HID_0b6e = 0x0b6e,\n+\tBNXT_ULP_CLASS_HID_07ba = 0x07ba,\n+\tBNXT_ULP_CLASS_HID_0086 = 0x0086,\n+\tBNXT_ULP_CLASS_HID_47b6 = 0x47b6,\n+\tBNXT_ULP_CLASS_HID_4082 = 0x4082,\n+\tBNXT_ULP_CLASS_HID_5dce = 0x5dce,\n+\tBNXT_ULP_CLASS_HID_561a = 0x561a,\n+\tBNXT_ULP_CLASS_HID_244e = 0x244e,\n+\tBNXT_ULP_CLASS_HID_209a = 0x209a,\n+\tBNXT_ULP_CLASS_HID_3de6 = 0x3de6,\n+\tBNXT_ULP_CLASS_HID_3632 = 0x3632,\n+\tBNXT_ULP_CLASS_HID_47aa = 0x47aa,\n+\tBNXT_ULP_CLASS_HID_40f6 = 0x40f6,\n+\tBNXT_ULP_CLASS_HID_5dc2 = 0x5dc2,\n+\tBNXT_ULP_CLASS_HID_560e = 0x560e,\n+\tBNXT_ULP_CLASS_HID_08de = 0x08de,\n+\tBNXT_ULP_CLASS_HID_052a = 0x052a,\n+\tBNXT_ULP_CLASS_HID_1e76 = 0x1e76,\n+\tBNXT_ULP_CLASS_HID_1b42 = 0x1b42,\n+\tBNXT_ULP_CLASS_HID_5e72 = 0x5e72,\n+\tBNXT_ULP_CLASS_HID_5abe = 0x5abe,\n+\tBNXT_ULP_CLASS_HID_578a = 0x578a,\n+\tBNXT_ULP_CLASS_HID_50d6 = 0x50d6,\n+\tBNXT_ULP_CLASS_HID_3e0a = 0x3e0a,\n+\tBNXT_ULP_CLASS_HID_3b56 = 0x3b56,\n+\tBNXT_ULP_CLASS_HID_37a2 = 0x37a2,\n+\tBNXT_ULP_CLASS_HID_30ee = 0x30ee,\n+\tBNXT_ULP_CLASS_HID_5e66 = 0x5e66,\n+\tBNXT_ULP_CLASS_HID_5ab2 = 0x5ab2,\n+\tBNXT_ULP_CLASS_HID_57fe = 0x57fe,\n+\tBNXT_ULP_CLASS_HID_50ca = 0x50ca,\n+\tBNXT_ULP_CLASS_HID_029a = 0x029a,\n+\tBNXT_ULP_CLASS_HID_1fe6 = 0x1fe6,\n+\tBNXT_ULP_CLASS_HID_1832 = 0x1832,\n+\tBNXT_ULP_CLASS_HID_157e = 0x157e,\n+\tBNXT_ULP_CLASS_HID_582e = 0x582e,\n+\tBNXT_ULP_CLASS_HID_557a = 0x557a,\n+\tBNXT_ULP_CLASS_HID_2e46 = 0x2e46,\n+\tBNXT_ULP_CLASS_HID_2a92 = 0x2a92,\n+\tBNXT_ULP_CLASS_HID_38c6 = 0x38c6,\n+\tBNXT_ULP_CLASS_HID_3512 = 0x3512,\n+\tBNXT_ULP_CLASS_HID_0e5e = 0x0e5e,\n+\tBNXT_ULP_CLASS_HID_0aaa = 0x0aaa,\n+\tBNXT_ULP_CLASS_HID_5822 = 0x5822,\n+\tBNXT_ULP_CLASS_HID_556e = 0x556e,\n+\tBNXT_ULP_CLASS_HID_51ba = 0x51ba,\n+\tBNXT_ULP_CLASS_HID_2a86 = 0x2a86,\n+\tBNXT_ULP_CLASS_HID_1d56 = 0x1d56,\n+\tBNXT_ULP_CLASS_HID_19a2 = 0x19a2,\n+\tBNXT_ULP_CLASS_HID_12ee = 0x12ee,\n+\tBNXT_ULP_CLASS_HID_4aee = 0x4aee,\n+\tBNXT_ULP_CLASS_HID_52ea = 0x52ea,\n+\tBNXT_ULP_CLASS_HID_2f36 = 0x2f36,\n+\tBNXT_ULP_CLASS_HID_2802 = 0x2802,\n+\tBNXT_ULP_CLASS_HID_254e = 0x254e,\n+\tBNXT_ULP_CLASS_HID_3282 = 0x3282,\n+\tBNXT_ULP_CLASS_HID_0fce = 0x0fce,\n+\tBNXT_ULP_CLASS_HID_081a = 0x081a,\n+\tBNXT_ULP_CLASS_HID_0566 = 0x0566,\n+\tBNXT_ULP_CLASS_HID_34d6 = 0x34d6,\n+\tBNXT_ULP_CLASS_HID_3a1a = 0x3a1a,\n+\tBNXT_ULP_CLASS_HID_09aa = 0x09aa,\n+\tBNXT_ULP_CLASS_HID_0276 = 0x0276,\n+\tBNXT_ULP_CLASS_HID_1f02 = 0x1f02,\n+\tBNXT_ULP_CLASS_HID_1bce = 0x1bce,\n+\tBNXT_ULP_CLASS_HID_2952 = 0x2952,\n+\tBNXT_ULP_CLASS_HID_221e = 0x221e,\n+\tBNXT_ULP_CLASS_HID_3f2a = 0x3f2a,\n+\tBNXT_ULP_CLASS_HID_3bf6 = 0x3bf6,\n+\tBNXT_ULP_CLASS_HID_03f2 = 0x03f2,\n+\tBNXT_ULP_CLASS_HID_1cbe = 0x1cbe,\n+\tBNXT_ULP_CLASS_HID_194a = 0x194a,\n+\tBNXT_ULP_CLASS_HID_1216 = 0x1216,\n+\tBNXT_ULP_CLASS_HID_5f3e = 0x5f3e,\n+\tBNXT_ULP_CLASS_HID_5bca = 0x5bca,\n+\tBNXT_ULP_CLASS_HID_5496 = 0x5496,\n+\tBNXT_ULP_CLASS_HID_51a2 = 0x51a2,\n+\tBNXT_ULP_CLASS_HID_03e6 = 0x03e6,\n+\tBNXT_ULP_CLASS_HID_1cb2 = 0x1cb2,\n+\tBNXT_ULP_CLASS_HID_197e = 0x197e,\n+\tBNXT_ULP_CLASS_HID_120a = 0x120a,\n+\tBNXT_ULP_CLASS_HID_238e = 0x238e,\n+\tBNXT_ULP_CLASS_HID_3c5a = 0x3c5a,\n+\tBNXT_ULP_CLASS_HID_3966 = 0x3966,\n+\tBNXT_ULP_CLASS_HID_3232 = 0x3232,\n+\tBNXT_ULP_CLASS_HID_1a2e = 0x1a2e,\n+\tBNXT_ULP_CLASS_HID_16fa = 0x16fa,\n+\tBNXT_ULP_CLASS_HID_1386 = 0x1386,\n+\tBNXT_ULP_CLASS_HID_4b86 = 0x4b86,\n+\tBNXT_ULP_CLASS_HID_597a = 0x597a,\n+\tBNXT_ULP_CLASS_HID_5206 = 0x5206,\n+\tBNXT_ULP_CLASS_HID_2ed2 = 0x2ed2,\n+\tBNXT_ULP_CLASS_HID_2b9e = 0x2b9e,\n+\tBNXT_ULP_CLASS_HID_4d8e = 0x4d8e,\n+\tBNXT_ULP_CLASS_HID_465a = 0x465a,\n+\tBNXT_ULP_CLASS_HID_4366 = 0x4366,\n+\tBNXT_ULP_CLASS_HID_5c32 = 0x5c32,\n+\tBNXT_ULP_CLASS_HID_0e42 = 0x0e42,\n+\tBNXT_ULP_CLASS_HID_0b0e = 0x0b0e,\n+\tBNXT_ULP_CLASS_HID_07da = 0x07da,\n \tBNXT_ULP_CLASS_HID_00e6 = 0x00e6,\n-\tBNXT_ULP_CLASS_HID_009c = 0x009c,\n-\tBNXT_ULP_CLASS_HID_005e = 0x005e,\n-\tBNXT_ULP_CLASS_HID_01f4 = 0x01f4,\n-\tBNXT_ULP_CLASS_HID_01b6 = 0x01b6\n+\tBNXT_ULP_CLASS_HID_47d6 = 0x47d6,\n+\tBNXT_ULP_CLASS_HID_40e2 = 0x40e2,\n+\tBNXT_ULP_CLASS_HID_5dae = 0x5dae,\n+\tBNXT_ULP_CLASS_HID_567a = 0x567a,\n+\tBNXT_ULP_CLASS_HID_242e = 0x242e,\n+\tBNXT_ULP_CLASS_HID_20fa = 0x20fa,\n+\tBNXT_ULP_CLASS_HID_3d86 = 0x3d86,\n+\tBNXT_ULP_CLASS_HID_3652 = 0x3652,\n+\tBNXT_ULP_CLASS_HID_47ca = 0x47ca,\n+\tBNXT_ULP_CLASS_HID_4096 = 0x4096,\n+\tBNXT_ULP_CLASS_HID_5da2 = 0x5da2,\n+\tBNXT_ULP_CLASS_HID_566e = 0x566e,\n+\tBNXT_ULP_CLASS_HID_08be = 0x08be,\n+\tBNXT_ULP_CLASS_HID_054a = 0x054a,\n+\tBNXT_ULP_CLASS_HID_1e16 = 0x1e16,\n+\tBNXT_ULP_CLASS_HID_1b22 = 0x1b22,\n+\tBNXT_ULP_CLASS_HID_5e12 = 0x5e12,\n+\tBNXT_ULP_CLASS_HID_5ade = 0x5ade,\n+\tBNXT_ULP_CLASS_HID_57ea = 0x57ea,\n+\tBNXT_ULP_CLASS_HID_50b6 = 0x50b6,\n+\tBNXT_ULP_CLASS_HID_3e6a = 0x3e6a,\n+\tBNXT_ULP_CLASS_HID_3b36 = 0x3b36,\n+\tBNXT_ULP_CLASS_HID_37c2 = 0x37c2,\n+\tBNXT_ULP_CLASS_HID_308e = 0x308e,\n+\tBNXT_ULP_CLASS_HID_5e06 = 0x5e06,\n+\tBNXT_ULP_CLASS_HID_5ad2 = 0x5ad2,\n+\tBNXT_ULP_CLASS_HID_579e = 0x579e,\n+\tBNXT_ULP_CLASS_HID_50aa = 0x50aa,\n+\tBNXT_ULP_CLASS_HID_02fa = 0x02fa,\n+\tBNXT_ULP_CLASS_HID_1f86 = 0x1f86,\n+\tBNXT_ULP_CLASS_HID_1852 = 0x1852,\n+\tBNXT_ULP_CLASS_HID_151e = 0x151e,\n+\tBNXT_ULP_CLASS_HID_584e = 0x584e,\n+\tBNXT_ULP_CLASS_HID_551a = 0x551a,\n+\tBNXT_ULP_CLASS_HID_2e26 = 0x2e26,\n+\tBNXT_ULP_CLASS_HID_2af2 = 0x2af2,\n+\tBNXT_ULP_CLASS_HID_38a6 = 0x38a6,\n+\tBNXT_ULP_CLASS_HID_3572 = 0x3572,\n+\tBNXT_ULP_CLASS_HID_0e3e = 0x0e3e,\n+\tBNXT_ULP_CLASS_HID_0aca = 0x0aca,\n+\tBNXT_ULP_CLASS_HID_5842 = 0x5842,\n+\tBNXT_ULP_CLASS_HID_550e = 0x550e,\n+\tBNXT_ULP_CLASS_HID_51da = 0x51da,\n+\tBNXT_ULP_CLASS_HID_2ae6 = 0x2ae6,\n+\tBNXT_ULP_CLASS_HID_1d36 = 0x1d36,\n+\tBNXT_ULP_CLASS_HID_19c2 = 0x19c2,\n+\tBNXT_ULP_CLASS_HID_128e = 0x128e,\n+\tBNXT_ULP_CLASS_HID_4a8e = 0x4a8e,\n+\tBNXT_ULP_CLASS_HID_528a = 0x528a,\n+\tBNXT_ULP_CLASS_HID_2f56 = 0x2f56,\n+\tBNXT_ULP_CLASS_HID_2862 = 0x2862,\n+\tBNXT_ULP_CLASS_HID_252e = 0x252e,\n+\tBNXT_ULP_CLASS_HID_32e2 = 0x32e2,\n+\tBNXT_ULP_CLASS_HID_0fae = 0x0fae,\n+\tBNXT_ULP_CLASS_HID_087a = 0x087a,\n+\tBNXT_ULP_CLASS_HID_0506 = 0x0506,\n+\tBNXT_ULP_CLASS_HID_34b6 = 0x34b6,\n+\tBNXT_ULP_CLASS_HID_3a7a = 0x3a7a,\n+\tBNXT_ULP_CLASS_HID_a73c = 0xa73c,\n+\tBNXT_ULP_CLASS_HID_a040 = 0xa040,\n+\tBNXT_ULP_CLASS_HID_1d640 = 0x1d640,\n+\tBNXT_ULP_CLASS_HID_1dd3c = 0x1dd3c,\n+\tBNXT_ULP_CLASS_HID_cba0 = 0xcba0,\n+\tBNXT_ULP_CLASS_HID_c4f4 = 0xc4f4,\n+\tBNXT_ULP_CLASS_HID_19f38 = 0x19f38,\n+\tBNXT_ULP_CLASS_HID_182f4 = 0x182f4,\n+\tBNXT_ULP_CLASS_HID_b098 = 0xb098,\n+\tBNXT_ULP_CLASS_HID_8dac = 0x8dac,\n+\tBNXT_ULP_CLASS_HID_1a3ac = 0x1a3ac,\n+\tBNXT_ULP_CLASS_HID_1a698 = 0x1a698,\n+\tBNXT_ULP_CLASS_HID_d50c = 0xd50c,\n+\tBNXT_ULP_CLASS_HID_ae50 = 0xae50,\n+\tBNXT_ULP_CLASS_HID_1c450 = 0x1c450,\n+\tBNXT_ULP_CLASS_HID_1cb0c = 0x1cb0c,\n+\tBNXT_ULP_CLASS_HID_a1f0 = 0xa1f0,\n+\tBNXT_ULP_CLASS_HID_ba04 = 0xba04,\n+\tBNXT_ULP_CLASS_HID_1d004 = 0x1d004,\n+\tBNXT_ULP_CLASS_HID_1d7f0 = 0x1d7f0,\n+\tBNXT_ULP_CLASS_HID_c264 = 0xc264,\n+\tBNXT_ULP_CLASS_HID_dea8 = 0xdea8,\n+\tBNXT_ULP_CLASS_HID_199fc = 0x199fc,\n+\tBNXT_ULP_CLASS_HID_19ca8 = 0x19ca8,\n+\tBNXT_ULP_CLASS_HID_8b5c = 0x8b5c,\n+\tBNXT_ULP_CLASS_HID_8460 = 0x8460,\n+\tBNXT_ULP_CLASS_HID_1ba60 = 0x1ba60,\n+\tBNXT_ULP_CLASS_HID_1a15c = 0x1a15c,\n+\tBNXT_ULP_CLASS_HID_afc0 = 0xafc0,\n+\tBNXT_ULP_CLASS_HID_a814 = 0xa814,\n+\tBNXT_ULP_CLASS_HID_1de14 = 0x1de14,\n+\tBNXT_ULP_CLASS_HID_1c5c0 = 0x1c5c0,\n+\tBNXT_ULP_CLASS_HID_8c2c = 0x8c2c,\n+\tBNXT_ULP_CLASS_HID_8970 = 0x8970,\n+\tBNXT_ULP_CLASS_HID_1bf70 = 0x1bf70,\n+\tBNXT_ULP_CLASS_HID_1a22c = 0x1a22c,\n+\tBNXT_ULP_CLASS_HID_d0d0 = 0xd0d0,\n+\tBNXT_ULP_CLASS_HID_ade4 = 0xade4,\n+\tBNXT_ULP_CLASS_HID_1c3e4 = 0x1c3e4,\n+\tBNXT_ULP_CLASS_HID_1c6d0 = 0x1c6d0,\n+\tBNXT_ULP_CLASS_HID_9988 = 0x9988,\n+\tBNXT_ULP_CLASS_HID_92dc = 0x92dc,\n+\tBNXT_ULP_CLASS_HID_188dc = 0x188dc,\n+\tBNXT_ULP_CLASS_HID_18f88 = 0x18f88,\n+\tBNXT_ULP_CLASS_HID_ba3c = 0xba3c,\n+\tBNXT_ULP_CLASS_HID_b740 = 0xb740,\n+\tBNXT_ULP_CLASS_HID_1ad40 = 0x1ad40,\n+\tBNXT_ULP_CLASS_HID_1d03c = 0x1d03c,\n+\tBNXT_ULP_CLASS_HID_86e0 = 0x86e0,\n+\tBNXT_ULP_CLASS_HID_8334 = 0x8334,\n+\tBNXT_ULP_CLASS_HID_1b934 = 0x1b934,\n+\tBNXT_ULP_CLASS_HID_1bce0 = 0x1bce0,\n+\tBNXT_ULP_CLASS_HID_aa94 = 0xaa94,\n+\tBNXT_ULP_CLASS_HID_a7d8 = 0xa7d8,\n+\tBNXT_ULP_CLASS_HID_1ddd8 = 0x1ddd8,\n+\tBNXT_ULP_CLASS_HID_1c094 = 0x1c094,\n+\tBNXT_ULP_CLASS_HID_904c = 0x904c,\n+\tBNXT_ULP_CLASS_HID_c84c = 0xc84c,\n+\tBNXT_ULP_CLASS_HID_18290 = 0x18290,\n+\tBNXT_ULP_CLASS_HID_1864c = 0x1864c,\n+\tBNXT_ULP_CLASS_HID_b4f0 = 0xb4f0,\n+\tBNXT_ULP_CLASS_HID_b104 = 0xb104,\n+\tBNXT_ULP_CLASS_HID_1a704 = 0x1a704,\n+\tBNXT_ULP_CLASS_HID_1aaf0 = 0x1aaf0,\n+\tBNXT_ULP_CLASS_HID_80a4 = 0x80a4,\n+\tBNXT_ULP_CLASS_HID_9de8 = 0x9de8,\n+\tBNXT_ULP_CLASS_HID_1b3e8 = 0x1b3e8,\n+\tBNXT_ULP_CLASS_HID_1b6a4 = 0x1b6a4,\n+\tBNXT_ULP_CLASS_HID_a548 = 0xa548,\n+\tBNXT_ULP_CLASS_HID_a19c = 0xa19c,\n+\tBNXT_ULP_CLASS_HID_1d79c = 0x1d79c,\n+\tBNXT_ULP_CLASS_HID_1db48 = 0x1db48,\n+\tBNXT_ULP_CLASS_HID_9a98 = 0x9a98,\n+\tBNXT_ULP_CLASS_HID_97ac = 0x97ac,\n+\tBNXT_ULP_CLASS_HID_18dac = 0x18dac,\n+\tBNXT_ULP_CLASS_HID_1b098 = 0x1b098,\n+\tBNXT_ULP_CLASS_HID_bf0c = 0xbf0c,\n+\tBNXT_ULP_CLASS_HID_b850 = 0xb850,\n+\tBNXT_ULP_CLASS_HID_1ae50 = 0x1ae50,\n+\tBNXT_ULP_CLASS_HID_1d50c = 0x1d50c,\n+\tBNXT_ULP_CLASS_HID_34f0 = 0x34f0,\n+\tBNXT_ULP_CLASS_HID_3a3c = 0x3a3c,\n+\tBNXT_ULP_CLASS_HID_5ea0 = 0x5ea0,\n+\tBNXT_ULP_CLASS_HID_0798 = 0x0798,\n+\tBNXT_ULP_CLASS_HID_280c = 0x280c,\n+\tBNXT_ULP_CLASS_HID_5964 = 0x5964,\n+\tBNXT_ULP_CLASS_HID_1e5c = 0x1e5c,\n+\tBNXT_ULP_CLASS_HID_22c0 = 0x22c0,\n+\tBNXT_ULP_CLASS_HID_a71c = 0xa71c,\n+\tBNXT_ULP_CLASS_HID_a8dc = 0xa8dc,\n+\tBNXT_ULP_CLASS_HID_ed9c = 0xed9c,\n+\tBNXT_ULP_CLASS_HID_ef5c = 0xef5c,\n+\tBNXT_ULP_CLASS_HID_a060 = 0xa060,\n+\tBNXT_ULP_CLASS_HID_a520 = 0xa520,\n+\tBNXT_ULP_CLASS_HID_e6e0 = 0xe6e0,\n+\tBNXT_ULP_CLASS_HID_eba0 = 0xeba0,\n+\tBNXT_ULP_CLASS_HID_1d660 = 0x1d660,\n+\tBNXT_ULP_CLASS_HID_1fb20 = 0x1fb20,\n+\tBNXT_ULP_CLASS_HID_1dce0 = 0x1dce0,\n+\tBNXT_ULP_CLASS_HID_1e1a0 = 0x1e1a0,\n+\tBNXT_ULP_CLASS_HID_1dd1c = 0x1dd1c,\n+\tBNXT_ULP_CLASS_HID_1fedc = 0x1fedc,\n+\tBNXT_ULP_CLASS_HID_1c39c = 0x1c39c,\n+\tBNXT_ULP_CLASS_HID_1e55c = 0x1e55c,\n+\tBNXT_ULP_CLASS_HID_cb80 = 0xcb80,\n+\tBNXT_ULP_CLASS_HID_b194 = 0xb194,\n+\tBNXT_ULP_CLASS_HID_d354 = 0xd354,\n+\tBNXT_ULP_CLASS_HID_f414 = 0xf414,\n+\tBNXT_ULP_CLASS_HID_c4d4 = 0xc4d4,\n+\tBNXT_ULP_CLASS_HID_e994 = 0xe994,\n+\tBNXT_ULP_CLASS_HID_cb54 = 0xcb54,\n+\tBNXT_ULP_CLASS_HID_f158 = 0xf158,\n+\tBNXT_ULP_CLASS_HID_19f18 = 0x19f18,\n+\tBNXT_ULP_CLASS_HID_1a0d8 = 0x1a0d8,\n+\tBNXT_ULP_CLASS_HID_1c598 = 0x1c598,\n+\tBNXT_ULP_CLASS_HID_1e758 = 0x1e758,\n+\tBNXT_ULP_CLASS_HID_182d4 = 0x182d4,\n+\tBNXT_ULP_CLASS_HID_1a794 = 0x1a794,\n+\tBNXT_ULP_CLASS_HID_1c954 = 0x1c954,\n+\tBNXT_ULP_CLASS_HID_1ea14 = 0x1ea14,\n+\tBNXT_ULP_CLASS_HID_b0b8 = 0xb0b8,\n+\tBNXT_ULP_CLASS_HID_b278 = 0xb278,\n+\tBNXT_ULP_CLASS_HID_f738 = 0xf738,\n+\tBNXT_ULP_CLASS_HID_f8f8 = 0xf8f8,\n+\tBNXT_ULP_CLASS_HID_8d8c = 0x8d8c,\n+\tBNXT_ULP_CLASS_HID_af4c = 0xaf4c,\n+\tBNXT_ULP_CLASS_HID_f00c = 0xf00c,\n+\tBNXT_ULP_CLASS_HID_f5cc = 0xf5cc,\n+\tBNXT_ULP_CLASS_HID_1a38c = 0x1a38c,\n+\tBNXT_ULP_CLASS_HID_1a54c = 0x1a54c,\n+\tBNXT_ULP_CLASS_HID_1e60c = 0x1e60c,\n+\tBNXT_ULP_CLASS_HID_1ebcc = 0x1ebcc,\n+\tBNXT_ULP_CLASS_HID_1a6b8 = 0x1a6b8,\n+\tBNXT_ULP_CLASS_HID_1a878 = 0x1a878,\n+\tBNXT_ULP_CLASS_HID_1ed38 = 0x1ed38,\n+\tBNXT_ULP_CLASS_HID_1eef8 = 0x1eef8,\n+\tBNXT_ULP_CLASS_HID_d52c = 0xd52c,\n+\tBNXT_ULP_CLASS_HID_f6ec = 0xf6ec,\n+\tBNXT_ULP_CLASS_HID_dbac = 0xdbac,\n+\tBNXT_ULP_CLASS_HID_fd6c = 0xfd6c,\n+\tBNXT_ULP_CLASS_HID_ae70 = 0xae70,\n+\tBNXT_ULP_CLASS_HID_f330 = 0xf330,\n+\tBNXT_ULP_CLASS_HID_d4f0 = 0xd4f0,\n+\tBNXT_ULP_CLASS_HID_f9b0 = 0xf9b0,\n+\tBNXT_ULP_CLASS_HID_1c470 = 0x1c470,\n+\tBNXT_ULP_CLASS_HID_1e930 = 0x1e930,\n+\tBNXT_ULP_CLASS_HID_1caf0 = 0x1caf0,\n+\tBNXT_ULP_CLASS_HID_1f084 = 0x1f084,\n+\tBNXT_ULP_CLASS_HID_1cb2c = 0x1cb2c,\n+\tBNXT_ULP_CLASS_HID_1b130 = 0x1b130,\n+\tBNXT_ULP_CLASS_HID_1d2f0 = 0x1d2f0,\n+\tBNXT_ULP_CLASS_HID_1f7b0 = 0x1f7b0,\n+\tBNXT_ULP_CLASS_HID_a1d0 = 0xa1d0,\n+\tBNXT_ULP_CLASS_HID_a290 = 0xa290,\n+\tBNXT_ULP_CLASS_HID_e450 = 0xe450,\n+\tBNXT_ULP_CLASS_HID_e910 = 0xe910,\n+\tBNXT_ULP_CLASS_HID_ba24 = 0xba24,\n+\tBNXT_ULP_CLASS_HID_bfe4 = 0xbfe4,\n+\tBNXT_ULP_CLASS_HID_e0a4 = 0xe0a4,\n+\tBNXT_ULP_CLASS_HID_e264 = 0xe264,\n+\tBNXT_ULP_CLASS_HID_1d024 = 0x1d024,\n+\tBNXT_ULP_CLASS_HID_1f5e4 = 0x1f5e4,\n+\tBNXT_ULP_CLASS_HID_1d6a4 = 0x1d6a4,\n+\tBNXT_ULP_CLASS_HID_1f864 = 0x1f864,\n+\tBNXT_ULP_CLASS_HID_1d7d0 = 0x1d7d0,\n+\tBNXT_ULP_CLASS_HID_1f890 = 0x1f890,\n+\tBNXT_ULP_CLASS_HID_1da50 = 0x1da50,\n+\tBNXT_ULP_CLASS_HID_1ff10 = 0x1ff10,\n+\tBNXT_ULP_CLASS_HID_c244 = 0xc244,\n+\tBNXT_ULP_CLASS_HID_e704 = 0xe704,\n+\tBNXT_ULP_CLASS_HID_c8c4 = 0xc8c4,\n+\tBNXT_ULP_CLASS_HID_ed84 = 0xed84,\n+\tBNXT_ULP_CLASS_HID_de88 = 0xde88,\n+\tBNXT_ULP_CLASS_HID_e048 = 0xe048,\n+\tBNXT_ULP_CLASS_HID_c508 = 0xc508,\n+\tBNXT_ULP_CLASS_HID_e6c8 = 0xe6c8,\n+\tBNXT_ULP_CLASS_HID_199dc = 0x199dc,\n+\tBNXT_ULP_CLASS_HID_1ba9c = 0x1ba9c,\n+\tBNXT_ULP_CLASS_HID_1dc5c = 0x1dc5c,\n+\tBNXT_ULP_CLASS_HID_1e11c = 0x1e11c,\n+\tBNXT_ULP_CLASS_HID_19c88 = 0x19c88,\n+\tBNXT_ULP_CLASS_HID_1be48 = 0x1be48,\n+\tBNXT_ULP_CLASS_HID_1c308 = 0x1c308,\n+\tBNXT_ULP_CLASS_HID_1e4c8 = 0x1e4c8,\n+\tBNXT_ULP_CLASS_HID_8b7c = 0x8b7c,\n+\tBNXT_ULP_CLASS_HID_ac3c = 0xac3c,\n+\tBNXT_ULP_CLASS_HID_f1fc = 0xf1fc,\n+\tBNXT_ULP_CLASS_HID_f2bc = 0xf2bc,\n+\tBNXT_ULP_CLASS_HID_8440 = 0x8440,\n+\tBNXT_ULP_CLASS_HID_a900 = 0xa900,\n+\tBNXT_ULP_CLASS_HID_cac0 = 0xcac0,\n+\tBNXT_ULP_CLASS_HID_ef80 = 0xef80,\n+\tBNXT_ULP_CLASS_HID_1ba40 = 0x1ba40,\n+\tBNXT_ULP_CLASS_HID_1bf00 = 0x1bf00,\n+\tBNXT_ULP_CLASS_HID_1e0c0 = 0x1e0c0,\n+\tBNXT_ULP_CLASS_HID_1e580 = 0x1e580,\n+\tBNXT_ULP_CLASS_HID_1a17c = 0x1a17c,\n+\tBNXT_ULP_CLASS_HID_1a23c = 0x1a23c,\n+\tBNXT_ULP_CLASS_HID_1e7fc = 0x1e7fc,\n+\tBNXT_ULP_CLASS_HID_1e8bc = 0x1e8bc,\n+\tBNXT_ULP_CLASS_HID_afe0 = 0xafe0,\n+\tBNXT_ULP_CLASS_HID_f0a0 = 0xf0a0,\n+\tBNXT_ULP_CLASS_HID_d260 = 0xd260,\n+\tBNXT_ULP_CLASS_HID_f720 = 0xf720,\n+\tBNXT_ULP_CLASS_HID_a834 = 0xa834,\n+\tBNXT_ULP_CLASS_HID_adf4 = 0xadf4,\n+\tBNXT_ULP_CLASS_HID_eeb4 = 0xeeb4,\n+\tBNXT_ULP_CLASS_HID_f074 = 0xf074,\n+\tBNXT_ULP_CLASS_HID_1de34 = 0x1de34,\n+\tBNXT_ULP_CLASS_HID_1e3f4 = 0x1e3f4,\n+\tBNXT_ULP_CLASS_HID_1c4b4 = 0x1c4b4,\n+\tBNXT_ULP_CLASS_HID_1e674 = 0x1e674,\n+\tBNXT_ULP_CLASS_HID_1c5e0 = 0x1c5e0,\n+\tBNXT_ULP_CLASS_HID_1e6a0 = 0x1e6a0,\n+\tBNXT_ULP_CLASS_HID_1c860 = 0x1c860,\n+\tBNXT_ULP_CLASS_HID_1ed20 = 0x1ed20,\n+\tBNXT_ULP_CLASS_HID_8c0c = 0x8c0c,\n+\tBNXT_ULP_CLASS_HID_b1cc = 0xb1cc,\n+\tBNXT_ULP_CLASS_HID_f28c = 0xf28c,\n+\tBNXT_ULP_CLASS_HID_f44c = 0xf44c,\n+\tBNXT_ULP_CLASS_HID_8950 = 0x8950,\n+\tBNXT_ULP_CLASS_HID_aa10 = 0xaa10,\n+\tBNXT_ULP_CLASS_HID_cfd0 = 0xcfd0,\n+\tBNXT_ULP_CLASS_HID_f090 = 0xf090,\n+\tBNXT_ULP_CLASS_HID_1bf50 = 0x1bf50,\n+\tBNXT_ULP_CLASS_HID_1a010 = 0x1a010,\n+\tBNXT_ULP_CLASS_HID_1e5d0 = 0x1e5d0,\n+\tBNXT_ULP_CLASS_HID_1e690 = 0x1e690,\n+\tBNXT_ULP_CLASS_HID_1a20c = 0x1a20c,\n+\tBNXT_ULP_CLASS_HID_1a7cc = 0x1a7cc,\n+\tBNXT_ULP_CLASS_HID_1e88c = 0x1e88c,\n+\tBNXT_ULP_CLASS_HID_1ea4c = 0x1ea4c,\n+\tBNXT_ULP_CLASS_HID_d0f0 = 0xd0f0,\n+\tBNXT_ULP_CLASS_HID_f5b0 = 0xf5b0,\n+\tBNXT_ULP_CLASS_HID_d770 = 0xd770,\n+\tBNXT_ULP_CLASS_HID_f830 = 0xf830,\n+\tBNXT_ULP_CLASS_HID_adc4 = 0xadc4,\n+\tBNXT_ULP_CLASS_HID_ae84 = 0xae84,\n+\tBNXT_ULP_CLASS_HID_d044 = 0xd044,\n+\tBNXT_ULP_CLASS_HID_f504 = 0xf504,\n+\tBNXT_ULP_CLASS_HID_1c3c4 = 0x1c3c4,\n+\tBNXT_ULP_CLASS_HID_1e484 = 0x1e484,\n+\tBNXT_ULP_CLASS_HID_1c644 = 0x1c644,\n+\tBNXT_ULP_CLASS_HID_1eb04 = 0x1eb04,\n+\tBNXT_ULP_CLASS_HID_1c6f0 = 0x1c6f0,\n+\tBNXT_ULP_CLASS_HID_1ebb0 = 0x1ebb0,\n+\tBNXT_ULP_CLASS_HID_1cd70 = 0x1cd70,\n+\tBNXT_ULP_CLASS_HID_1f304 = 0x1f304,\n+\tBNXT_ULP_CLASS_HID_99a8 = 0x99a8,\n+\tBNXT_ULP_CLASS_HID_bb68 = 0xbb68,\n+\tBNXT_ULP_CLASS_HID_dc28 = 0xdc28,\n+\tBNXT_ULP_CLASS_HID_e1e8 = 0xe1e8,\n+\tBNXT_ULP_CLASS_HID_92fc = 0x92fc,\n+\tBNXT_ULP_CLASS_HID_b7bc = 0xb7bc,\n+\tBNXT_ULP_CLASS_HID_d97c = 0xd97c,\n+\tBNXT_ULP_CLASS_HID_fa3c = 0xfa3c,\n+\tBNXT_ULP_CLASS_HID_188fc = 0x188fc,\n+\tBNXT_ULP_CLASS_HID_1adbc = 0x1adbc,\n+\tBNXT_ULP_CLASS_HID_1cf7c = 0x1cf7c,\n+\tBNXT_ULP_CLASS_HID_1f03c = 0x1f03c,\n+\tBNXT_ULP_CLASS_HID_18fa8 = 0x18fa8,\n+\tBNXT_ULP_CLASS_HID_1b168 = 0x1b168,\n+\tBNXT_ULP_CLASS_HID_1f228 = 0x1f228,\n+\tBNXT_ULP_CLASS_HID_1f7e8 = 0x1f7e8,\n+\tBNXT_ULP_CLASS_HID_ba1c = 0xba1c,\n+\tBNXT_ULP_CLASS_HID_bfdc = 0xbfdc,\n+\tBNXT_ULP_CLASS_HID_e09c = 0xe09c,\n+\tBNXT_ULP_CLASS_HID_e25c = 0xe25c,\n+\tBNXT_ULP_CLASS_HID_b760 = 0xb760,\n+\tBNXT_ULP_CLASS_HID_b820 = 0xb820,\n+\tBNXT_ULP_CLASS_HID_fde0 = 0xfde0,\n+\tBNXT_ULP_CLASS_HID_fea0 = 0xfea0,\n+\tBNXT_ULP_CLASS_HID_1ad60 = 0x1ad60,\n+\tBNXT_ULP_CLASS_HID_1ae20 = 0x1ae20,\n+\tBNXT_ULP_CLASS_HID_1d3e0 = 0x1d3e0,\n+\tBNXT_ULP_CLASS_HID_1f4a0 = 0x1f4a0,\n+\tBNXT_ULP_CLASS_HID_1d01c = 0x1d01c,\n+\tBNXT_ULP_CLASS_HID_1f5dc = 0x1f5dc,\n+\tBNXT_ULP_CLASS_HID_1d69c = 0x1d69c,\n+\tBNXT_ULP_CLASS_HID_1f85c = 0x1f85c,\n+\tBNXT_ULP_CLASS_HID_86c0 = 0x86c0,\n+\tBNXT_ULP_CLASS_HID_ab80 = 0xab80,\n+\tBNXT_ULP_CLASS_HID_cd40 = 0xcd40,\n+\tBNXT_ULP_CLASS_HID_ee00 = 0xee00,\n+\tBNXT_ULP_CLASS_HID_8314 = 0x8314,\n+\tBNXT_ULP_CLASS_HID_a4d4 = 0xa4d4,\n+\tBNXT_ULP_CLASS_HID_c994 = 0xc994,\n+\tBNXT_ULP_CLASS_HID_eb54 = 0xeb54,\n+\tBNXT_ULP_CLASS_HID_1b914 = 0x1b914,\n+\tBNXT_ULP_CLASS_HID_1bad4 = 0x1bad4,\n+\tBNXT_ULP_CLASS_HID_1ff94 = 0x1ff94,\n+\tBNXT_ULP_CLASS_HID_1e154 = 0x1e154,\n+\tBNXT_ULP_CLASS_HID_1bcc0 = 0x1bcc0,\n+\tBNXT_ULP_CLASS_HID_1a180 = 0x1a180,\n+\tBNXT_ULP_CLASS_HID_1e340 = 0x1e340,\n+\tBNXT_ULP_CLASS_HID_1e400 = 0x1e400,\n+\tBNXT_ULP_CLASS_HID_aab4 = 0xaab4,\n+\tBNXT_ULP_CLASS_HID_ac74 = 0xac74,\n+\tBNXT_ULP_CLASS_HID_d134 = 0xd134,\n+\tBNXT_ULP_CLASS_HID_f2f4 = 0xf2f4,\n+\tBNXT_ULP_CLASS_HID_a7f8 = 0xa7f8,\n+\tBNXT_ULP_CLASS_HID_a8b8 = 0xa8b8,\n+\tBNXT_ULP_CLASS_HID_ea78 = 0xea78,\n+\tBNXT_ULP_CLASS_HID_ef38 = 0xef38,\n+\tBNXT_ULP_CLASS_HID_1ddf8 = 0x1ddf8,\n+\tBNXT_ULP_CLASS_HID_1feb8 = 0x1feb8,\n+\tBNXT_ULP_CLASS_HID_1c078 = 0x1c078,\n+\tBNXT_ULP_CLASS_HID_1e538 = 0x1e538,\n+\tBNXT_ULP_CLASS_HID_1c0b4 = 0x1c0b4,\n+\tBNXT_ULP_CLASS_HID_1e274 = 0x1e274,\n+\tBNXT_ULP_CLASS_HID_1c734 = 0x1c734,\n+\tBNXT_ULP_CLASS_HID_1e8f4 = 0x1e8f4,\n+\tBNXT_ULP_CLASS_HID_906c = 0x906c,\n+\tBNXT_ULP_CLASS_HID_b52c = 0xb52c,\n+\tBNXT_ULP_CLASS_HID_d6ec = 0xd6ec,\n+\tBNXT_ULP_CLASS_HID_fbac = 0xfbac,\n+\tBNXT_ULP_CLASS_HID_c86c = 0xc86c,\n+\tBNXT_ULP_CLASS_HID_ed2c = 0xed2c,\n+\tBNXT_ULP_CLASS_HID_d330 = 0xd330,\n+\tBNXT_ULP_CLASS_HID_f4f0 = 0xf4f0,\n+\tBNXT_ULP_CLASS_HID_182b0 = 0x182b0,\n+\tBNXT_ULP_CLASS_HID_1a470 = 0x1a470,\n+\tBNXT_ULP_CLASS_HID_1c930 = 0x1c930,\n+\tBNXT_ULP_CLASS_HID_1eaf0 = 0x1eaf0,\n+\tBNXT_ULP_CLASS_HID_1866c = 0x1866c,\n+\tBNXT_ULP_CLASS_HID_1ab2c = 0x1ab2c,\n+\tBNXT_ULP_CLASS_HID_1ccec = 0x1ccec,\n+\tBNXT_ULP_CLASS_HID_1f1ac = 0x1f1ac,\n+\tBNXT_ULP_CLASS_HID_b4d0 = 0xb4d0,\n+\tBNXT_ULP_CLASS_HID_b990 = 0xb990,\n+\tBNXT_ULP_CLASS_HID_fb50 = 0xfb50,\n+\tBNXT_ULP_CLASS_HID_fc10 = 0xfc10,\n+\tBNXT_ULP_CLASS_HID_b124 = 0xb124,\n+\tBNXT_ULP_CLASS_HID_b2e4 = 0xb2e4,\n+\tBNXT_ULP_CLASS_HID_f7a4 = 0xf7a4,\n+\tBNXT_ULP_CLASS_HID_f964 = 0xf964,\n+\tBNXT_ULP_CLASS_HID_1a724 = 0x1a724,\n+\tBNXT_ULP_CLASS_HID_1a8e4 = 0x1a8e4,\n+\tBNXT_ULP_CLASS_HID_1eda4 = 0x1eda4,\n+\tBNXT_ULP_CLASS_HID_1ef64 = 0x1ef64,\n+\tBNXT_ULP_CLASS_HID_1aad0 = 0x1aad0,\n+\tBNXT_ULP_CLASS_HID_1af90 = 0x1af90,\n+\tBNXT_ULP_CLASS_HID_1d150 = 0x1d150,\n+\tBNXT_ULP_CLASS_HID_1f210 = 0x1f210,\n+\tBNXT_ULP_CLASS_HID_8084 = 0x8084,\n+\tBNXT_ULP_CLASS_HID_a244 = 0xa244,\n+\tBNXT_ULP_CLASS_HID_c704 = 0xc704,\n+\tBNXT_ULP_CLASS_HID_e8c4 = 0xe8c4,\n+\tBNXT_ULP_CLASS_HID_9dc8 = 0x9dc8,\n+\tBNXT_ULP_CLASS_HID_be88 = 0xbe88,\n+\tBNXT_ULP_CLASS_HID_c048 = 0xc048,\n+\tBNXT_ULP_CLASS_HID_e508 = 0xe508,\n+\tBNXT_ULP_CLASS_HID_1b3c8 = 0x1b3c8,\n+\tBNXT_ULP_CLASS_HID_1b488 = 0x1b488,\n+\tBNXT_ULP_CLASS_HID_1f648 = 0x1f648,\n+\tBNXT_ULP_CLASS_HID_1fb08 = 0x1fb08,\n+\tBNXT_ULP_CLASS_HID_1b684 = 0x1b684,\n+\tBNXT_ULP_CLASS_HID_1b844 = 0x1b844,\n+\tBNXT_ULP_CLASS_HID_1fd04 = 0x1fd04,\n+\tBNXT_ULP_CLASS_HID_1fec4 = 0x1fec4,\n+\tBNXT_ULP_CLASS_HID_a568 = 0xa568,\n+\tBNXT_ULP_CLASS_HID_a628 = 0xa628,\n+\tBNXT_ULP_CLASS_HID_ebe8 = 0xebe8,\n+\tBNXT_ULP_CLASS_HID_eca8 = 0xeca8,\n+\tBNXT_ULP_CLASS_HID_a1bc = 0xa1bc,\n+\tBNXT_ULP_CLASS_HID_a37c = 0xa37c,\n+\tBNXT_ULP_CLASS_HID_e43c = 0xe43c,\n+\tBNXT_ULP_CLASS_HID_e9fc = 0xe9fc,\n+\tBNXT_ULP_CLASS_HID_1d7bc = 0x1d7bc,\n+\tBNXT_ULP_CLASS_HID_1f97c = 0x1f97c,\n+\tBNXT_ULP_CLASS_HID_1da3c = 0x1da3c,\n+\tBNXT_ULP_CLASS_HID_1fffc = 0x1fffc,\n+\tBNXT_ULP_CLASS_HID_1db68 = 0x1db68,\n+\tBNXT_ULP_CLASS_HID_1fc28 = 0x1fc28,\n+\tBNXT_ULP_CLASS_HID_1c1e8 = 0x1c1e8,\n+\tBNXT_ULP_CLASS_HID_1e2a8 = 0x1e2a8,\n+\tBNXT_ULP_CLASS_HID_9ab8 = 0x9ab8,\n+\tBNXT_ULP_CLASS_HID_bc78 = 0xbc78,\n+\tBNXT_ULP_CLASS_HID_c138 = 0xc138,\n+\tBNXT_ULP_CLASS_HID_e2f8 = 0xe2f8,\n+\tBNXT_ULP_CLASS_HID_978c = 0x978c,\n+\tBNXT_ULP_CLASS_HID_b94c = 0xb94c,\n+\tBNXT_ULP_CLASS_HID_da0c = 0xda0c,\n+\tBNXT_ULP_CLASS_HID_ffcc = 0xffcc,\n+\tBNXT_ULP_CLASS_HID_18d8c = 0x18d8c,\n+\tBNXT_ULP_CLASS_HID_1af4c = 0x1af4c,\n+\tBNXT_ULP_CLASS_HID_1f00c = 0x1f00c,\n+\tBNXT_ULP_CLASS_HID_1f5cc = 0x1f5cc,\n+\tBNXT_ULP_CLASS_HID_1b0b8 = 0x1b0b8,\n+\tBNXT_ULP_CLASS_HID_1b278 = 0x1b278,\n+\tBNXT_ULP_CLASS_HID_1f738 = 0x1f738,\n+\tBNXT_ULP_CLASS_HID_1f8f8 = 0x1f8f8,\n+\tBNXT_ULP_CLASS_HID_bf2c = 0xbf2c,\n+\tBNXT_ULP_CLASS_HID_a0ec = 0xa0ec,\n+\tBNXT_ULP_CLASS_HID_e5ac = 0xe5ac,\n+\tBNXT_ULP_CLASS_HID_e76c = 0xe76c,\n+\tBNXT_ULP_CLASS_HID_b870 = 0xb870,\n+\tBNXT_ULP_CLASS_HID_bd30 = 0xbd30,\n+\tBNXT_ULP_CLASS_HID_fef0 = 0xfef0,\n+\tBNXT_ULP_CLASS_HID_e3b0 = 0xe3b0,\n+\tBNXT_ULP_CLASS_HID_1ae70 = 0x1ae70,\n+\tBNXT_ULP_CLASS_HID_1f330 = 0x1f330,\n+\tBNXT_ULP_CLASS_HID_1d4f0 = 0x1d4f0,\n+\tBNXT_ULP_CLASS_HID_1f9b0 = 0x1f9b0,\n+\tBNXT_ULP_CLASS_HID_1d52c = 0x1d52c,\n+\tBNXT_ULP_CLASS_HID_1f6ec = 0x1f6ec,\n+\tBNXT_ULP_CLASS_HID_1dbac = 0x1dbac,\n+\tBNXT_ULP_CLASS_HID_1fd6c = 0x1fd6c,\n+\tBNXT_ULP_CLASS_HID_34d0 = 0x34d0,\n+\tBNXT_ULP_CLASS_HID_3a1c = 0x3a1c,\n+\tBNXT_ULP_CLASS_HID_5e80 = 0x5e80,\n+\tBNXT_ULP_CLASS_HID_07b8 = 0x07b8,\n+\tBNXT_ULP_CLASS_HID_282c = 0x282c,\n+\tBNXT_ULP_CLASS_HID_5944 = 0x5944,\n+\tBNXT_ULP_CLASS_HID_1e7c = 0x1e7c,\n+\tBNXT_ULP_CLASS_HID_22e0 = 0x22e0,\n+\tBNXT_ULP_CLASS_HID_a77c = 0xa77c,\n+\tBNXT_ULP_CLASS_HID_a8bc = 0xa8bc,\n+\tBNXT_ULP_CLASS_HID_edfc = 0xedfc,\n+\tBNXT_ULP_CLASS_HID_ef3c = 0xef3c,\n+\tBNXT_ULP_CLASS_HID_a000 = 0xa000,\n+\tBNXT_ULP_CLASS_HID_a540 = 0xa540,\n+\tBNXT_ULP_CLASS_HID_e680 = 0xe680,\n+\tBNXT_ULP_CLASS_HID_ebc0 = 0xebc0,\n+\tBNXT_ULP_CLASS_HID_1d600 = 0x1d600,\n+\tBNXT_ULP_CLASS_HID_1fb40 = 0x1fb40,\n+\tBNXT_ULP_CLASS_HID_1dc80 = 0x1dc80,\n+\tBNXT_ULP_CLASS_HID_1e1c0 = 0x1e1c0,\n+\tBNXT_ULP_CLASS_HID_1dd7c = 0x1dd7c,\n+\tBNXT_ULP_CLASS_HID_1febc = 0x1febc,\n+\tBNXT_ULP_CLASS_HID_1c3fc = 0x1c3fc,\n+\tBNXT_ULP_CLASS_HID_1e53c = 0x1e53c,\n+\tBNXT_ULP_CLASS_HID_cbe0 = 0xcbe0,\n+\tBNXT_ULP_CLASS_HID_b1f4 = 0xb1f4,\n+\tBNXT_ULP_CLASS_HID_d334 = 0xd334,\n+\tBNXT_ULP_CLASS_HID_f474 = 0xf474,\n+\tBNXT_ULP_CLASS_HID_c4b4 = 0xc4b4,\n+\tBNXT_ULP_CLASS_HID_e9f4 = 0xe9f4,\n+\tBNXT_ULP_CLASS_HID_cb34 = 0xcb34,\n+\tBNXT_ULP_CLASS_HID_f138 = 0xf138,\n+\tBNXT_ULP_CLASS_HID_19f78 = 0x19f78,\n+\tBNXT_ULP_CLASS_HID_1a0b8 = 0x1a0b8,\n+\tBNXT_ULP_CLASS_HID_1c5f8 = 0x1c5f8,\n+\tBNXT_ULP_CLASS_HID_1e738 = 0x1e738,\n+\tBNXT_ULP_CLASS_HID_182b4 = 0x182b4,\n+\tBNXT_ULP_CLASS_HID_1a7f4 = 0x1a7f4,\n+\tBNXT_ULP_CLASS_HID_1c934 = 0x1c934,\n+\tBNXT_ULP_CLASS_HID_1ea74 = 0x1ea74,\n+\tBNXT_ULP_CLASS_HID_b0d8 = 0xb0d8,\n+\tBNXT_ULP_CLASS_HID_b218 = 0xb218,\n+\tBNXT_ULP_CLASS_HID_f758 = 0xf758,\n+\tBNXT_ULP_CLASS_HID_f898 = 0xf898,\n+\tBNXT_ULP_CLASS_HID_8dec = 0x8dec,\n+\tBNXT_ULP_CLASS_HID_af2c = 0xaf2c,\n+\tBNXT_ULP_CLASS_HID_f06c = 0xf06c,\n+\tBNXT_ULP_CLASS_HID_f5ac = 0xf5ac,\n+\tBNXT_ULP_CLASS_HID_1a3ec = 0x1a3ec,\n+\tBNXT_ULP_CLASS_HID_1a52c = 0x1a52c,\n+\tBNXT_ULP_CLASS_HID_1e66c = 0x1e66c,\n+\tBNXT_ULP_CLASS_HID_1ebac = 0x1ebac,\n+\tBNXT_ULP_CLASS_HID_1a6d8 = 0x1a6d8,\n+\tBNXT_ULP_CLASS_HID_1a818 = 0x1a818,\n+\tBNXT_ULP_CLASS_HID_1ed58 = 0x1ed58,\n+\tBNXT_ULP_CLASS_HID_1ee98 = 0x1ee98,\n+\tBNXT_ULP_CLASS_HID_d54c = 0xd54c,\n+\tBNXT_ULP_CLASS_HID_f68c = 0xf68c,\n+\tBNXT_ULP_CLASS_HID_dbcc = 0xdbcc,\n+\tBNXT_ULP_CLASS_HID_fd0c = 0xfd0c,\n+\tBNXT_ULP_CLASS_HID_ae10 = 0xae10,\n+\tBNXT_ULP_CLASS_HID_f350 = 0xf350,\n+\tBNXT_ULP_CLASS_HID_d490 = 0xd490,\n+\tBNXT_ULP_CLASS_HID_f9d0 = 0xf9d0,\n+\tBNXT_ULP_CLASS_HID_1c410 = 0x1c410,\n+\tBNXT_ULP_CLASS_HID_1e950 = 0x1e950,\n+\tBNXT_ULP_CLASS_HID_1ca90 = 0x1ca90,\n+\tBNXT_ULP_CLASS_HID_1f0e4 = 0x1f0e4,\n+\tBNXT_ULP_CLASS_HID_1cb4c = 0x1cb4c,\n+\tBNXT_ULP_CLASS_HID_1b150 = 0x1b150,\n+\tBNXT_ULP_CLASS_HID_1d290 = 0x1d290,\n+\tBNXT_ULP_CLASS_HID_1f7d0 = 0x1f7d0,\n+\tBNXT_ULP_CLASS_HID_a1b0 = 0xa1b0,\n+\tBNXT_ULP_CLASS_HID_a2f0 = 0xa2f0,\n+\tBNXT_ULP_CLASS_HID_e430 = 0xe430,\n+\tBNXT_ULP_CLASS_HID_e970 = 0xe970,\n+\tBNXT_ULP_CLASS_HID_ba44 = 0xba44,\n+\tBNXT_ULP_CLASS_HID_bf84 = 0xbf84,\n+\tBNXT_ULP_CLASS_HID_e0c4 = 0xe0c4,\n+\tBNXT_ULP_CLASS_HID_e204 = 0xe204,\n+\tBNXT_ULP_CLASS_HID_1d044 = 0x1d044,\n+\tBNXT_ULP_CLASS_HID_1f584 = 0x1f584,\n+\tBNXT_ULP_CLASS_HID_1d6c4 = 0x1d6c4,\n+\tBNXT_ULP_CLASS_HID_1f804 = 0x1f804,\n+\tBNXT_ULP_CLASS_HID_1d7b0 = 0x1d7b0,\n+\tBNXT_ULP_CLASS_HID_1f8f0 = 0x1f8f0,\n+\tBNXT_ULP_CLASS_HID_1da30 = 0x1da30,\n+\tBNXT_ULP_CLASS_HID_1ff70 = 0x1ff70,\n+\tBNXT_ULP_CLASS_HID_c224 = 0xc224,\n+\tBNXT_ULP_CLASS_HID_e764 = 0xe764,\n+\tBNXT_ULP_CLASS_HID_c8a4 = 0xc8a4,\n+\tBNXT_ULP_CLASS_HID_ede4 = 0xede4,\n+\tBNXT_ULP_CLASS_HID_dee8 = 0xdee8,\n+\tBNXT_ULP_CLASS_HID_e028 = 0xe028,\n+\tBNXT_ULP_CLASS_HID_c568 = 0xc568,\n+\tBNXT_ULP_CLASS_HID_e6a8 = 0xe6a8,\n+\tBNXT_ULP_CLASS_HID_199bc = 0x199bc,\n+\tBNXT_ULP_CLASS_HID_1bafc = 0x1bafc,\n+\tBNXT_ULP_CLASS_HID_1dc3c = 0x1dc3c,\n+\tBNXT_ULP_CLASS_HID_1e17c = 0x1e17c,\n+\tBNXT_ULP_CLASS_HID_19ce8 = 0x19ce8,\n+\tBNXT_ULP_CLASS_HID_1be28 = 0x1be28,\n+\tBNXT_ULP_CLASS_HID_1c368 = 0x1c368,\n+\tBNXT_ULP_CLASS_HID_1e4a8 = 0x1e4a8,\n+\tBNXT_ULP_CLASS_HID_8b1c = 0x8b1c,\n+\tBNXT_ULP_CLASS_HID_ac5c = 0xac5c,\n+\tBNXT_ULP_CLASS_HID_f19c = 0xf19c,\n+\tBNXT_ULP_CLASS_HID_f2dc = 0xf2dc,\n+\tBNXT_ULP_CLASS_HID_8420 = 0x8420,\n+\tBNXT_ULP_CLASS_HID_a960 = 0xa960,\n+\tBNXT_ULP_CLASS_HID_caa0 = 0xcaa0,\n+\tBNXT_ULP_CLASS_HID_efe0 = 0xefe0,\n+\tBNXT_ULP_CLASS_HID_1ba20 = 0x1ba20,\n+\tBNXT_ULP_CLASS_HID_1bf60 = 0x1bf60,\n+\tBNXT_ULP_CLASS_HID_1e0a0 = 0x1e0a0,\n+\tBNXT_ULP_CLASS_HID_1e5e0 = 0x1e5e0,\n+\tBNXT_ULP_CLASS_HID_1a11c = 0x1a11c,\n+\tBNXT_ULP_CLASS_HID_1a25c = 0x1a25c,\n+\tBNXT_ULP_CLASS_HID_1e79c = 0x1e79c,\n+\tBNXT_ULP_CLASS_HID_1e8dc = 0x1e8dc,\n+\tBNXT_ULP_CLASS_HID_af80 = 0xaf80,\n+\tBNXT_ULP_CLASS_HID_f0c0 = 0xf0c0,\n+\tBNXT_ULP_CLASS_HID_d200 = 0xd200,\n+\tBNXT_ULP_CLASS_HID_f740 = 0xf740,\n+\tBNXT_ULP_CLASS_HID_a854 = 0xa854,\n+\tBNXT_ULP_CLASS_HID_ad94 = 0xad94,\n+\tBNXT_ULP_CLASS_HID_eed4 = 0xeed4,\n+\tBNXT_ULP_CLASS_HID_f014 = 0xf014,\n+\tBNXT_ULP_CLASS_HID_1de54 = 0x1de54,\n+\tBNXT_ULP_CLASS_HID_1e394 = 0x1e394,\n+\tBNXT_ULP_CLASS_HID_1c4d4 = 0x1c4d4,\n+\tBNXT_ULP_CLASS_HID_1e614 = 0x1e614,\n+\tBNXT_ULP_CLASS_HID_1c580 = 0x1c580,\n+\tBNXT_ULP_CLASS_HID_1e6c0 = 0x1e6c0,\n+\tBNXT_ULP_CLASS_HID_1c800 = 0x1c800,\n+\tBNXT_ULP_CLASS_HID_1ed40 = 0x1ed40,\n+\tBNXT_ULP_CLASS_HID_8c6c = 0x8c6c,\n+\tBNXT_ULP_CLASS_HID_b1ac = 0xb1ac,\n+\tBNXT_ULP_CLASS_HID_f2ec = 0xf2ec,\n+\tBNXT_ULP_CLASS_HID_f42c = 0xf42c,\n+\tBNXT_ULP_CLASS_HID_8930 = 0x8930,\n+\tBNXT_ULP_CLASS_HID_aa70 = 0xaa70,\n+\tBNXT_ULP_CLASS_HID_cfb0 = 0xcfb0,\n+\tBNXT_ULP_CLASS_HID_f0f0 = 0xf0f0,\n+\tBNXT_ULP_CLASS_HID_1bf30 = 0x1bf30,\n+\tBNXT_ULP_CLASS_HID_1a070 = 0x1a070,\n+\tBNXT_ULP_CLASS_HID_1e5b0 = 0x1e5b0,\n+\tBNXT_ULP_CLASS_HID_1e6f0 = 0x1e6f0,\n+\tBNXT_ULP_CLASS_HID_1a26c = 0x1a26c,\n+\tBNXT_ULP_CLASS_HID_1a7ac = 0x1a7ac,\n+\tBNXT_ULP_CLASS_HID_1e8ec = 0x1e8ec,\n+\tBNXT_ULP_CLASS_HID_1ea2c = 0x1ea2c,\n+\tBNXT_ULP_CLASS_HID_d090 = 0xd090,\n+\tBNXT_ULP_CLASS_HID_f5d0 = 0xf5d0,\n+\tBNXT_ULP_CLASS_HID_d710 = 0xd710,\n+\tBNXT_ULP_CLASS_HID_f850 = 0xf850,\n+\tBNXT_ULP_CLASS_HID_ada4 = 0xada4,\n+\tBNXT_ULP_CLASS_HID_aee4 = 0xaee4,\n+\tBNXT_ULP_CLASS_HID_d024 = 0xd024,\n+\tBNXT_ULP_CLASS_HID_f564 = 0xf564,\n+\tBNXT_ULP_CLASS_HID_1c3a4 = 0x1c3a4,\n+\tBNXT_ULP_CLASS_HID_1e4e4 = 0x1e4e4,\n+\tBNXT_ULP_CLASS_HID_1c624 = 0x1c624,\n+\tBNXT_ULP_CLASS_HID_1eb64 = 0x1eb64,\n+\tBNXT_ULP_CLASS_HID_1c690 = 0x1c690,\n+\tBNXT_ULP_CLASS_HID_1ebd0 = 0x1ebd0,\n+\tBNXT_ULP_CLASS_HID_1cd10 = 0x1cd10,\n+\tBNXT_ULP_CLASS_HID_1f364 = 0x1f364,\n+\tBNXT_ULP_CLASS_HID_99c8 = 0x99c8,\n+\tBNXT_ULP_CLASS_HID_bb08 = 0xbb08,\n+\tBNXT_ULP_CLASS_HID_dc48 = 0xdc48,\n+\tBNXT_ULP_CLASS_HID_e188 = 0xe188,\n+\tBNXT_ULP_CLASS_HID_929c = 0x929c,\n+\tBNXT_ULP_CLASS_HID_b7dc = 0xb7dc,\n+\tBNXT_ULP_CLASS_HID_d91c = 0xd91c,\n+\tBNXT_ULP_CLASS_HID_fa5c = 0xfa5c,\n+\tBNXT_ULP_CLASS_HID_1889c = 0x1889c,\n+\tBNXT_ULP_CLASS_HID_1addc = 0x1addc,\n+\tBNXT_ULP_CLASS_HID_1cf1c = 0x1cf1c,\n+\tBNXT_ULP_CLASS_HID_1f05c = 0x1f05c,\n+\tBNXT_ULP_CLASS_HID_18fc8 = 0x18fc8,\n+\tBNXT_ULP_CLASS_HID_1b108 = 0x1b108,\n+\tBNXT_ULP_CLASS_HID_1f248 = 0x1f248,\n+\tBNXT_ULP_CLASS_HID_1f788 = 0x1f788,\n+\tBNXT_ULP_CLASS_HID_ba7c = 0xba7c,\n+\tBNXT_ULP_CLASS_HID_bfbc = 0xbfbc,\n+\tBNXT_ULP_CLASS_HID_e0fc = 0xe0fc,\n+\tBNXT_ULP_CLASS_HID_e23c = 0xe23c,\n+\tBNXT_ULP_CLASS_HID_b700 = 0xb700,\n+\tBNXT_ULP_CLASS_HID_b840 = 0xb840,\n+\tBNXT_ULP_CLASS_HID_fd80 = 0xfd80,\n+\tBNXT_ULP_CLASS_HID_fec0 = 0xfec0,\n+\tBNXT_ULP_CLASS_HID_1ad00 = 0x1ad00,\n+\tBNXT_ULP_CLASS_HID_1ae40 = 0x1ae40,\n+\tBNXT_ULP_CLASS_HID_1d380 = 0x1d380,\n+\tBNXT_ULP_CLASS_HID_1f4c0 = 0x1f4c0,\n+\tBNXT_ULP_CLASS_HID_1d07c = 0x1d07c,\n+\tBNXT_ULP_CLASS_HID_1f5bc = 0x1f5bc,\n+\tBNXT_ULP_CLASS_HID_1d6fc = 0x1d6fc,\n+\tBNXT_ULP_CLASS_HID_1f83c = 0x1f83c,\n+\tBNXT_ULP_CLASS_HID_86a0 = 0x86a0,\n+\tBNXT_ULP_CLASS_HID_abe0 = 0xabe0,\n+\tBNXT_ULP_CLASS_HID_cd20 = 0xcd20,\n+\tBNXT_ULP_CLASS_HID_ee60 = 0xee60,\n+\tBNXT_ULP_CLASS_HID_8374 = 0x8374,\n+\tBNXT_ULP_CLASS_HID_a4b4 = 0xa4b4,\n+\tBNXT_ULP_CLASS_HID_c9f4 = 0xc9f4,\n+\tBNXT_ULP_CLASS_HID_eb34 = 0xeb34,\n+\tBNXT_ULP_CLASS_HID_1b974 = 0x1b974,\n+\tBNXT_ULP_CLASS_HID_1bab4 = 0x1bab4,\n+\tBNXT_ULP_CLASS_HID_1fff4 = 0x1fff4,\n+\tBNXT_ULP_CLASS_HID_1e134 = 0x1e134,\n+\tBNXT_ULP_CLASS_HID_1bca0 = 0x1bca0,\n+\tBNXT_ULP_CLASS_HID_1a1e0 = 0x1a1e0,\n+\tBNXT_ULP_CLASS_HID_1e320 = 0x1e320,\n+\tBNXT_ULP_CLASS_HID_1e460 = 0x1e460,\n+\tBNXT_ULP_CLASS_HID_aad4 = 0xaad4,\n+\tBNXT_ULP_CLASS_HID_ac14 = 0xac14,\n+\tBNXT_ULP_CLASS_HID_d154 = 0xd154,\n+\tBNXT_ULP_CLASS_HID_f294 = 0xf294,\n+\tBNXT_ULP_CLASS_HID_a798 = 0xa798,\n+\tBNXT_ULP_CLASS_HID_a8d8 = 0xa8d8,\n+\tBNXT_ULP_CLASS_HID_ea18 = 0xea18,\n+\tBNXT_ULP_CLASS_HID_ef58 = 0xef58,\n+\tBNXT_ULP_CLASS_HID_1dd98 = 0x1dd98,\n+\tBNXT_ULP_CLASS_HID_1fed8 = 0x1fed8,\n+\tBNXT_ULP_CLASS_HID_1c018 = 0x1c018,\n+\tBNXT_ULP_CLASS_HID_1e558 = 0x1e558,\n+\tBNXT_ULP_CLASS_HID_1c0d4 = 0x1c0d4,\n+\tBNXT_ULP_CLASS_HID_1e214 = 0x1e214,\n+\tBNXT_ULP_CLASS_HID_1c754 = 0x1c754,\n+\tBNXT_ULP_CLASS_HID_1e894 = 0x1e894,\n+\tBNXT_ULP_CLASS_HID_900c = 0x900c,\n+\tBNXT_ULP_CLASS_HID_b54c = 0xb54c,\n+\tBNXT_ULP_CLASS_HID_d68c = 0xd68c,\n+\tBNXT_ULP_CLASS_HID_fbcc = 0xfbcc,\n+\tBNXT_ULP_CLASS_HID_c80c = 0xc80c,\n+\tBNXT_ULP_CLASS_HID_ed4c = 0xed4c,\n+\tBNXT_ULP_CLASS_HID_d350 = 0xd350,\n+\tBNXT_ULP_CLASS_HID_f490 = 0xf490,\n+\tBNXT_ULP_CLASS_HID_182d0 = 0x182d0,\n+\tBNXT_ULP_CLASS_HID_1a410 = 0x1a410,\n+\tBNXT_ULP_CLASS_HID_1c950 = 0x1c950,\n+\tBNXT_ULP_CLASS_HID_1ea90 = 0x1ea90,\n+\tBNXT_ULP_CLASS_HID_1860c = 0x1860c,\n+\tBNXT_ULP_CLASS_HID_1ab4c = 0x1ab4c,\n+\tBNXT_ULP_CLASS_HID_1cc8c = 0x1cc8c,\n+\tBNXT_ULP_CLASS_HID_1f1cc = 0x1f1cc,\n+\tBNXT_ULP_CLASS_HID_b4b0 = 0xb4b0,\n+\tBNXT_ULP_CLASS_HID_b9f0 = 0xb9f0,\n+\tBNXT_ULP_CLASS_HID_fb30 = 0xfb30,\n+\tBNXT_ULP_CLASS_HID_fc70 = 0xfc70,\n+\tBNXT_ULP_CLASS_HID_b144 = 0xb144,\n+\tBNXT_ULP_CLASS_HID_b284 = 0xb284,\n+\tBNXT_ULP_CLASS_HID_f7c4 = 0xf7c4,\n+\tBNXT_ULP_CLASS_HID_f904 = 0xf904,\n+\tBNXT_ULP_CLASS_HID_1a744 = 0x1a744,\n+\tBNXT_ULP_CLASS_HID_1a884 = 0x1a884,\n+\tBNXT_ULP_CLASS_HID_1edc4 = 0x1edc4,\n+\tBNXT_ULP_CLASS_HID_1ef04 = 0x1ef04,\n+\tBNXT_ULP_CLASS_HID_1aab0 = 0x1aab0,\n+\tBNXT_ULP_CLASS_HID_1aff0 = 0x1aff0,\n+\tBNXT_ULP_CLASS_HID_1d130 = 0x1d130,\n+\tBNXT_ULP_CLASS_HID_1f270 = 0x1f270,\n+\tBNXT_ULP_CLASS_HID_80e4 = 0x80e4,\n+\tBNXT_ULP_CLASS_HID_a224 = 0xa224,\n+\tBNXT_ULP_CLASS_HID_c764 = 0xc764,\n+\tBNXT_ULP_CLASS_HID_e8a4 = 0xe8a4,\n+\tBNXT_ULP_CLASS_HID_9da8 = 0x9da8,\n+\tBNXT_ULP_CLASS_HID_bee8 = 0xbee8,\n+\tBNXT_ULP_CLASS_HID_c028 = 0xc028,\n+\tBNXT_ULP_CLASS_HID_e568 = 0xe568,\n+\tBNXT_ULP_CLASS_HID_1b3a8 = 0x1b3a8,\n+\tBNXT_ULP_CLASS_HID_1b4e8 = 0x1b4e8,\n+\tBNXT_ULP_CLASS_HID_1f628 = 0x1f628,\n+\tBNXT_ULP_CLASS_HID_1fb68 = 0x1fb68,\n+\tBNXT_ULP_CLASS_HID_1b6e4 = 0x1b6e4,\n+\tBNXT_ULP_CLASS_HID_1b824 = 0x1b824,\n+\tBNXT_ULP_CLASS_HID_1fd64 = 0x1fd64,\n+\tBNXT_ULP_CLASS_HID_1fea4 = 0x1fea4,\n+\tBNXT_ULP_CLASS_HID_a508 = 0xa508,\n+\tBNXT_ULP_CLASS_HID_a648 = 0xa648,\n+\tBNXT_ULP_CLASS_HID_eb88 = 0xeb88,\n+\tBNXT_ULP_CLASS_HID_ecc8 = 0xecc8,\n+\tBNXT_ULP_CLASS_HID_a1dc = 0xa1dc,\n+\tBNXT_ULP_CLASS_HID_a31c = 0xa31c,\n+\tBNXT_ULP_CLASS_HID_e45c = 0xe45c,\n+\tBNXT_ULP_CLASS_HID_e99c = 0xe99c,\n+\tBNXT_ULP_CLASS_HID_1d7dc = 0x1d7dc,\n+\tBNXT_ULP_CLASS_HID_1f91c = 0x1f91c,\n+\tBNXT_ULP_CLASS_HID_1da5c = 0x1da5c,\n+\tBNXT_ULP_CLASS_HID_1ff9c = 0x1ff9c,\n+\tBNXT_ULP_CLASS_HID_1db08 = 0x1db08,\n+\tBNXT_ULP_CLASS_HID_1fc48 = 0x1fc48,\n+\tBNXT_ULP_CLASS_HID_1c188 = 0x1c188,\n+\tBNXT_ULP_CLASS_HID_1e2c8 = 0x1e2c8,\n+\tBNXT_ULP_CLASS_HID_9ad8 = 0x9ad8,\n+\tBNXT_ULP_CLASS_HID_bc18 = 0xbc18,\n+\tBNXT_ULP_CLASS_HID_c158 = 0xc158,\n+\tBNXT_ULP_CLASS_HID_e298 = 0xe298,\n+\tBNXT_ULP_CLASS_HID_97ec = 0x97ec,\n+\tBNXT_ULP_CLASS_HID_b92c = 0xb92c,\n+\tBNXT_ULP_CLASS_HID_da6c = 0xda6c,\n+\tBNXT_ULP_CLASS_HID_ffac = 0xffac,\n+\tBNXT_ULP_CLASS_HID_18dec = 0x18dec,\n+\tBNXT_ULP_CLASS_HID_1af2c = 0x1af2c,\n+\tBNXT_ULP_CLASS_HID_1f06c = 0x1f06c,\n+\tBNXT_ULP_CLASS_HID_1f5ac = 0x1f5ac,\n+\tBNXT_ULP_CLASS_HID_1b0d8 = 0x1b0d8,\n+\tBNXT_ULP_CLASS_HID_1b218 = 0x1b218,\n+\tBNXT_ULP_CLASS_HID_1f758 = 0x1f758,\n+\tBNXT_ULP_CLASS_HID_1f898 = 0x1f898,\n+\tBNXT_ULP_CLASS_HID_bf4c = 0xbf4c,\n+\tBNXT_ULP_CLASS_HID_a08c = 0xa08c,\n+\tBNXT_ULP_CLASS_HID_e5cc = 0xe5cc,\n+\tBNXT_ULP_CLASS_HID_e70c = 0xe70c,\n+\tBNXT_ULP_CLASS_HID_b810 = 0xb810,\n+\tBNXT_ULP_CLASS_HID_bd50 = 0xbd50,\n+\tBNXT_ULP_CLASS_HID_fe90 = 0xfe90,\n+\tBNXT_ULP_CLASS_HID_e3d0 = 0xe3d0,\n+\tBNXT_ULP_CLASS_HID_1ae10 = 0x1ae10,\n+\tBNXT_ULP_CLASS_HID_1f350 = 0x1f350,\n+\tBNXT_ULP_CLASS_HID_1d490 = 0x1d490,\n+\tBNXT_ULP_CLASS_HID_1f9d0 = 0x1f9d0,\n+\tBNXT_ULP_CLASS_HID_1d54c = 0x1d54c,\n+\tBNXT_ULP_CLASS_HID_1f68c = 0x1f68c,\n+\tBNXT_ULP_CLASS_HID_1dbcc = 0x1dbcc,\n+\tBNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c,\n+\tBNXT_ULP_CLASS_HID_34b0 = 0x34b0,\n+\tBNXT_ULP_CLASS_HID_3a7c = 0x3a7c,\n+\tBNXT_ULP_CLASS_HID_5ee0 = 0x5ee0,\n+\tBNXT_ULP_CLASS_HID_07d8 = 0x07d8,\n+\tBNXT_ULP_CLASS_HID_284c = 0x284c,\n+\tBNXT_ULP_CLASS_HID_5924 = 0x5924,\n+\tBNXT_ULP_CLASS_HID_1e1c = 0x1e1c,\n+\tBNXT_ULP_CLASS_HID_2280 = 0x2280,\n+\tBNXT_ULP_CLASS_HID_24604 = 0x24604,\n+\tBNXT_ULP_CLASS_HID_255d4 = 0x255d4,\n+\tBNXT_ULP_CLASS_HID_22e08 = 0x22e08,\n+\tBNXT_ULP_CLASS_HID_24378 = 0x24378,\n+\tBNXT_ULP_CLASS_HID_20fcc = 0x20fcc,\n+\tBNXT_ULP_CLASS_HID_21a9c = 0x21a9c,\n+\tBNXT_ULP_CLASS_HID_217d0 = 0x217d0,\n+\tBNXT_ULP_CLASS_HID_20800 = 0x20800,\n+\tBNXT_ULP_CLASS_HID_253a0 = 0x253a0,\n+\tBNXT_ULP_CLASS_HID_23f70 = 0x23f70,\n+\tBNXT_ULP_CLASS_HID_23ba4 = 0x23ba4,\n+\tBNXT_ULP_CLASS_HID_22c94 = 0x22c94,\n+\tBNXT_ULP_CLASS_HID_21968 = 0x21968,\n+\tBNXT_ULP_CLASS_HID_243c4 = 0x243c4,\n+\tBNXT_ULP_CLASS_HID_25c38 = 0x25c38,\n+\tBNXT_ULP_CLASS_HID_2125c = 0x2125c,\n+\tBNXT_ULP_CLASS_HID_240c8 = 0x240c8,\n+\tBNXT_ULP_CLASS_HID_22f98 = 0x22f98,\n+\tBNXT_ULP_CLASS_HID_228cc = 0x228cc,\n+\tBNXT_ULP_CLASS_HID_25d3c = 0x25d3c,\n+\tBNXT_ULP_CLASS_HID_20990 = 0x20990,\n+\tBNXT_ULP_CLASS_HID_214a0 = 0x214a0,\n+\tBNXT_ULP_CLASS_HID_21194 = 0x21194,\n+\tBNXT_ULP_CLASS_HID_202c4 = 0x202c4,\n+\tBNXT_ULP_CLASS_HID_22a64 = 0x22a64,\n+\tBNXT_ULP_CLASS_HID_23934 = 0x23934,\n+\tBNXT_ULP_CLASS_HID_23268 = 0x23268,\n+\tBNXT_ULP_CLASS_HID_22758 = 0x22758,\n+\tBNXT_ULP_CLASS_HID_2132c = 0x2132c,\n+\tBNXT_ULP_CLASS_HID_25d88 = 0x25d88,\n+\tBNXT_ULP_CLASS_HID_256fc = 0x256fc,\n+\tBNXT_ULP_CLASS_HID_24b2c = 0x24b2c,\n+\tBNXT_ULP_CLASS_HID_22f14 = 0x22f14,\n+\tBNXT_ULP_CLASS_HID_23a24 = 0x23a24,\n+\tBNXT_ULP_CLASS_HID_23718 = 0x23718,\n+\tBNXT_ULP_CLASS_HID_22848 = 0x22848,\n+\tBNXT_ULP_CLASS_HID_214dc = 0x214dc,\n+\tBNXT_ULP_CLASS_HID_25eb8 = 0x25eb8,\n+\tBNXT_ULP_CLASS_HID_25bec = 0x25bec,\n+\tBNXT_ULP_CLASS_HID_21110 = 0x21110,\n+\tBNXT_ULP_CLASS_HID_238b0 = 0x238b0,\n+\tBNXT_ULP_CLASS_HID_20440 = 0x20440,\n+\tBNXT_ULP_CLASS_HID_200b4 = 0x200b4,\n+\tBNXT_ULP_CLASS_HID_235e4 = 0x235e4,\n+\tBNXT_ULP_CLASS_HID_25d04 = 0x25d04,\n+\tBNXT_ULP_CLASS_HID_228d4 = 0x228d4,\n+\tBNXT_ULP_CLASS_HID_22508 = 0x22508,\n+\tBNXT_ULP_CLASS_HID_25678 = 0x25678,\n+\tBNXT_ULP_CLASS_HID_229d8 = 0x229d8,\n+\tBNXT_ULP_CLASS_HID_234e8 = 0x234e8,\n+\tBNXT_ULP_CLASS_HID_231dc = 0x231dc,\n+\tBNXT_ULP_CLASS_HID_2220c = 0x2220c,\n+\tBNXT_ULP_CLASS_HID_24dac = 0x24dac,\n+\tBNXT_ULP_CLASS_HID_2597c = 0x2597c,\n+\tBNXT_ULP_CLASS_HID_255b0 = 0x255b0,\n+\tBNXT_ULP_CLASS_HID_246e0 = 0x246e0,\n+\tBNXT_ULP_CLASS_HID_23374 = 0x23374,\n+\tBNXT_ULP_CLASS_HID_21e04 = 0x21e04,\n+\tBNXT_ULP_CLASS_HID_21b78 = 0x21b78,\n+\tBNXT_ULP_CLASS_HID_20fa8 = 0x20fa8,\n+\tBNXT_ULP_CLASS_HID_257c8 = 0x257c8,\n+\tBNXT_ULP_CLASS_HID_22298 = 0x22298,\n+\tBNXT_ULP_CLASS_HID_23fcc = 0x23fcc,\n+\tBNXT_ULP_CLASS_HID_2503c = 0x2503c,\n+\tBNXT_ULP_CLASS_HID_2239c = 0x2239c,\n+\tBNXT_ULP_CLASS_HID_20eac = 0x20eac,\n+\tBNXT_ULP_CLASS_HID_20be0 = 0x20be0,\n+\tBNXT_ULP_CLASS_HID_23cd0 = 0x23cd0,\n+\tBNXT_ULP_CLASS_HID_24470 = 0x24470,\n+\tBNXT_ULP_CLASS_HID_25300 = 0x25300,\n+\tBNXT_ULP_CLASS_HID_22c74 = 0x22c74,\n+\tBNXT_ULP_CLASS_HID_240a4 = 0x240a4,\n+\tBNXT_ULP_CLASS_HID_23da0 = 0x23da0,\n+\tBNXT_ULP_CLASS_HID_20970 = 0x20970,\n+\tBNXT_ULP_CLASS_HID_205a4 = 0x205a4,\n+\tBNXT_ULP_CLASS_HID_23694 = 0x23694,\n+\tBNXT_ULP_CLASS_HID_25e34 = 0x25e34,\n+\tBNXT_ULP_CLASS_HID_22dc4 = 0x22dc4,\n+\tBNXT_ULP_CLASS_HID_22638 = 0x22638,\n+\tBNXT_ULP_CLASS_HID_25b68 = 0x25b68,\n+\tBNXT_ULP_CLASS_HID_34c8 = 0x34c8,\n+\tBNXT_ULP_CLASS_HID_3a04 = 0x3a04,\n+\tBNXT_ULP_CLASS_HID_5e98 = 0x5e98,\n+\tBNXT_ULP_CLASS_HID_07a0 = 0x07a0,\n+\tBNXT_ULP_CLASS_HID_2834 = 0x2834,\n+\tBNXT_ULP_CLASS_HID_595c = 0x595c,\n+\tBNXT_ULP_CLASS_HID_1e64 = 0x1e64,\n+\tBNXT_ULP_CLASS_HID_22f8 = 0x22f8,\n+\tBNXT_ULP_CLASS_HID_24664 = 0x24664,\n+\tBNXT_ULP_CLASS_HID_29418 = 0x29418,\n+\tBNXT_ULP_CLASS_HID_30118 = 0x30118,\n+\tBNXT_ULP_CLASS_HID_38a18 = 0x38a18,\n+\tBNXT_ULP_CLASS_HID_255b4 = 0x255b4,\n+\tBNXT_ULP_CLASS_HID_2deb4 = 0x2deb4,\n+\tBNXT_ULP_CLASS_HID_34bb4 = 0x34bb4,\n+\tBNXT_ULP_CLASS_HID_39968 = 0x39968,\n+\tBNXT_ULP_CLASS_HID_22e68 = 0x22e68,\n+\tBNXT_ULP_CLASS_HID_2db68 = 0x2db68,\n+\tBNXT_ULP_CLASS_HID_34468 = 0x34468,\n+\tBNXT_ULP_CLASS_HID_3921c = 0x3921c,\n+\tBNXT_ULP_CLASS_HID_24318 = 0x24318,\n+\tBNXT_ULP_CLASS_HID_290cc = 0x290cc,\n+\tBNXT_ULP_CLASS_HID_31dcc = 0x31dcc,\n+\tBNXT_ULP_CLASS_HID_386cc = 0x386cc,\n+\tBNXT_ULP_CLASS_HID_20fac = 0x20fac,\n+\tBNXT_ULP_CLASS_HID_2b8ac = 0x2b8ac,\n+\tBNXT_ULP_CLASS_HID_325ac = 0x325ac,\n+\tBNXT_ULP_CLASS_HID_3aeac = 0x3aeac,\n+\tBNXT_ULP_CLASS_HID_21afc = 0x21afc,\n+\tBNXT_ULP_CLASS_HID_287fc = 0x287fc,\n+\tBNXT_ULP_CLASS_HID_330fc = 0x330fc,\n+\tBNXT_ULP_CLASS_HID_3bdfc = 0x3bdfc,\n+\tBNXT_ULP_CLASS_HID_217b0 = 0x217b0,\n+\tBNXT_ULP_CLASS_HID_280b0 = 0x280b0,\n+\tBNXT_ULP_CLASS_HID_30db0 = 0x30db0,\n+\tBNXT_ULP_CLASS_HID_3b6b0 = 0x3b6b0,\n+\tBNXT_ULP_CLASS_HID_20860 = 0x20860,\n+\tBNXT_ULP_CLASS_HID_2b560 = 0x2b560,\n+\tBNXT_ULP_CLASS_HID_33e60 = 0x33e60,\n+\tBNXT_ULP_CLASS_HID_3ab60 = 0x3ab60,\n+\tBNXT_ULP_CLASS_HID_253c0 = 0x253c0,\n+\tBNXT_ULP_CLASS_HID_2dcc0 = 0x2dcc0,\n+\tBNXT_ULP_CLASS_HID_349c0 = 0x349c0,\n+\tBNXT_ULP_CLASS_HID_397f4 = 0x397f4,\n+\tBNXT_ULP_CLASS_HID_23f10 = 0x23f10,\n+\tBNXT_ULP_CLASS_HID_2a810 = 0x2a810,\n+\tBNXT_ULP_CLASS_HID_35510 = 0x35510,\n+\tBNXT_ULP_CLASS_HID_3de10 = 0x3de10,\n+\tBNXT_ULP_CLASS_HID_23bc4 = 0x23bc4,\n+\tBNXT_ULP_CLASS_HID_2a4c4 = 0x2a4c4,\n+\tBNXT_ULP_CLASS_HID_351c4 = 0x351c4,\n+\tBNXT_ULP_CLASS_HID_3dac4 = 0x3dac4,\n+\tBNXT_ULP_CLASS_HID_22cf4 = 0x22cf4,\n+\tBNXT_ULP_CLASS_HID_2d9f4 = 0x2d9f4,\n+\tBNXT_ULP_CLASS_HID_342f4 = 0x342f4,\n+\tBNXT_ULP_CLASS_HID_390a8 = 0x390a8,\n+\tBNXT_ULP_CLASS_HID_21908 = 0x21908,\n+\tBNXT_ULP_CLASS_HID_28208 = 0x28208,\n+\tBNXT_ULP_CLASS_HID_30f08 = 0x30f08,\n+\tBNXT_ULP_CLASS_HID_3b808 = 0x3b808,\n+\tBNXT_ULP_CLASS_HID_243a4 = 0x243a4,\n+\tBNXT_ULP_CLASS_HID_29158 = 0x29158,\n+\tBNXT_ULP_CLASS_HID_31a58 = 0x31a58,\n+\tBNXT_ULP_CLASS_HID_38758 = 0x38758,\n+\tBNXT_ULP_CLASS_HID_25c58 = 0x25c58,\n+\tBNXT_ULP_CLASS_HID_2c958 = 0x2c958,\n+\tBNXT_ULP_CLASS_HID_3170c = 0x3170c,\n+\tBNXT_ULP_CLASS_HID_3800c = 0x3800c,\n+\tBNXT_ULP_CLASS_HID_2123c = 0x2123c,\n+\tBNXT_ULP_CLASS_HID_29f3c = 0x29f3c,\n+\tBNXT_ULP_CLASS_HID_3083c = 0x3083c,\n+\tBNXT_ULP_CLASS_HID_3b53c = 0x3b53c,\n+\tBNXT_ULP_CLASS_HID_240a8 = 0x240a8,\n+\tBNXT_ULP_CLASS_HID_2cda8 = 0x2cda8,\n+\tBNXT_ULP_CLASS_HID_31b5c = 0x31b5c,\n+\tBNXT_ULP_CLASS_HID_3845c = 0x3845c,\n+\tBNXT_ULP_CLASS_HID_22ff8 = 0x22ff8,\n+\tBNXT_ULP_CLASS_HID_2d8f8 = 0x2d8f8,\n+\tBNXT_ULP_CLASS_HID_345f8 = 0x345f8,\n+\tBNXT_ULP_CLASS_HID_393ac = 0x393ac,\n+\tBNXT_ULP_CLASS_HID_228ac = 0x228ac,\n+\tBNXT_ULP_CLASS_HID_2d5ac = 0x2d5ac,\n+\tBNXT_ULP_CLASS_HID_35eac = 0x35eac,\n+\tBNXT_ULP_CLASS_HID_3cbac = 0x3cbac,\n+\tBNXT_ULP_CLASS_HID_25d5c = 0x25d5c,\n+\tBNXT_ULP_CLASS_HID_2c65c = 0x2c65c,\n+\tBNXT_ULP_CLASS_HID_31410 = 0x31410,\n+\tBNXT_ULP_CLASS_HID_38110 = 0x38110,\n+\tBNXT_ULP_CLASS_HID_209f0 = 0x209f0,\n+\tBNXT_ULP_CLASS_HID_2b2f0 = 0x2b2f0,\n+\tBNXT_ULP_CLASS_HID_33ff0 = 0x33ff0,\n+\tBNXT_ULP_CLASS_HID_3a8f0 = 0x3a8f0,\n+\tBNXT_ULP_CLASS_HID_214c0 = 0x214c0,\n+\tBNXT_ULP_CLASS_HID_281c0 = 0x281c0,\n+\tBNXT_ULP_CLASS_HID_30ac0 = 0x30ac0,\n+\tBNXT_ULP_CLASS_HID_3b7c0 = 0x3b7c0,\n+\tBNXT_ULP_CLASS_HID_211f4 = 0x211f4,\n+\tBNXT_ULP_CLASS_HID_29af4 = 0x29af4,\n+\tBNXT_ULP_CLASS_HID_307f4 = 0x307f4,\n+\tBNXT_ULP_CLASS_HID_3b0f4 = 0x3b0f4,\n+\tBNXT_ULP_CLASS_HID_202a4 = 0x202a4,\n+\tBNXT_ULP_CLASS_HID_28fa4 = 0x28fa4,\n+\tBNXT_ULP_CLASS_HID_338a4 = 0x338a4,\n+\tBNXT_ULP_CLASS_HID_3a5a4 = 0x3a5a4,\n+\tBNXT_ULP_CLASS_HID_22a04 = 0x22a04,\n+\tBNXT_ULP_CLASS_HID_2d704 = 0x2d704,\n+\tBNXT_ULP_CLASS_HID_34004 = 0x34004,\n+\tBNXT_ULP_CLASS_HID_3cd04 = 0x3cd04,\n+\tBNXT_ULP_CLASS_HID_23954 = 0x23954,\n+\tBNXT_ULP_CLASS_HID_2a254 = 0x2a254,\n+\tBNXT_ULP_CLASS_HID_32f54 = 0x32f54,\n+\tBNXT_ULP_CLASS_HID_3d854 = 0x3d854,\n+\tBNXT_ULP_CLASS_HID_23208 = 0x23208,\n+\tBNXT_ULP_CLASS_HID_2bf08 = 0x2bf08,\n+\tBNXT_ULP_CLASS_HID_32808 = 0x32808,\n+\tBNXT_ULP_CLASS_HID_3d508 = 0x3d508,\n+\tBNXT_ULP_CLASS_HID_22738 = 0x22738,\n+\tBNXT_ULP_CLASS_HID_2d038 = 0x2d038,\n+\tBNXT_ULP_CLASS_HID_35d38 = 0x35d38,\n+\tBNXT_ULP_CLASS_HID_3c638 = 0x3c638,\n+\tBNXT_ULP_CLASS_HID_2134c = 0x2134c,\n+\tBNXT_ULP_CLASS_HID_29c4c = 0x29c4c,\n+\tBNXT_ULP_CLASS_HID_3094c = 0x3094c,\n+\tBNXT_ULP_CLASS_HID_3b24c = 0x3b24c,\n+\tBNXT_ULP_CLASS_HID_25de8 = 0x25de8,\n+\tBNXT_ULP_CLASS_HID_2c6e8 = 0x2c6e8,\n+\tBNXT_ULP_CLASS_HID_3149c = 0x3149c,\n+\tBNXT_ULP_CLASS_HID_3819c = 0x3819c,\n+\tBNXT_ULP_CLASS_HID_2569c = 0x2569c,\n+\tBNXT_ULP_CLASS_HID_2c39c = 0x2c39c,\n+\tBNXT_ULP_CLASS_HID_31150 = 0x31150,\n+\tBNXT_ULP_CLASS_HID_39a50 = 0x39a50,\n+\tBNXT_ULP_CLASS_HID_24b4c = 0x24b4c,\n+\tBNXT_ULP_CLASS_HID_29900 = 0x29900,\n+\tBNXT_ULP_CLASS_HID_30200 = 0x30200,\n+\tBNXT_ULP_CLASS_HID_38f00 = 0x38f00,\n+\tBNXT_ULP_CLASS_HID_22f74 = 0x22f74,\n+\tBNXT_ULP_CLASS_HID_2d874 = 0x2d874,\n+\tBNXT_ULP_CLASS_HID_34574 = 0x34574,\n+\tBNXT_ULP_CLASS_HID_39328 = 0x39328,\n+\tBNXT_ULP_CLASS_HID_23a44 = 0x23a44,\n+\tBNXT_ULP_CLASS_HID_2a744 = 0x2a744,\n+\tBNXT_ULP_CLASS_HID_35044 = 0x35044,\n+\tBNXT_ULP_CLASS_HID_3dd44 = 0x3dd44,\n+\tBNXT_ULP_CLASS_HID_23778 = 0x23778,\n+\tBNXT_ULP_CLASS_HID_2a078 = 0x2a078,\n+\tBNXT_ULP_CLASS_HID_32d78 = 0x32d78,\n+\tBNXT_ULP_CLASS_HID_3d678 = 0x3d678,\n+\tBNXT_ULP_CLASS_HID_22828 = 0x22828,\n+\tBNXT_ULP_CLASS_HID_2d528 = 0x2d528,\n+\tBNXT_ULP_CLASS_HID_35e28 = 0x35e28,\n+\tBNXT_ULP_CLASS_HID_3cb28 = 0x3cb28,\n+\tBNXT_ULP_CLASS_HID_214bc = 0x214bc,\n+\tBNXT_ULP_CLASS_HID_281bc = 0x281bc,\n+\tBNXT_ULP_CLASS_HID_30abc = 0x30abc,\n+\tBNXT_ULP_CLASS_HID_3b7bc = 0x3b7bc,\n+\tBNXT_ULP_CLASS_HID_25ed8 = 0x25ed8,\n+\tBNXT_ULP_CLASS_HID_2cbd8 = 0x2cbd8,\n+\tBNXT_ULP_CLASS_HID_3198c = 0x3198c,\n+\tBNXT_ULP_CLASS_HID_3828c = 0x3828c,\n+\tBNXT_ULP_CLASS_HID_25b8c = 0x25b8c,\n+\tBNXT_ULP_CLASS_HID_2c48c = 0x2c48c,\n+\tBNXT_ULP_CLASS_HID_31240 = 0x31240,\n+\tBNXT_ULP_CLASS_HID_39f40 = 0x39f40,\n+\tBNXT_ULP_CLASS_HID_21170 = 0x21170,\n+\tBNXT_ULP_CLASS_HID_29a70 = 0x29a70,\n+\tBNXT_ULP_CLASS_HID_30770 = 0x30770,\n+\tBNXT_ULP_CLASS_HID_3b070 = 0x3b070,\n+\tBNXT_ULP_CLASS_HID_238d0 = 0x238d0,\n+\tBNXT_ULP_CLASS_HID_2a5d0 = 0x2a5d0,\n+\tBNXT_ULP_CLASS_HID_32ed0 = 0x32ed0,\n+\tBNXT_ULP_CLASS_HID_3dbd0 = 0x3dbd0,\n+\tBNXT_ULP_CLASS_HID_20420 = 0x20420,\n+\tBNXT_ULP_CLASS_HID_2b120 = 0x2b120,\n+\tBNXT_ULP_CLASS_HID_33a20 = 0x33a20,\n+\tBNXT_ULP_CLASS_HID_3a720 = 0x3a720,\n+\tBNXT_ULP_CLASS_HID_200d4 = 0x200d4,\n+\tBNXT_ULP_CLASS_HID_28dd4 = 0x28dd4,\n+\tBNXT_ULP_CLASS_HID_336d4 = 0x336d4,\n+\tBNXT_ULP_CLASS_HID_3a3d4 = 0x3a3d4,\n+\tBNXT_ULP_CLASS_HID_23584 = 0x23584,\n+\tBNXT_ULP_CLASS_HID_2be84 = 0x2be84,\n+\tBNXT_ULP_CLASS_HID_32b84 = 0x32b84,\n+\tBNXT_ULP_CLASS_HID_3d484 = 0x3d484,\n+\tBNXT_ULP_CLASS_HID_25d64 = 0x25d64,\n+\tBNXT_ULP_CLASS_HID_2c664 = 0x2c664,\n+\tBNXT_ULP_CLASS_HID_31418 = 0x31418,\n+\tBNXT_ULP_CLASS_HID_38118 = 0x38118,\n+\tBNXT_ULP_CLASS_HID_228b4 = 0x228b4,\n+\tBNXT_ULP_CLASS_HID_2d5b4 = 0x2d5b4,\n+\tBNXT_ULP_CLASS_HID_35eb4 = 0x35eb4,\n+\tBNXT_ULP_CLASS_HID_3cbb4 = 0x3cbb4,\n+\tBNXT_ULP_CLASS_HID_22568 = 0x22568,\n+\tBNXT_ULP_CLASS_HID_2ae68 = 0x2ae68,\n+\tBNXT_ULP_CLASS_HID_35b68 = 0x35b68,\n+\tBNXT_ULP_CLASS_HID_3c468 = 0x3c468,\n+\tBNXT_ULP_CLASS_HID_25618 = 0x25618,\n+\tBNXT_ULP_CLASS_HID_2c318 = 0x2c318,\n+\tBNXT_ULP_CLASS_HID_310cc = 0x310cc,\n+\tBNXT_ULP_CLASS_HID_39dcc = 0x39dcc,\n+\tBNXT_ULP_CLASS_HID_229b8 = 0x229b8,\n+\tBNXT_ULP_CLASS_HID_2d2b8 = 0x2d2b8,\n+\tBNXT_ULP_CLASS_HID_35fb8 = 0x35fb8,\n+\tBNXT_ULP_CLASS_HID_3c8b8 = 0x3c8b8,\n+\tBNXT_ULP_CLASS_HID_23488 = 0x23488,\n+\tBNXT_ULP_CLASS_HID_2a188 = 0x2a188,\n+\tBNXT_ULP_CLASS_HID_32a88 = 0x32a88,\n+\tBNXT_ULP_CLASS_HID_3d788 = 0x3d788,\n+\tBNXT_ULP_CLASS_HID_231bc = 0x231bc,\n+\tBNXT_ULP_CLASS_HID_2babc = 0x2babc,\n+\tBNXT_ULP_CLASS_HID_327bc = 0x327bc,\n+\tBNXT_ULP_CLASS_HID_3d0bc = 0x3d0bc,\n+\tBNXT_ULP_CLASS_HID_2226c = 0x2226c,\n+\tBNXT_ULP_CLASS_HID_2af6c = 0x2af6c,\n+\tBNXT_ULP_CLASS_HID_3586c = 0x3586c,\n+\tBNXT_ULP_CLASS_HID_3c56c = 0x3c56c,\n+\tBNXT_ULP_CLASS_HID_24dcc = 0x24dcc,\n+\tBNXT_ULP_CLASS_HID_29b80 = 0x29b80,\n+\tBNXT_ULP_CLASS_HID_30480 = 0x30480,\n+\tBNXT_ULP_CLASS_HID_3b180 = 0x3b180,\n+\tBNXT_ULP_CLASS_HID_2591c = 0x2591c,\n+\tBNXT_ULP_CLASS_HID_2c21c = 0x2c21c,\n+\tBNXT_ULP_CLASS_HID_313d0 = 0x313d0,\n+\tBNXT_ULP_CLASS_HID_39cd0 = 0x39cd0,\n+\tBNXT_ULP_CLASS_HID_255d0 = 0x255d0,\n+\tBNXT_ULP_CLASS_HID_2ded0 = 0x2ded0,\n+\tBNXT_ULP_CLASS_HID_34bd0 = 0x34bd0,\n+\tBNXT_ULP_CLASS_HID_39984 = 0x39984,\n+\tBNXT_ULP_CLASS_HID_24680 = 0x24680,\n+\tBNXT_ULP_CLASS_HID_294b4 = 0x294b4,\n+\tBNXT_ULP_CLASS_HID_301b4 = 0x301b4,\n+\tBNXT_ULP_CLASS_HID_38ab4 = 0x38ab4,\n+\tBNXT_ULP_CLASS_HID_23314 = 0x23314,\n+\tBNXT_ULP_CLASS_HID_2bc14 = 0x2bc14,\n+\tBNXT_ULP_CLASS_HID_32914 = 0x32914,\n+\tBNXT_ULP_CLASS_HID_3d214 = 0x3d214,\n+\tBNXT_ULP_CLASS_HID_21e64 = 0x21e64,\n+\tBNXT_ULP_CLASS_HID_28b64 = 0x28b64,\n+\tBNXT_ULP_CLASS_HID_33464 = 0x33464,\n+\tBNXT_ULP_CLASS_HID_3a164 = 0x3a164,\n+\tBNXT_ULP_CLASS_HID_21b18 = 0x21b18,\n+\tBNXT_ULP_CLASS_HID_28418 = 0x28418,\n+\tBNXT_ULP_CLASS_HID_33118 = 0x33118,\n+\tBNXT_ULP_CLASS_HID_3ba18 = 0x3ba18,\n+\tBNXT_ULP_CLASS_HID_20fc8 = 0x20fc8,\n+\tBNXT_ULP_CLASS_HID_2b8c8 = 0x2b8c8,\n+\tBNXT_ULP_CLASS_HID_325c8 = 0x325c8,\n+\tBNXT_ULP_CLASS_HID_3aec8 = 0x3aec8,\n+\tBNXT_ULP_CLASS_HID_257a8 = 0x257a8,\n+\tBNXT_ULP_CLASS_HID_2c0a8 = 0x2c0a8,\n+\tBNXT_ULP_CLASS_HID_34da8 = 0x34da8,\n+\tBNXT_ULP_CLASS_HID_39b5c = 0x39b5c,\n+\tBNXT_ULP_CLASS_HID_222f8 = 0x222f8,\n+\tBNXT_ULP_CLASS_HID_2aff8 = 0x2aff8,\n+\tBNXT_ULP_CLASS_HID_358f8 = 0x358f8,\n+\tBNXT_ULP_CLASS_HID_3c5f8 = 0x3c5f8,\n+\tBNXT_ULP_CLASS_HID_23fac = 0x23fac,\n+\tBNXT_ULP_CLASS_HID_2a8ac = 0x2a8ac,\n+\tBNXT_ULP_CLASS_HID_355ac = 0x355ac,\n+\tBNXT_ULP_CLASS_HID_3deac = 0x3deac,\n+\tBNXT_ULP_CLASS_HID_2505c = 0x2505c,\n+\tBNXT_ULP_CLASS_HID_2dd5c = 0x2dd5c,\n+\tBNXT_ULP_CLASS_HID_3465c = 0x3465c,\n+\tBNXT_ULP_CLASS_HID_39410 = 0x39410,\n+\tBNXT_ULP_CLASS_HID_223fc = 0x223fc,\n+\tBNXT_ULP_CLASS_HID_2acfc = 0x2acfc,\n+\tBNXT_ULP_CLASS_HID_359fc = 0x359fc,\n+\tBNXT_ULP_CLASS_HID_3c2fc = 0x3c2fc,\n+\tBNXT_ULP_CLASS_HID_20ecc = 0x20ecc,\n+\tBNXT_ULP_CLASS_HID_2bbcc = 0x2bbcc,\n+\tBNXT_ULP_CLASS_HID_324cc = 0x324cc,\n+\tBNXT_ULP_CLASS_HID_3d1cc = 0x3d1cc,\n+\tBNXT_ULP_CLASS_HID_20b80 = 0x20b80,\n+\tBNXT_ULP_CLASS_HID_2b480 = 0x2b480,\n+\tBNXT_ULP_CLASS_HID_32180 = 0x32180,\n+\tBNXT_ULP_CLASS_HID_3aa80 = 0x3aa80,\n+\tBNXT_ULP_CLASS_HID_23cb0 = 0x23cb0,\n+\tBNXT_ULP_CLASS_HID_2a9b0 = 0x2a9b0,\n+\tBNXT_ULP_CLASS_HID_352b0 = 0x352b0,\n+\tBNXT_ULP_CLASS_HID_3dfb0 = 0x3dfb0,\n+\tBNXT_ULP_CLASS_HID_24410 = 0x24410,\n+\tBNXT_ULP_CLASS_HID_295c4 = 0x295c4,\n+\tBNXT_ULP_CLASS_HID_31ec4 = 0x31ec4,\n+\tBNXT_ULP_CLASS_HID_38bc4 = 0x38bc4,\n+\tBNXT_ULP_CLASS_HID_25360 = 0x25360,\n+\tBNXT_ULP_CLASS_HID_2dc60 = 0x2dc60,\n+\tBNXT_ULP_CLASS_HID_34960 = 0x34960,\n+\tBNXT_ULP_CLASS_HID_39714 = 0x39714,\n+\tBNXT_ULP_CLASS_HID_22c14 = 0x22c14,\n+\tBNXT_ULP_CLASS_HID_2d914 = 0x2d914,\n+\tBNXT_ULP_CLASS_HID_34214 = 0x34214,\n+\tBNXT_ULP_CLASS_HID_393c8 = 0x393c8,\n+\tBNXT_ULP_CLASS_HID_240c4 = 0x240c4,\n+\tBNXT_ULP_CLASS_HID_2cdc4 = 0x2cdc4,\n+\tBNXT_ULP_CLASS_HID_31bf8 = 0x31bf8,\n+\tBNXT_ULP_CLASS_HID_384f8 = 0x384f8,\n+\tBNXT_ULP_CLASS_HID_23dc0 = 0x23dc0,\n+\tBNXT_ULP_CLASS_HID_2a6c0 = 0x2a6c0,\n+\tBNXT_ULP_CLASS_HID_353c0 = 0x353c0,\n+\tBNXT_ULP_CLASS_HID_3dcc0 = 0x3dcc0,\n+\tBNXT_ULP_CLASS_HID_20910 = 0x20910,\n+\tBNXT_ULP_CLASS_HID_2b210 = 0x2b210,\n+\tBNXT_ULP_CLASS_HID_33f10 = 0x33f10,\n+\tBNXT_ULP_CLASS_HID_3a810 = 0x3a810,\n+\tBNXT_ULP_CLASS_HID_205c4 = 0x205c4,\n+\tBNXT_ULP_CLASS_HID_28ec4 = 0x28ec4,\n+\tBNXT_ULP_CLASS_HID_33bc4 = 0x33bc4,\n+\tBNXT_ULP_CLASS_HID_3a4c4 = 0x3a4c4,\n+\tBNXT_ULP_CLASS_HID_236f4 = 0x236f4,\n+\tBNXT_ULP_CLASS_HID_2a3f4 = 0x2a3f4,\n+\tBNXT_ULP_CLASS_HID_32cf4 = 0x32cf4,\n+\tBNXT_ULP_CLASS_HID_3d9f4 = 0x3d9f4,\n+\tBNXT_ULP_CLASS_HID_25e54 = 0x25e54,\n+\tBNXT_ULP_CLASS_HID_2cb54 = 0x2cb54,\n+\tBNXT_ULP_CLASS_HID_31908 = 0x31908,\n+\tBNXT_ULP_CLASS_HID_38208 = 0x38208,\n+\tBNXT_ULP_CLASS_HID_22da4 = 0x22da4,\n+\tBNXT_ULP_CLASS_HID_2d6a4 = 0x2d6a4,\n+\tBNXT_ULP_CLASS_HID_343a4 = 0x343a4,\n+\tBNXT_ULP_CLASS_HID_39158 = 0x39158,\n+\tBNXT_ULP_CLASS_HID_22658 = 0x22658,\n+\tBNXT_ULP_CLASS_HID_2d358 = 0x2d358,\n+\tBNXT_ULP_CLASS_HID_35c58 = 0x35c58,\n+\tBNXT_ULP_CLASS_HID_3c958 = 0x3c958,\n+\tBNXT_ULP_CLASS_HID_25b08 = 0x25b08,\n+\tBNXT_ULP_CLASS_HID_2c408 = 0x2c408,\n+\tBNXT_ULP_CLASS_HID_3123c = 0x3123c,\n+\tBNXT_ULP_CLASS_HID_39f3c = 0x39f3c,\n+\tBNXT_ULP_CLASS_HID_34a8 = 0x34a8,\n+\tBNXT_ULP_CLASS_HID_3a64 = 0x3a64,\n+\tBNXT_ULP_CLASS_HID_5ef8 = 0x5ef8,\n+\tBNXT_ULP_CLASS_HID_07c0 = 0x07c0,\n+\tBNXT_ULP_CLASS_HID_2854 = 0x2854,\n+\tBNXT_ULP_CLASS_HID_593c = 0x593c,\n+\tBNXT_ULP_CLASS_HID_1e04 = 0x1e04,\n+\tBNXT_ULP_CLASS_HID_2298 = 0x2298,\n+\tBNXT_ULP_CLASS_HID_24644 = 0x24644,\n+\tBNXT_ULP_CLASS_HID_29438 = 0x29438,\n+\tBNXT_ULP_CLASS_HID_30138 = 0x30138,\n+\tBNXT_ULP_CLASS_HID_38a38 = 0x38a38,\n+\tBNXT_ULP_CLASS_HID_25594 = 0x25594,\n+\tBNXT_ULP_CLASS_HID_2de94 = 0x2de94,\n+\tBNXT_ULP_CLASS_HID_34b94 = 0x34b94,\n+\tBNXT_ULP_CLASS_HID_39948 = 0x39948,\n+\tBNXT_ULP_CLASS_HID_22e48 = 0x22e48,\n+\tBNXT_ULP_CLASS_HID_2db48 = 0x2db48,\n+\tBNXT_ULP_CLASS_HID_34448 = 0x34448,\n+\tBNXT_ULP_CLASS_HID_3923c = 0x3923c,\n+\tBNXT_ULP_CLASS_HID_24338 = 0x24338,\n+\tBNXT_ULP_CLASS_HID_290ec = 0x290ec,\n+\tBNXT_ULP_CLASS_HID_31dec = 0x31dec,\n+\tBNXT_ULP_CLASS_HID_386ec = 0x386ec,\n+\tBNXT_ULP_CLASS_HID_20f8c = 0x20f8c,\n+\tBNXT_ULP_CLASS_HID_2b88c = 0x2b88c,\n+\tBNXT_ULP_CLASS_HID_3258c = 0x3258c,\n+\tBNXT_ULP_CLASS_HID_3ae8c = 0x3ae8c,\n+\tBNXT_ULP_CLASS_HID_21adc = 0x21adc,\n+\tBNXT_ULP_CLASS_HID_287dc = 0x287dc,\n+\tBNXT_ULP_CLASS_HID_330dc = 0x330dc,\n+\tBNXT_ULP_CLASS_HID_3bddc = 0x3bddc,\n+\tBNXT_ULP_CLASS_HID_21790 = 0x21790,\n+\tBNXT_ULP_CLASS_HID_28090 = 0x28090,\n+\tBNXT_ULP_CLASS_HID_30d90 = 0x30d90,\n+\tBNXT_ULP_CLASS_HID_3b690 = 0x3b690,\n+\tBNXT_ULP_CLASS_HID_20840 = 0x20840,\n+\tBNXT_ULP_CLASS_HID_2b540 = 0x2b540,\n+\tBNXT_ULP_CLASS_HID_33e40 = 0x33e40,\n+\tBNXT_ULP_CLASS_HID_3ab40 = 0x3ab40,\n+\tBNXT_ULP_CLASS_HID_253e0 = 0x253e0,\n+\tBNXT_ULP_CLASS_HID_2dce0 = 0x2dce0,\n+\tBNXT_ULP_CLASS_HID_349e0 = 0x349e0,\n+\tBNXT_ULP_CLASS_HID_397d4 = 0x397d4,\n+\tBNXT_ULP_CLASS_HID_23f30 = 0x23f30,\n+\tBNXT_ULP_CLASS_HID_2a830 = 0x2a830,\n+\tBNXT_ULP_CLASS_HID_35530 = 0x35530,\n+\tBNXT_ULP_CLASS_HID_3de30 = 0x3de30,\n+\tBNXT_ULP_CLASS_HID_23be4 = 0x23be4,\n+\tBNXT_ULP_CLASS_HID_2a4e4 = 0x2a4e4,\n+\tBNXT_ULP_CLASS_HID_351e4 = 0x351e4,\n+\tBNXT_ULP_CLASS_HID_3dae4 = 0x3dae4,\n+\tBNXT_ULP_CLASS_HID_22cd4 = 0x22cd4,\n+\tBNXT_ULP_CLASS_HID_2d9d4 = 0x2d9d4,\n+\tBNXT_ULP_CLASS_HID_342d4 = 0x342d4,\n+\tBNXT_ULP_CLASS_HID_39088 = 0x39088,\n+\tBNXT_ULP_CLASS_HID_21928 = 0x21928,\n+\tBNXT_ULP_CLASS_HID_28228 = 0x28228,\n+\tBNXT_ULP_CLASS_HID_30f28 = 0x30f28,\n+\tBNXT_ULP_CLASS_HID_3b828 = 0x3b828,\n+\tBNXT_ULP_CLASS_HID_24384 = 0x24384,\n+\tBNXT_ULP_CLASS_HID_29178 = 0x29178,\n+\tBNXT_ULP_CLASS_HID_31a78 = 0x31a78,\n+\tBNXT_ULP_CLASS_HID_38778 = 0x38778,\n+\tBNXT_ULP_CLASS_HID_25c78 = 0x25c78,\n+\tBNXT_ULP_CLASS_HID_2c978 = 0x2c978,\n+\tBNXT_ULP_CLASS_HID_3172c = 0x3172c,\n+\tBNXT_ULP_CLASS_HID_3802c = 0x3802c,\n+\tBNXT_ULP_CLASS_HID_2121c = 0x2121c,\n+\tBNXT_ULP_CLASS_HID_29f1c = 0x29f1c,\n+\tBNXT_ULP_CLASS_HID_3081c = 0x3081c,\n+\tBNXT_ULP_CLASS_HID_3b51c = 0x3b51c,\n+\tBNXT_ULP_CLASS_HID_24088 = 0x24088,\n+\tBNXT_ULP_CLASS_HID_2cd88 = 0x2cd88,\n+\tBNXT_ULP_CLASS_HID_31b7c = 0x31b7c,\n+\tBNXT_ULP_CLASS_HID_3847c = 0x3847c,\n+\tBNXT_ULP_CLASS_HID_22fd8 = 0x22fd8,\n+\tBNXT_ULP_CLASS_HID_2d8d8 = 0x2d8d8,\n+\tBNXT_ULP_CLASS_HID_345d8 = 0x345d8,\n+\tBNXT_ULP_CLASS_HID_3938c = 0x3938c,\n+\tBNXT_ULP_CLASS_HID_2288c = 0x2288c,\n+\tBNXT_ULP_CLASS_HID_2d58c = 0x2d58c,\n+\tBNXT_ULP_CLASS_HID_35e8c = 0x35e8c,\n+\tBNXT_ULP_CLASS_HID_3cb8c = 0x3cb8c,\n+\tBNXT_ULP_CLASS_HID_25d7c = 0x25d7c,\n+\tBNXT_ULP_CLASS_HID_2c67c = 0x2c67c,\n+\tBNXT_ULP_CLASS_HID_31430 = 0x31430,\n+\tBNXT_ULP_CLASS_HID_38130 = 0x38130,\n+\tBNXT_ULP_CLASS_HID_209d0 = 0x209d0,\n+\tBNXT_ULP_CLASS_HID_2b2d0 = 0x2b2d0,\n+\tBNXT_ULP_CLASS_HID_33fd0 = 0x33fd0,\n+\tBNXT_ULP_CLASS_HID_3a8d0 = 0x3a8d0,\n+\tBNXT_ULP_CLASS_HID_214e0 = 0x214e0,\n+\tBNXT_ULP_CLASS_HID_281e0 = 0x281e0,\n+\tBNXT_ULP_CLASS_HID_30ae0 = 0x30ae0,\n+\tBNXT_ULP_CLASS_HID_3b7e0 = 0x3b7e0,\n+\tBNXT_ULP_CLASS_HID_211d4 = 0x211d4,\n+\tBNXT_ULP_CLASS_HID_29ad4 = 0x29ad4,\n+\tBNXT_ULP_CLASS_HID_307d4 = 0x307d4,\n+\tBNXT_ULP_CLASS_HID_3b0d4 = 0x3b0d4,\n+\tBNXT_ULP_CLASS_HID_20284 = 0x20284,\n+\tBNXT_ULP_CLASS_HID_28f84 = 0x28f84,\n+\tBNXT_ULP_CLASS_HID_33884 = 0x33884,\n+\tBNXT_ULP_CLASS_HID_3a584 = 0x3a584,\n+\tBNXT_ULP_CLASS_HID_22a24 = 0x22a24,\n+\tBNXT_ULP_CLASS_HID_2d724 = 0x2d724,\n+\tBNXT_ULP_CLASS_HID_34024 = 0x34024,\n+\tBNXT_ULP_CLASS_HID_3cd24 = 0x3cd24,\n+\tBNXT_ULP_CLASS_HID_23974 = 0x23974,\n+\tBNXT_ULP_CLASS_HID_2a274 = 0x2a274,\n+\tBNXT_ULP_CLASS_HID_32f74 = 0x32f74,\n+\tBNXT_ULP_CLASS_HID_3d874 = 0x3d874,\n+\tBNXT_ULP_CLASS_HID_23228 = 0x23228,\n+\tBNXT_ULP_CLASS_HID_2bf28 = 0x2bf28,\n+\tBNXT_ULP_CLASS_HID_32828 = 0x32828,\n+\tBNXT_ULP_CLASS_HID_3d528 = 0x3d528,\n+\tBNXT_ULP_CLASS_HID_22718 = 0x22718,\n+\tBNXT_ULP_CLASS_HID_2d018 = 0x2d018,\n+\tBNXT_ULP_CLASS_HID_35d18 = 0x35d18,\n+\tBNXT_ULP_CLASS_HID_3c618 = 0x3c618,\n+\tBNXT_ULP_CLASS_HID_2136c = 0x2136c,\n+\tBNXT_ULP_CLASS_HID_29c6c = 0x29c6c,\n+\tBNXT_ULP_CLASS_HID_3096c = 0x3096c,\n+\tBNXT_ULP_CLASS_HID_3b26c = 0x3b26c,\n+\tBNXT_ULP_CLASS_HID_25dc8 = 0x25dc8,\n+\tBNXT_ULP_CLASS_HID_2c6c8 = 0x2c6c8,\n+\tBNXT_ULP_CLASS_HID_314bc = 0x314bc,\n+\tBNXT_ULP_CLASS_HID_381bc = 0x381bc,\n+\tBNXT_ULP_CLASS_HID_256bc = 0x256bc,\n+\tBNXT_ULP_CLASS_HID_2c3bc = 0x2c3bc,\n+\tBNXT_ULP_CLASS_HID_31170 = 0x31170,\n+\tBNXT_ULP_CLASS_HID_39a70 = 0x39a70,\n+\tBNXT_ULP_CLASS_HID_24b6c = 0x24b6c,\n+\tBNXT_ULP_CLASS_HID_29920 = 0x29920,\n+\tBNXT_ULP_CLASS_HID_30220 = 0x30220,\n+\tBNXT_ULP_CLASS_HID_38f20 = 0x38f20,\n+\tBNXT_ULP_CLASS_HID_22f54 = 0x22f54,\n+\tBNXT_ULP_CLASS_HID_2d854 = 0x2d854,\n+\tBNXT_ULP_CLASS_HID_34554 = 0x34554,\n+\tBNXT_ULP_CLASS_HID_39308 = 0x39308,\n+\tBNXT_ULP_CLASS_HID_23a64 = 0x23a64,\n+\tBNXT_ULP_CLASS_HID_2a764 = 0x2a764,\n+\tBNXT_ULP_CLASS_HID_35064 = 0x35064,\n+\tBNXT_ULP_CLASS_HID_3dd64 = 0x3dd64,\n+\tBNXT_ULP_CLASS_HID_23758 = 0x23758,\n+\tBNXT_ULP_CLASS_HID_2a058 = 0x2a058,\n+\tBNXT_ULP_CLASS_HID_32d58 = 0x32d58,\n+\tBNXT_ULP_CLASS_HID_3d658 = 0x3d658,\n+\tBNXT_ULP_CLASS_HID_22808 = 0x22808,\n+\tBNXT_ULP_CLASS_HID_2d508 = 0x2d508,\n+\tBNXT_ULP_CLASS_HID_35e08 = 0x35e08,\n+\tBNXT_ULP_CLASS_HID_3cb08 = 0x3cb08,\n+\tBNXT_ULP_CLASS_HID_2149c = 0x2149c,\n+\tBNXT_ULP_CLASS_HID_2819c = 0x2819c,\n+\tBNXT_ULP_CLASS_HID_30a9c = 0x30a9c,\n+\tBNXT_ULP_CLASS_HID_3b79c = 0x3b79c,\n+\tBNXT_ULP_CLASS_HID_25ef8 = 0x25ef8,\n+\tBNXT_ULP_CLASS_HID_2cbf8 = 0x2cbf8,\n+\tBNXT_ULP_CLASS_HID_319ac = 0x319ac,\n+\tBNXT_ULP_CLASS_HID_382ac = 0x382ac,\n+\tBNXT_ULP_CLASS_HID_25bac = 0x25bac,\n+\tBNXT_ULP_CLASS_HID_2c4ac = 0x2c4ac,\n+\tBNXT_ULP_CLASS_HID_31260 = 0x31260,\n+\tBNXT_ULP_CLASS_HID_39f60 = 0x39f60,\n+\tBNXT_ULP_CLASS_HID_21150 = 0x21150,\n+\tBNXT_ULP_CLASS_HID_29a50 = 0x29a50,\n+\tBNXT_ULP_CLASS_HID_30750 = 0x30750,\n+\tBNXT_ULP_CLASS_HID_3b050 = 0x3b050,\n+\tBNXT_ULP_CLASS_HID_238f0 = 0x238f0,\n+\tBNXT_ULP_CLASS_HID_2a5f0 = 0x2a5f0,\n+\tBNXT_ULP_CLASS_HID_32ef0 = 0x32ef0,\n+\tBNXT_ULP_CLASS_HID_3dbf0 = 0x3dbf0,\n+\tBNXT_ULP_CLASS_HID_20400 = 0x20400,\n+\tBNXT_ULP_CLASS_HID_2b100 = 0x2b100,\n+\tBNXT_ULP_CLASS_HID_33a00 = 0x33a00,\n+\tBNXT_ULP_CLASS_HID_3a700 = 0x3a700,\n+\tBNXT_ULP_CLASS_HID_200f4 = 0x200f4,\n+\tBNXT_ULP_CLASS_HID_28df4 = 0x28df4,\n+\tBNXT_ULP_CLASS_HID_336f4 = 0x336f4,\n+\tBNXT_ULP_CLASS_HID_3a3f4 = 0x3a3f4,\n+\tBNXT_ULP_CLASS_HID_235a4 = 0x235a4,\n+\tBNXT_ULP_CLASS_HID_2bea4 = 0x2bea4,\n+\tBNXT_ULP_CLASS_HID_32ba4 = 0x32ba4,\n+\tBNXT_ULP_CLASS_HID_3d4a4 = 0x3d4a4,\n+\tBNXT_ULP_CLASS_HID_25d44 = 0x25d44,\n+\tBNXT_ULP_CLASS_HID_2c644 = 0x2c644,\n+\tBNXT_ULP_CLASS_HID_31438 = 0x31438,\n+\tBNXT_ULP_CLASS_HID_38138 = 0x38138,\n+\tBNXT_ULP_CLASS_HID_22894 = 0x22894,\n+\tBNXT_ULP_CLASS_HID_2d594 = 0x2d594,\n+\tBNXT_ULP_CLASS_HID_35e94 = 0x35e94,\n+\tBNXT_ULP_CLASS_HID_3cb94 = 0x3cb94,\n+\tBNXT_ULP_CLASS_HID_22548 = 0x22548,\n+\tBNXT_ULP_CLASS_HID_2ae48 = 0x2ae48,\n+\tBNXT_ULP_CLASS_HID_35b48 = 0x35b48,\n+\tBNXT_ULP_CLASS_HID_3c448 = 0x3c448,\n+\tBNXT_ULP_CLASS_HID_25638 = 0x25638,\n+\tBNXT_ULP_CLASS_HID_2c338 = 0x2c338,\n+\tBNXT_ULP_CLASS_HID_310ec = 0x310ec,\n+\tBNXT_ULP_CLASS_HID_39dec = 0x39dec,\n+\tBNXT_ULP_CLASS_HID_22998 = 0x22998,\n+\tBNXT_ULP_CLASS_HID_2d298 = 0x2d298,\n+\tBNXT_ULP_CLASS_HID_35f98 = 0x35f98,\n+\tBNXT_ULP_CLASS_HID_3c898 = 0x3c898,\n+\tBNXT_ULP_CLASS_HID_234a8 = 0x234a8,\n+\tBNXT_ULP_CLASS_HID_2a1a8 = 0x2a1a8,\n+\tBNXT_ULP_CLASS_HID_32aa8 = 0x32aa8,\n+\tBNXT_ULP_CLASS_HID_3d7a8 = 0x3d7a8,\n+\tBNXT_ULP_CLASS_HID_2319c = 0x2319c,\n+\tBNXT_ULP_CLASS_HID_2ba9c = 0x2ba9c,\n+\tBNXT_ULP_CLASS_HID_3279c = 0x3279c,\n+\tBNXT_ULP_CLASS_HID_3d09c = 0x3d09c,\n+\tBNXT_ULP_CLASS_HID_2224c = 0x2224c,\n+\tBNXT_ULP_CLASS_HID_2af4c = 0x2af4c,\n+\tBNXT_ULP_CLASS_HID_3584c = 0x3584c,\n+\tBNXT_ULP_CLASS_HID_3c54c = 0x3c54c,\n+\tBNXT_ULP_CLASS_HID_24dec = 0x24dec,\n+\tBNXT_ULP_CLASS_HID_29ba0 = 0x29ba0,\n+\tBNXT_ULP_CLASS_HID_304a0 = 0x304a0,\n+\tBNXT_ULP_CLASS_HID_3b1a0 = 0x3b1a0,\n+\tBNXT_ULP_CLASS_HID_2593c = 0x2593c,\n+\tBNXT_ULP_CLASS_HID_2c23c = 0x2c23c,\n+\tBNXT_ULP_CLASS_HID_313f0 = 0x313f0,\n+\tBNXT_ULP_CLASS_HID_39cf0 = 0x39cf0,\n+\tBNXT_ULP_CLASS_HID_255f0 = 0x255f0,\n+\tBNXT_ULP_CLASS_HID_2def0 = 0x2def0,\n+\tBNXT_ULP_CLASS_HID_34bf0 = 0x34bf0,\n+\tBNXT_ULP_CLASS_HID_399a4 = 0x399a4,\n+\tBNXT_ULP_CLASS_HID_246a0 = 0x246a0,\n+\tBNXT_ULP_CLASS_HID_29494 = 0x29494,\n+\tBNXT_ULP_CLASS_HID_30194 = 0x30194,\n+\tBNXT_ULP_CLASS_HID_38a94 = 0x38a94,\n+\tBNXT_ULP_CLASS_HID_23334 = 0x23334,\n+\tBNXT_ULP_CLASS_HID_2bc34 = 0x2bc34,\n+\tBNXT_ULP_CLASS_HID_32934 = 0x32934,\n+\tBNXT_ULP_CLASS_HID_3d234 = 0x3d234,\n+\tBNXT_ULP_CLASS_HID_21e44 = 0x21e44,\n+\tBNXT_ULP_CLASS_HID_28b44 = 0x28b44,\n+\tBNXT_ULP_CLASS_HID_33444 = 0x33444,\n+\tBNXT_ULP_CLASS_HID_3a144 = 0x3a144,\n+\tBNXT_ULP_CLASS_HID_21b38 = 0x21b38,\n+\tBNXT_ULP_CLASS_HID_28438 = 0x28438,\n+\tBNXT_ULP_CLASS_HID_33138 = 0x33138,\n+\tBNXT_ULP_CLASS_HID_3ba38 = 0x3ba38,\n+\tBNXT_ULP_CLASS_HID_20fe8 = 0x20fe8,\n+\tBNXT_ULP_CLASS_HID_2b8e8 = 0x2b8e8,\n+\tBNXT_ULP_CLASS_HID_325e8 = 0x325e8,\n+\tBNXT_ULP_CLASS_HID_3aee8 = 0x3aee8,\n+\tBNXT_ULP_CLASS_HID_25788 = 0x25788,\n+\tBNXT_ULP_CLASS_HID_2c088 = 0x2c088,\n+\tBNXT_ULP_CLASS_HID_34d88 = 0x34d88,\n+\tBNXT_ULP_CLASS_HID_39b7c = 0x39b7c,\n+\tBNXT_ULP_CLASS_HID_222d8 = 0x222d8,\n+\tBNXT_ULP_CLASS_HID_2afd8 = 0x2afd8,\n+\tBNXT_ULP_CLASS_HID_358d8 = 0x358d8,\n+\tBNXT_ULP_CLASS_HID_3c5d8 = 0x3c5d8,\n+\tBNXT_ULP_CLASS_HID_23f8c = 0x23f8c,\n+\tBNXT_ULP_CLASS_HID_2a88c = 0x2a88c,\n+\tBNXT_ULP_CLASS_HID_3558c = 0x3558c,\n+\tBNXT_ULP_CLASS_HID_3de8c = 0x3de8c,\n+\tBNXT_ULP_CLASS_HID_2507c = 0x2507c,\n+\tBNXT_ULP_CLASS_HID_2dd7c = 0x2dd7c,\n+\tBNXT_ULP_CLASS_HID_3467c = 0x3467c,\n+\tBNXT_ULP_CLASS_HID_39430 = 0x39430,\n+\tBNXT_ULP_CLASS_HID_223dc = 0x223dc,\n+\tBNXT_ULP_CLASS_HID_2acdc = 0x2acdc,\n+\tBNXT_ULP_CLASS_HID_359dc = 0x359dc,\n+\tBNXT_ULP_CLASS_HID_3c2dc = 0x3c2dc,\n+\tBNXT_ULP_CLASS_HID_20eec = 0x20eec,\n+\tBNXT_ULP_CLASS_HID_2bbec = 0x2bbec,\n+\tBNXT_ULP_CLASS_HID_324ec = 0x324ec,\n+\tBNXT_ULP_CLASS_HID_3d1ec = 0x3d1ec,\n+\tBNXT_ULP_CLASS_HID_20ba0 = 0x20ba0,\n+\tBNXT_ULP_CLASS_HID_2b4a0 = 0x2b4a0,\n+\tBNXT_ULP_CLASS_HID_321a0 = 0x321a0,\n+\tBNXT_ULP_CLASS_HID_3aaa0 = 0x3aaa0,\n+\tBNXT_ULP_CLASS_HID_23c90 = 0x23c90,\n+\tBNXT_ULP_CLASS_HID_2a990 = 0x2a990,\n+\tBNXT_ULP_CLASS_HID_35290 = 0x35290,\n+\tBNXT_ULP_CLASS_HID_3df90 = 0x3df90,\n+\tBNXT_ULP_CLASS_HID_24430 = 0x24430,\n+\tBNXT_ULP_CLASS_HID_295e4 = 0x295e4,\n+\tBNXT_ULP_CLASS_HID_31ee4 = 0x31ee4,\n+\tBNXT_ULP_CLASS_HID_38be4 = 0x38be4,\n+\tBNXT_ULP_CLASS_HID_25340 = 0x25340,\n+\tBNXT_ULP_CLASS_HID_2dc40 = 0x2dc40,\n+\tBNXT_ULP_CLASS_HID_34940 = 0x34940,\n+\tBNXT_ULP_CLASS_HID_39734 = 0x39734,\n+\tBNXT_ULP_CLASS_HID_22c34 = 0x22c34,\n+\tBNXT_ULP_CLASS_HID_2d934 = 0x2d934,\n+\tBNXT_ULP_CLASS_HID_34234 = 0x34234,\n+\tBNXT_ULP_CLASS_HID_393e8 = 0x393e8,\n+\tBNXT_ULP_CLASS_HID_240e4 = 0x240e4,\n+\tBNXT_ULP_CLASS_HID_2cde4 = 0x2cde4,\n+\tBNXT_ULP_CLASS_HID_31bd8 = 0x31bd8,\n+\tBNXT_ULP_CLASS_HID_384d8 = 0x384d8,\n+\tBNXT_ULP_CLASS_HID_23de0 = 0x23de0,\n+\tBNXT_ULP_CLASS_HID_2a6e0 = 0x2a6e0,\n+\tBNXT_ULP_CLASS_HID_353e0 = 0x353e0,\n+\tBNXT_ULP_CLASS_HID_3dce0 = 0x3dce0,\n+\tBNXT_ULP_CLASS_HID_20930 = 0x20930,\n+\tBNXT_ULP_CLASS_HID_2b230 = 0x2b230,\n+\tBNXT_ULP_CLASS_HID_33f30 = 0x33f30,\n+\tBNXT_ULP_CLASS_HID_3a830 = 0x3a830,\n+\tBNXT_ULP_CLASS_HID_205e4 = 0x205e4,\n+\tBNXT_ULP_CLASS_HID_28ee4 = 0x28ee4,\n+\tBNXT_ULP_CLASS_HID_33be4 = 0x33be4,\n+\tBNXT_ULP_CLASS_HID_3a4e4 = 0x3a4e4,\n+\tBNXT_ULP_CLASS_HID_236d4 = 0x236d4,\n+\tBNXT_ULP_CLASS_HID_2a3d4 = 0x2a3d4,\n+\tBNXT_ULP_CLASS_HID_32cd4 = 0x32cd4,\n+\tBNXT_ULP_CLASS_HID_3d9d4 = 0x3d9d4,\n+\tBNXT_ULP_CLASS_HID_25e74 = 0x25e74,\n+\tBNXT_ULP_CLASS_HID_2cb74 = 0x2cb74,\n+\tBNXT_ULP_CLASS_HID_31928 = 0x31928,\n+\tBNXT_ULP_CLASS_HID_38228 = 0x38228,\n+\tBNXT_ULP_CLASS_HID_22d84 = 0x22d84,\n+\tBNXT_ULP_CLASS_HID_2d684 = 0x2d684,\n+\tBNXT_ULP_CLASS_HID_34384 = 0x34384,\n+\tBNXT_ULP_CLASS_HID_39178 = 0x39178,\n+\tBNXT_ULP_CLASS_HID_22678 = 0x22678,\n+\tBNXT_ULP_CLASS_HID_2d378 = 0x2d378,\n+\tBNXT_ULP_CLASS_HID_35c78 = 0x35c78,\n+\tBNXT_ULP_CLASS_HID_3c978 = 0x3c978,\n+\tBNXT_ULP_CLASS_HID_25b28 = 0x25b28,\n+\tBNXT_ULP_CLASS_HID_2c428 = 0x2c428,\n+\tBNXT_ULP_CLASS_HID_3121c = 0x3121c,\n+\tBNXT_ULP_CLASS_HID_39f1c = 0x39f1c,\n+\tBNXT_ULP_CLASS_HID_3488 = 0x3488,\n+\tBNXT_ULP_CLASS_HID_3a44 = 0x3a44,\n+\tBNXT_ULP_CLASS_HID_5ed8 = 0x5ed8,\n+\tBNXT_ULP_CLASS_HID_07e0 = 0x07e0,\n+\tBNXT_ULP_CLASS_HID_2874 = 0x2874,\n+\tBNXT_ULP_CLASS_HID_591c = 0x591c,\n+\tBNXT_ULP_CLASS_HID_1e24 = 0x1e24,\n+\tBNXT_ULP_CLASS_HID_22b8 = 0x22b8\n };\n \n enum bnxt_ulp_act_hid {\n \tBNXT_ULP_ACT_HID_0000 = 0x0000,\n \tBNXT_ULP_ACT_HID_0001 = 0x0001,\n \tBNXT_ULP_ACT_HID_0400 = 0x0400,\n-\tBNXT_ULP_ACT_HID_0325 = 0x0325,\n+\tBNXT_ULP_ACT_HID_01ab = 0x01ab,\n \tBNXT_ULP_ACT_HID_0010 = 0x0010,\n-\tBNXT_ULP_ACT_HID_0725 = 0x0725,\n-\tBNXT_ULP_ACT_HID_0335 = 0x0335,\n+\tBNXT_ULP_ACT_HID_05ab = 0x05ab,\n+\tBNXT_ULP_ACT_HID_01bb = 0x01bb,\n \tBNXT_ULP_ACT_HID_0002 = 0x0002,\n \tBNXT_ULP_ACT_HID_0003 = 0x0003,\n \tBNXT_ULP_ACT_HID_0402 = 0x0402,\n-\tBNXT_ULP_ACT_HID_0327 = 0x0327,\n+\tBNXT_ULP_ACT_HID_01ad = 0x01ad,\n \tBNXT_ULP_ACT_HID_0012 = 0x0012,\n-\tBNXT_ULP_ACT_HID_0727 = 0x0727,\n-\tBNXT_ULP_ACT_HID_0337 = 0x0337,\n-\tBNXT_ULP_ACT_HID_01de = 0x01de,\n-\tBNXT_ULP_ACT_HID_00c6 = 0x00c6,\n-\tBNXT_ULP_ACT_HID_0506 = 0x0506,\n-\tBNXT_ULP_ACT_HID_01ed = 0x01ed,\n-\tBNXT_ULP_ACT_HID_03ef = 0x03ef,\n-\tBNXT_ULP_ACT_HID_0516 = 0x0516,\n-\tBNXT_ULP_ACT_HID_01df = 0x01df,\n-\tBNXT_ULP_ACT_HID_01e4 = 0x01e4,\n-\tBNXT_ULP_ACT_HID_00cc = 0x00cc,\n-\tBNXT_ULP_ACT_HID_0504 = 0x0504,\n-\tBNXT_ULP_ACT_HID_01ef = 0x01ef,\n-\tBNXT_ULP_ACT_HID_03ed = 0x03ed,\n-\tBNXT_ULP_ACT_HID_0514 = 0x0514,\n-\tBNXT_ULP_ACT_HID_00db = 0x00db,\n-\tBNXT_ULP_ACT_HID_00df = 0x00df\n+\tBNXT_ULP_ACT_HID_05ad = 0x05ad,\n+\tBNXT_ULP_ACT_HID_01bd = 0x01bd,\n+\tBNXT_ULP_ACT_HID_0613 = 0x0613,\n+\tBNXT_ULP_ACT_HID_02a9 = 0x02a9,\n+\tBNXT_ULP_ACT_HID_0054 = 0x0054,\n+\tBNXT_ULP_ACT_HID_0622 = 0x0622,\n+\tBNXT_ULP_ACT_HID_0454 = 0x0454,\n+\tBNXT_ULP_ACT_HID_0064 = 0x0064,\n+\tBNXT_ULP_ACT_HID_0614 = 0x0614,\n+\tBNXT_ULP_ACT_HID_0615 = 0x0615,\n+\tBNXT_ULP_ACT_HID_02ab = 0x02ab,\n+\tBNXT_ULP_ACT_HID_0056 = 0x0056,\n+\tBNXT_ULP_ACT_HID_0624 = 0x0624,\n+\tBNXT_ULP_ACT_HID_0456 = 0x0456,\n+\tBNXT_ULP_ACT_HID_0066 = 0x0066,\n+\tBNXT_ULP_ACT_HID_048d = 0x048d,\n+\tBNXT_ULP_ACT_HID_048f = 0x048f,\n+\tBNXT_ULP_ACT_HID_04bc = 0x04bc,\n+\tBNXT_ULP_ACT_HID_00a9 = 0x00a9,\n+\tBNXT_ULP_ACT_HID_020f = 0x020f,\n+\tBNXT_ULP_ACT_HID_04a9 = 0x04a9,\n+\tBNXT_ULP_ACT_HID_01fc = 0x01fc,\n+\tBNXT_ULP_ACT_HID_04be = 0x04be,\n+\tBNXT_ULP_ACT_HID_00ab = 0x00ab,\n+\tBNXT_ULP_ACT_HID_0211 = 0x0211,\n+\tBNXT_ULP_ACT_HID_04ab = 0x04ab,\n+\tBNXT_ULP_ACT_HID_01fe = 0x01fe,\n+\tBNXT_ULP_ACT_HID_0667 = 0x0667,\n+\tBNXT_ULP_ACT_HID_0254 = 0x0254,\n+\tBNXT_ULP_ACT_HID_03ba = 0x03ba,\n+\tBNXT_ULP_ACT_HID_0654 = 0x0654,\n+\tBNXT_ULP_ACT_HID_03a7 = 0x03a7,\n+\tBNXT_ULP_ACT_HID_0669 = 0x0669,\n+\tBNXT_ULP_ACT_HID_0256 = 0x0256,\n+\tBNXT_ULP_ACT_HID_03bc = 0x03bc,\n+\tBNXT_ULP_ACT_HID_0656 = 0x0656,\n+\tBNXT_ULP_ACT_HID_03a9 = 0x03a9,\n+\tBNXT_ULP_ACT_HID_021b = 0x021b,\n+\tBNXT_ULP_ACT_HID_021c = 0x021c,\n+\tBNXT_ULP_ACT_HID_021e = 0x021e,\n+\tBNXT_ULP_ACT_HID_063f = 0x063f,\n+\tBNXT_ULP_ACT_HID_0510 = 0x0510,\n+\tBNXT_ULP_ACT_HID_03c6 = 0x03c6,\n+\tBNXT_ULP_ACT_HID_0082 = 0x0082,\n+\tBNXT_ULP_ACT_HID_06bb = 0x06bb,\n+\tBNXT_ULP_ACT_HID_021d = 0x021d,\n+\tBNXT_ULP_ACT_HID_0641 = 0x0641,\n+\tBNXT_ULP_ACT_HID_0512 = 0x0512,\n+\tBNXT_ULP_ACT_HID_03c8 = 0x03c8,\n+\tBNXT_ULP_ACT_HID_0084 = 0x0084,\n+\tBNXT_ULP_ACT_HID_06bd = 0x06bd,\n+\tBNXT_ULP_ACT_HID_06d7 = 0x06d7,\n+\tBNXT_ULP_ACT_HID_02c4 = 0x02c4,\n+\tBNXT_ULP_ACT_HID_042a = 0x042a,\n+\tBNXT_ULP_ACT_HID_06c4 = 0x06c4,\n+\tBNXT_ULP_ACT_HID_0417 = 0x0417,\n+\tBNXT_ULP_ACT_HID_06d9 = 0x06d9,\n+\tBNXT_ULP_ACT_HID_02c6 = 0x02c6,\n+\tBNXT_ULP_ACT_HID_042c = 0x042c,\n+\tBNXT_ULP_ACT_HID_06c6 = 0x06c6,\n+\tBNXT_ULP_ACT_HID_0419 = 0x0419,\n+\tBNXT_ULP_ACT_HID_0119 = 0x0119,\n+\tBNXT_ULP_ACT_HID_046f = 0x046f,\n+\tBNXT_ULP_ACT_HID_05d5 = 0x05d5,\n+\tBNXT_ULP_ACT_HID_0106 = 0x0106,\n+\tBNXT_ULP_ACT_HID_05c2 = 0x05c2,\n+\tBNXT_ULP_ACT_HID_011b = 0x011b,\n+\tBNXT_ULP_ACT_HID_0471 = 0x0471,\n+\tBNXT_ULP_ACT_HID_05d7 = 0x05d7,\n+\tBNXT_ULP_ACT_HID_0108 = 0x0108,\n+\tBNXT_ULP_ACT_HID_05c4 = 0x05c4,\n+\tBNXT_ULP_ACT_HID_00a2 = 0x00a2,\n+\tBNXT_ULP_ACT_HID_00a4 = 0x00a4\n };\n \n enum bnxt_ulp_df_tpl {\n-\tBNXT_ULP_DF_TPL_PORT_TO_VS = 2,\n-\tBNXT_ULP_DF_TPL_VS_TO_PORT = 3,\n-\tBNXT_ULP_DF_TPL_VFREP_TO_VF = 4,\n-\tBNXT_ULP_DF_TPL_VF_TO_VFREP = 5,\n-\tBNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6\n+\tBNXT_ULP_DF_TPL_PORT_TO_VS = 3,\n+\tBNXT_ULP_DF_TPL_VS_TO_PORT = 4,\n+\tBNXT_ULP_DF_TPL_VFREP_TO_VF = 5,\n+\tBNXT_ULP_DF_TPL_VF_TO_VFREP = 6,\n+\tBNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7\n };\n-\n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\nindex c1294d081c..a6a4b472f4 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Dec  7 09:51:03 2020 */\n+/* date: Wed Dec 16 16:03:45 2020 */\n \n #ifndef ULP_HDR_FIELD_ENUMS_H_\n #define ULP_HDR_FIELD_ENUMS_H_\n@@ -122,16 +122,7 @@ enum bnxt_ulp_hf1_0_bitmask {\n \tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n \tBNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n \tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000010000000000\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000\n };\n \n enum bnxt_ulp_hf1_1_bitmask {\n@@ -150,10 +141,15 @@ enum bnxt_ulp_hf1_1_bitmask {\n \tBNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n \tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n \tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_UDP_CSUM         = 0x0000200000000000\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000010000000000\n };\n \n enum bnxt_ulp_hf1_2_bitmask {\n@@ -162,23 +158,20 @@ enum bnxt_ulp_hf1_2_bitmask {\n \tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM         = 0x0000080000000000,\n-\tBNXT_ULP_HF1_2_BITMASK_O_TCP_URP          = 0x0000040000000000\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_UDP_CSUM         = 0x0000200000000000\n };\n \n enum bnxt_ulp_hf1_3_bitmask {\n@@ -194,11 +187,7 @@ enum bnxt_ulp_hf1_3_bitmask {\n \tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n \tBNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n \tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n-\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,\n-\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,\n-\tBNXT_ULP_HF1_3_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,\n-\tBNXT_ULP_HF1_3_BITMASK_O_UDP_CSUM         = 0x0000800000000000\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000\n };\n \n enum bnxt_ulp_hf1_4_bitmask {\n@@ -207,28 +196,23 @@ enum bnxt_ulp_hf1_4_bitmask {\n \tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM         = 0x0000004000000000,\n-\tBNXT_ULP_HF1_4_BITMASK_O_TCP_URP          = 0x0000002000000000\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM         = 0x0000080000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_URP          = 0x0000040000000000\n };\n \n enum bnxt_ulp_hf1_5_bitmask {\n@@ -237,23 +221,18 @@ enum bnxt_ulp_hf1_5_bitmask {\n \tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n-\tBNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000800000000000\n };\n \n enum bnxt_ulp_hf1_6_bitmask {\n@@ -265,23 +244,16 @@ enum bnxt_ulp_hf1_6_bitmask {\n \tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n \tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n \tBNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_SENT_SEQ     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_RECV_ACK     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_DATA_OFF     = 0x0000080000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_TCP_FLAGS    = 0x0000040000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_RX_WIN       = 0x0000020000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_CSUM         = 0x0000010000000000,\n-\tBNXT_ULP_HF1_6_BITMASK_O_TCP_URP          = 0x0000008000000000\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000\n };\n \n enum bnxt_ulp_hf1_7_bitmask {\n@@ -293,17 +265,393 @@ enum bnxt_ulp_hf1_7_bitmask {\n \tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n \tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n \tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,\n-\tBNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM         = 0x0000100000000000\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_CSUM         = 0x0000004000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_TCP_URP          = 0x0000002000000000\n+};\n+\n+enum bnxt_ulp_hf1_8_bitmask {\n+\tBNXT_ULP_HF1_8_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n+\tBNXT_ULP_HF1_8_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n+};\n+\n+enum bnxt_ulp_hf1_9_bitmask {\n+\tBNXT_ULP_HF1_9_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000\n+};\n+\n+enum bnxt_ulp_hf1_10_bitmask {\n+\tBNXT_ULP_HF1_10_BITMASK_WM                = 0x8000000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_SVIF_INDEX        = 0x4000000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC        = 0x2000000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC        = 0x1000000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE        = 0x0800000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID       = 0x0200000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_VER        = 0x0080000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_TC         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_TTL        = 0x0004000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_SENT_SEQ    = 0x0000200000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_RECV_ACK    = 0x0000100000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_DATA_OFF    = 0x0000080000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_TCP_FLAGS   = 0x0000040000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_RX_WIN      = 0x0000020000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_CSUM        = 0x0000010000000000,\n+\tBNXT_ULP_HF1_10_BITMASK_O_TCP_URP         = 0x0000008000000000\n+};\n+\n+enum bnxt_ulp_hf1_11_bitmask {\n+\tBNXT_ULP_HF1_11_BITMASK_WM                = 0x8000000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_SVIF_INDEX        = 0x4000000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC        = 0x2000000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC        = 0x1000000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE        = 0x0800000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID       = 0x0200000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_VER        = 0x0080000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_TC         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_TTL        = 0x0004000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH      = 0x0000200000000000,\n+\tBNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM        = 0x0000100000000000\n+};\n+\n+enum bnxt_ulp_hf2_0_bitmask {\n+\tBNXT_ULP_HF2_0_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000\n+};\n+\n+enum bnxt_ulp_hf2_1_bitmask {\n+\tBNXT_ULP_HF2_1_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n+\tBNXT_ULP_HF2_1_BITMASK_O_TCP_URP          = 0x0000010000000000\n+};\n+\n+enum bnxt_ulp_hf2_2_bitmask {\n+\tBNXT_ULP_HF2_2_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,\n+\tBNXT_ULP_HF2_2_BITMASK_O_UDP_CSUM         = 0x0000200000000000\n+};\n+\n+enum bnxt_ulp_hf2_3_bitmask {\n+\tBNXT_ULP_HF2_3_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000\n+};\n+\n+enum bnxt_ulp_hf2_4_bitmask {\n+\tBNXT_ULP_HF2_4_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_CSUM         = 0x0000080000000000,\n+\tBNXT_ULP_HF2_4_BITMASK_O_TCP_URP          = 0x0000040000000000\n+};\n+\n+enum bnxt_ulp_hf2_5_bitmask {\n+\tBNXT_ULP_HF2_5_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,\n+\tBNXT_ULP_HF2_5_BITMASK_O_UDP_CSUM         = 0x0000800000000000\n+};\n+\n+enum bnxt_ulp_hf2_6_bitmask {\n+\tBNXT_ULP_HF2_6_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000\n+};\n+\n+enum bnxt_ulp_hf2_7_bitmask {\n+\tBNXT_ULP_HF2_7_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_CSUM         = 0x0000004000000000,\n+\tBNXT_ULP_HF2_7_BITMASK_O_TCP_URP          = 0x0000002000000000\n+};\n+\n+enum bnxt_ulp_hf2_8_bitmask {\n+\tBNXT_ULP_HF2_8_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n+\tBNXT_ULP_HF2_8_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n+};\n+\n+enum bnxt_ulp_hf2_9_bitmask {\n+\tBNXT_ULP_HF2_9_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000\n+};\n+\n+enum bnxt_ulp_hf2_10_bitmask {\n+\tBNXT_ULP_HF2_10_BITMASK_WM                = 0x8000000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_SVIF_INDEX        = 0x4000000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC        = 0x2000000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC        = 0x1000000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE        = 0x0800000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID       = 0x0200000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_VER        = 0x0080000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_TC         = 0x0040000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_TTL        = 0x0004000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT    = 0x0000800000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT    = 0x0000400000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_SENT_SEQ    = 0x0000200000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_RECV_ACK    = 0x0000100000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_DATA_OFF    = 0x0000080000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_TCP_FLAGS   = 0x0000040000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_RX_WIN      = 0x0000020000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_CSUM        = 0x0000010000000000,\n+\tBNXT_ULP_HF2_10_BITMASK_O_TCP_URP         = 0x0000008000000000\n+};\n+\n+enum bnxt_ulp_hf2_11_bitmask {\n+\tBNXT_ULP_HF2_11_BITMASK_WM                = 0x8000000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_SVIF_INDEX        = 0x4000000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC        = 0x2000000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC        = 0x1000000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE        = 0x0800000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID       = 0x0200000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_VER        = 0x0080000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_TC         = 0x0040000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_TTL        = 0x0004000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT    = 0x0000800000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT    = 0x0000400000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH      = 0x0000200000000000,\n+\tBNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM        = 0x0000100000000000\n };\n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c\nindex c1b3c7bcd2..d29b7a200f 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c\n@@ -32,14 +32,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 0,\n \t.result_bit_size = 64,\n@@ -54,14 +54,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 1,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 1,\n \t.result_bit_size = 0,\n@@ -76,14 +76,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 13,\n \t.result_bit_size = 128,\n@@ -98,14 +98,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 39,\n \t.result_bit_size = 128,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c\nindex a0cab178ec..df09de929e 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c\n@@ -82,13 +82,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 2,\n+\t\t.cond_true_goto = 2,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 0,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n@@ -101,14 +101,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.key_start_idx = 1,\n@@ -129,13 +129,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 14,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n@@ -144,29 +144,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.ident_nums = 3\n \t},\n \t{ /* class_tid: 1, stingray, table: branch.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 3,\n+\t\t.cond_true_goto = 3,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 1,\n \t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID\n \t},\n \t{ /* class_tid: 1, stingray, table: profile_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n@@ -188,13 +188,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 60,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n@@ -210,12 +210,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.key_start_idx = 63,\n@@ -233,12 +233,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 3,\n \t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n \t.key_start_idx = 73,\n@@ -251,15 +251,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.encap_num_fields = 0\n \t},\n \t{ /* class_tid: 1, stingray, table: last */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID\n \t},\n \t{ /* class_tid: 2, stingray, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -268,14 +268,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 44,\n \t.result_bit_size = 128,\n@@ -287,14 +287,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n@@ -318,13 +318,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 96,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n@@ -339,14 +339,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 87,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -357,14 +357,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 88,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -375,14 +375,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 89,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -395,14 +395,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 90,\n \t.result_bit_size = 128,\n@@ -414,14 +414,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n@@ -444,13 +444,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 5,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 110,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n@@ -463,14 +463,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 6,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n@@ -492,13 +492,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 8,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 124,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n@@ -513,14 +513,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 146,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -531,14 +531,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 147,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -549,14 +549,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 148,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -569,14 +569,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 149,\n \t.result_bit_size = 0,\n@@ -590,14 +590,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 161,\n \t.result_bit_size = 128,\n@@ -609,14 +609,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n@@ -638,13 +638,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 138,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n@@ -663,14 +663,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 204,\n \t.result_bit_size = 128,\n@@ -682,14 +682,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n@@ -710,14 +710,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n@@ -738,14 +738,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n@@ -767,13 +767,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.key_start_idx = 178,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n@@ -788,14 +788,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 273,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -806,14 +806,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 274,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -824,14 +824,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.result_start_idx = 275,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n@@ -844,14 +844,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n \t.result_start_idx = 276,\n \t.result_bit_size = 128,\n@@ -863,14 +863,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n@@ -893,7 +893,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\nindex 6b49a9d93f..64cf6534b9 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Fri Dec  4 19:01:47 2020 */\n+/* date: Wed Dec 16 16:03:45 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -99,6 +99,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = {\n \t.tmpl_list_size          = ULP_WH_PLUS_ACT_TMPL_LIST_SIZE,\n \t.tbl_list                = ulp_wh_plus_act_tbl_list,\n \t.tbl_list_size           = ULP_WH_PLUS_ACT_TBL_LIST_SIZE,\n+\t.key_info_list           = ulp_wh_plus_act_key_info_list,\n+\t.key_info_list_size      = ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE,\n+\t.ident_list              = ulp_wh_plus_act_ident_list,\n+\t.ident_list_size         = ULP_WH_PLUS_ACT_IDENT_LIST_SIZE,\n \t.cond_list               = ulp_wh_plus_act_cond_list,\n \t.cond_list_size          = ULP_WH_PLUS_ACT_COND_LIST_SIZE,\n \t.result_field_list       = ulp_wh_plus_act_result_field_list,\n@@ -322,15 +326,6 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2070] = 12,\n \t[2072] = 13,\n \t[2074] = 14,\n-\t[2102] = 15,\n-\t[2104] = 16,\n-\t[2106] = 17,\n-\t[2108] = 18,\n-\t[2110] = 19,\n-\t[2112] = 20,\n-\t[2114] = 21,\n-\t[2116] = 22,\n-\t[2118] = 23,\n \t[2176] = 0,\n \t[2177] = 1,\n \t[2178] = 2,\n@@ -346,32 +341,34 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2198] = 12,\n \t[2200] = 13,\n \t[2202] = 14,\n-\t[2248] = 15,\n-\t[2250] = 16,\n-\t[2252] = 17,\n-\t[2254] = 18,\n+\t[2230] = 15,\n+\t[2232] = 16,\n+\t[2234] = 17,\n+\t[2236] = 18,\n+\t[2238] = 19,\n+\t[2240] = 20,\n+\t[2242] = 21,\n+\t[2244] = 22,\n+\t[2246] = 23,\n \t[2304] = 0,\n \t[2305] = 1,\n \t[2306] = 2,\n \t[2308] = 3,\n \t[2310] = 4,\n-\t[2332] = 5,\n-\t[2334] = 6,\n-\t[2336] = 7,\n-\t[2338] = 8,\n-\t[2340] = 9,\n-\t[2342] = 10,\n-\t[2344] = 11,\n-\t[2346] = 12,\n-\t[2358] = 13,\n-\t[2360] = 14,\n-\t[2362] = 15,\n-\t[2364] = 16,\n-\t[2366] = 17,\n-\t[2368] = 18,\n-\t[2370] = 19,\n-\t[2372] = 20,\n-\t[2374] = 21,\n+\t[2312] = 5,\n+\t[2314] = 6,\n+\t[2316] = 7,\n+\t[2318] = 8,\n+\t[2320] = 9,\n+\t[2322] = 10,\n+\t[2324] = 11,\n+\t[2326] = 12,\n+\t[2328] = 13,\n+\t[2330] = 14,\n+\t[2376] = 15,\n+\t[2378] = 16,\n+\t[2380] = 17,\n+\t[2382] = 18,\n \t[2432] = 0,\n \t[2433] = 1,\n \t[2434] = 2,\n@@ -385,81 +382,60 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2470] = 10,\n \t[2472] = 11,\n \t[2474] = 12,\n-\t[2504] = 13,\n-\t[2506] = 14,\n-\t[2508] = 15,\n-\t[2510] = 16,\n \t[2560] = 0,\n \t[2561] = 1,\n \t[2562] = 2,\n \t[2564] = 3,\n \t[2566] = 4,\n-\t[2568] = 8,\n-\t[2570] = 9,\n-\t[2572] = 10,\n-\t[2574] = 11,\n-\t[2576] = 12,\n-\t[2578] = 13,\n-\t[2580] = 14,\n-\t[2582] = 15,\n-\t[2584] = 16,\n-\t[2586] = 17,\n-\t[2614] = 18,\n-\t[2616] = 19,\n-\t[2618] = 20,\n-\t[2620] = 21,\n-\t[2622] = 22,\n-\t[2624] = 23,\n-\t[2626] = 24,\n-\t[2628] = 25,\n-\t[2630] = 26,\n-\t[2640] = 5,\n-\t[2644] = 6,\n-\t[2648] = 7,\n+\t[2588] = 5,\n+\t[2590] = 6,\n+\t[2592] = 7,\n+\t[2594] = 8,\n+\t[2596] = 9,\n+\t[2598] = 10,\n+\t[2600] = 11,\n+\t[2602] = 12,\n+\t[2614] = 13,\n+\t[2616] = 14,\n+\t[2618] = 15,\n+\t[2620] = 16,\n+\t[2622] = 17,\n+\t[2624] = 18,\n+\t[2626] = 19,\n+\t[2628] = 20,\n+\t[2630] = 21,\n \t[2688] = 0,\n \t[2689] = 1,\n \t[2690] = 2,\n \t[2692] = 3,\n \t[2694] = 4,\n-\t[2696] = 8,\n-\t[2698] = 9,\n-\t[2700] = 10,\n-\t[2702] = 11,\n-\t[2704] = 12,\n-\t[2706] = 13,\n-\t[2708] = 14,\n-\t[2710] = 15,\n-\t[2712] = 16,\n-\t[2714] = 17,\n-\t[2760] = 18,\n-\t[2762] = 19,\n-\t[2764] = 20,\n-\t[2766] = 21,\n-\t[2768] = 5,\n-\t[2772] = 6,\n-\t[2776] = 7,\n+\t[2716] = 5,\n+\t[2718] = 6,\n+\t[2720] = 7,\n+\t[2722] = 8,\n+\t[2724] = 9,\n+\t[2726] = 10,\n+\t[2728] = 11,\n+\t[2730] = 12,\n+\t[2760] = 13,\n+\t[2762] = 14,\n+\t[2764] = 15,\n+\t[2766] = 16,\n \t[2816] = 0,\n \t[2817] = 1,\n \t[2818] = 2,\n \t[2820] = 3,\n \t[2822] = 4,\n-\t[2844] = 8,\n-\t[2846] = 9,\n-\t[2848] = 10,\n-\t[2850] = 11,\n-\t[2852] = 12,\n-\t[2854] = 13,\n-\t[2856] = 14,\n-\t[2858] = 15,\n-\t[2870] = 16,\n-\t[2872] = 17,\n-\t[2874] = 18,\n-\t[2876] = 19,\n-\t[2878] = 20,\n-\t[2880] = 21,\n-\t[2882] = 22,\n-\t[2884] = 23,\n-\t[2886] = 24,\n+\t[2824] = 8,\n+\t[2826] = 9,\n+\t[2828] = 10,\n+\t[2830] = 11,\n+\t[2832] = 12,\n+\t[2834] = 13,\n+\t[2836] = 14,\n+\t[2838] = 15,\n+\t[2840] = 16,\n+\t[2842] = 17,\n \t[2896] = 5,\n \t[2900] = 6,\n \t[2904] = 7,\n@@ -468,20 +444,348 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2946] = 2,\n \t[2948] = 3,\n \t[2950] = 4,\n-\t[2972] = 8,\n-\t[2974] = 9,\n-\t[2976] = 10,\n-\t[2978] = 11,\n-\t[2980] = 12,\n-\t[2982] = 13,\n-\t[2984] = 14,\n-\t[2986] = 15,\n-\t[3016] = 16,\n-\t[3018] = 17,\n-\t[3020] = 18,\n-\t[3022] = 19,\n+\t[2952] = 8,\n+\t[2954] = 9,\n+\t[2956] = 10,\n+\t[2958] = 11,\n+\t[2960] = 12,\n+\t[2962] = 13,\n+\t[2964] = 14,\n+\t[2966] = 15,\n+\t[2968] = 16,\n+\t[2970] = 17,\n+\t[2998] = 18,\n+\t[3000] = 19,\n+\t[3002] = 20,\n+\t[3004] = 21,\n+\t[3006] = 22,\n+\t[3008] = 23,\n+\t[3010] = 24,\n+\t[3012] = 25,\n+\t[3014] = 26,\n \t[3024] = 5,\n \t[3028] = 6,\n-\t[3032] = 7\n+\t[3032] = 7,\n+\t[3072] = 0,\n+\t[3073] = 1,\n+\t[3074] = 2,\n+\t[3076] = 3,\n+\t[3078] = 4,\n+\t[3080] = 8,\n+\t[3082] = 9,\n+\t[3084] = 10,\n+\t[3086] = 11,\n+\t[3088] = 12,\n+\t[3090] = 13,\n+\t[3092] = 14,\n+\t[3094] = 15,\n+\t[3096] = 16,\n+\t[3098] = 17,\n+\t[3144] = 18,\n+\t[3146] = 19,\n+\t[3148] = 20,\n+\t[3150] = 21,\n+\t[3152] = 5,\n+\t[3156] = 6,\n+\t[3160] = 7,\n+\t[3200] = 0,\n+\t[3201] = 1,\n+\t[3202] = 2,\n+\t[3204] = 3,\n+\t[3206] = 4,\n+\t[3228] = 8,\n+\t[3230] = 9,\n+\t[3232] = 10,\n+\t[3234] = 11,\n+\t[3236] = 12,\n+\t[3238] = 13,\n+\t[3240] = 14,\n+\t[3242] = 15,\n+\t[3280] = 5,\n+\t[3284] = 6,\n+\t[3288] = 7,\n+\t[3328] = 0,\n+\t[3329] = 1,\n+\t[3330] = 2,\n+\t[3332] = 3,\n+\t[3334] = 4,\n+\t[3356] = 8,\n+\t[3358] = 9,\n+\t[3360] = 10,\n+\t[3362] = 11,\n+\t[3364] = 12,\n+\t[3366] = 13,\n+\t[3368] = 14,\n+\t[3370] = 15,\n+\t[3382] = 16,\n+\t[3384] = 17,\n+\t[3386] = 18,\n+\t[3388] = 19,\n+\t[3390] = 20,\n+\t[3392] = 21,\n+\t[3394] = 22,\n+\t[3396] = 23,\n+\t[3398] = 24,\n+\t[3408] = 5,\n+\t[3412] = 6,\n+\t[3416] = 7,\n+\t[3456] = 0,\n+\t[3457] = 1,\n+\t[3458] = 2,\n+\t[3460] = 3,\n+\t[3462] = 4,\n+\t[3484] = 8,\n+\t[3486] = 9,\n+\t[3488] = 10,\n+\t[3490] = 11,\n+\t[3492] = 12,\n+\t[3494] = 13,\n+\t[3496] = 14,\n+\t[3498] = 15,\n+\t[3528] = 16,\n+\t[3530] = 17,\n+\t[3532] = 18,\n+\t[3534] = 19,\n+\t[3536] = 5,\n+\t[3540] = 6,\n+\t[3544] = 7,\n+\t[4096] = 0,\n+\t[4097] = 1,\n+\t[4098] = 2,\n+\t[4100] = 3,\n+\t[4102] = 4,\n+\t[4104] = 5,\n+\t[4106] = 6,\n+\t[4108] = 7,\n+\t[4110] = 8,\n+\t[4112] = 9,\n+\t[4114] = 10,\n+\t[4116] = 11,\n+\t[4118] = 12,\n+\t[4120] = 13,\n+\t[4122] = 14,\n+\t[4224] = 0,\n+\t[4225] = 1,\n+\t[4226] = 2,\n+\t[4228] = 3,\n+\t[4230] = 4,\n+\t[4232] = 5,\n+\t[4234] = 6,\n+\t[4236] = 7,\n+\t[4238] = 8,\n+\t[4240] = 9,\n+\t[4242] = 10,\n+\t[4244] = 11,\n+\t[4246] = 12,\n+\t[4248] = 13,\n+\t[4250] = 14,\n+\t[4278] = 15,\n+\t[4280] = 16,\n+\t[4282] = 17,\n+\t[4284] = 18,\n+\t[4286] = 19,\n+\t[4288] = 20,\n+\t[4290] = 21,\n+\t[4292] = 22,\n+\t[4294] = 23,\n+\t[4352] = 0,\n+\t[4353] = 1,\n+\t[4354] = 2,\n+\t[4356] = 3,\n+\t[4358] = 4,\n+\t[4360] = 5,\n+\t[4362] = 6,\n+\t[4364] = 7,\n+\t[4366] = 8,\n+\t[4368] = 9,\n+\t[4370] = 10,\n+\t[4372] = 11,\n+\t[4374] = 12,\n+\t[4376] = 13,\n+\t[4378] = 14,\n+\t[4424] = 15,\n+\t[4426] = 16,\n+\t[4428] = 17,\n+\t[4430] = 18,\n+\t[4480] = 0,\n+\t[4481] = 1,\n+\t[4482] = 2,\n+\t[4484] = 3,\n+\t[4486] = 4,\n+\t[4508] = 5,\n+\t[4510] = 6,\n+\t[4512] = 7,\n+\t[4514] = 8,\n+\t[4516] = 9,\n+\t[4518] = 10,\n+\t[4520] = 11,\n+\t[4522] = 12,\n+\t[4608] = 0,\n+\t[4609] = 1,\n+\t[4610] = 2,\n+\t[4612] = 3,\n+\t[4614] = 4,\n+\t[4636] = 5,\n+\t[4638] = 6,\n+\t[4640] = 7,\n+\t[4642] = 8,\n+\t[4644] = 9,\n+\t[4646] = 10,\n+\t[4648] = 11,\n+\t[4650] = 12,\n+\t[4662] = 13,\n+\t[4664] = 14,\n+\t[4666] = 15,\n+\t[4668] = 16,\n+\t[4670] = 17,\n+\t[4672] = 18,\n+\t[4674] = 19,\n+\t[4676] = 20,\n+\t[4678] = 21,\n+\t[4736] = 0,\n+\t[4737] = 1,\n+\t[4738] = 2,\n+\t[4740] = 3,\n+\t[4742] = 4,\n+\t[4764] = 5,\n+\t[4766] = 6,\n+\t[4768] = 7,\n+\t[4770] = 8,\n+\t[4772] = 9,\n+\t[4774] = 10,\n+\t[4776] = 11,\n+\t[4778] = 12,\n+\t[4808] = 13,\n+\t[4810] = 14,\n+\t[4812] = 15,\n+\t[4814] = 16,\n+\t[4864] = 0,\n+\t[4865] = 1,\n+\t[4866] = 2,\n+\t[4868] = 3,\n+\t[4870] = 4,\n+\t[4872] = 8,\n+\t[4874] = 9,\n+\t[4876] = 10,\n+\t[4878] = 11,\n+\t[4880] = 12,\n+\t[4882] = 13,\n+\t[4884] = 14,\n+\t[4886] = 15,\n+\t[4888] = 16,\n+\t[4890] = 17,\n+\t[4944] = 5,\n+\t[4948] = 6,\n+\t[4952] = 7,\n+\t[4992] = 0,\n+\t[4993] = 1,\n+\t[4994] = 2,\n+\t[4996] = 3,\n+\t[4998] = 4,\n+\t[5000] = 8,\n+\t[5002] = 9,\n+\t[5004] = 10,\n+\t[5006] = 11,\n+\t[5008] = 12,\n+\t[5010] = 13,\n+\t[5012] = 14,\n+\t[5014] = 15,\n+\t[5016] = 16,\n+\t[5018] = 17,\n+\t[5046] = 18,\n+\t[5048] = 19,\n+\t[5050] = 20,\n+\t[5052] = 21,\n+\t[5054] = 22,\n+\t[5056] = 23,\n+\t[5058] = 24,\n+\t[5060] = 25,\n+\t[5062] = 26,\n+\t[5072] = 5,\n+\t[5076] = 6,\n+\t[5080] = 7,\n+\t[5120] = 0,\n+\t[5121] = 1,\n+\t[5122] = 2,\n+\t[5124] = 3,\n+\t[5126] = 4,\n+\t[5128] = 8,\n+\t[5130] = 9,\n+\t[5132] = 10,\n+\t[5134] = 11,\n+\t[5136] = 12,\n+\t[5138] = 13,\n+\t[5140] = 14,\n+\t[5142] = 15,\n+\t[5144] = 16,\n+\t[5146] = 17,\n+\t[5192] = 18,\n+\t[5194] = 19,\n+\t[5196] = 20,\n+\t[5198] = 21,\n+\t[5200] = 5,\n+\t[5204] = 6,\n+\t[5208] = 7,\n+\t[5248] = 0,\n+\t[5249] = 1,\n+\t[5250] = 2,\n+\t[5252] = 3,\n+\t[5254] = 4,\n+\t[5276] = 8,\n+\t[5278] = 9,\n+\t[5280] = 10,\n+\t[5282] = 11,\n+\t[5284] = 12,\n+\t[5286] = 13,\n+\t[5288] = 14,\n+\t[5290] = 15,\n+\t[5328] = 5,\n+\t[5332] = 6,\n+\t[5336] = 7,\n+\t[5376] = 0,\n+\t[5377] = 1,\n+\t[5378] = 2,\n+\t[5380] = 3,\n+\t[5382] = 4,\n+\t[5404] = 8,\n+\t[5406] = 9,\n+\t[5408] = 10,\n+\t[5410] = 11,\n+\t[5412] = 12,\n+\t[5414] = 13,\n+\t[5416] = 14,\n+\t[5418] = 15,\n+\t[5430] = 16,\n+\t[5432] = 17,\n+\t[5434] = 18,\n+\t[5436] = 19,\n+\t[5438] = 20,\n+\t[5440] = 21,\n+\t[5442] = 22,\n+\t[5444] = 23,\n+\t[5446] = 24,\n+\t[5456] = 5,\n+\t[5460] = 6,\n+\t[5464] = 7,\n+\t[5504] = 0,\n+\t[5505] = 1,\n+\t[5506] = 2,\n+\t[5508] = 3,\n+\t[5510] = 4,\n+\t[5532] = 8,\n+\t[5534] = 9,\n+\t[5536] = 10,\n+\t[5538] = 11,\n+\t[5540] = 12,\n+\t[5542] = 13,\n+\t[5544] = 14,\n+\t[5546] = 15,\n+\t[5576] = 16,\n+\t[5578] = 17,\n+\t[5580] = 18,\n+\t[5582] = 19,\n+\t[5584] = 5,\n+\t[5588] = 6,\n+\t[5592] = 7\n };\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h\nindex befde44a1b..cccdcf5b72 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h\n@@ -36,6 +36,10 @@ bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[];\n extern struct\n bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[];\n \n+extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[];\n+\n+extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[];\n+\n /* STINGRAY template table declarations */\n extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[];\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\nindex 3de82a673f..8cc81b1451 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  8 14:57:13 2020 */\n+/* date: Thu Dec 17 19:43:07 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -25,12 +25,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {\n \t/* act_tid: 2, wh_plus, ingress */\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 6,\n+\t.num_tbls = 7,\n \t.start_tbl_idx = 5,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 }\n+\t},\n+\t/* act_tid: 3, wh_plus, ingress */\n+\t[3] = {\n+\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.num_tbls = 6,\n+\t.start_tbl_idx = 12,\n+\t.reject_info = {\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n+\t\t.cond_start_idx = 13,\n+\t\t.cond_nums = 0 }\n+\t},\n+\t/* act_tid: 4, wh_plus, egress */\n+\t[4] = {\n+\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.num_tbls = 5,\n+\t.start_tbl_idx = 18,\n+\t.reject_info = {\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 }\n+\t},\n+\t/* act_tid: 5, wh_plus, egress */\n+\t[5] = {\n+\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.num_tbls = 6,\n+\t.start_tbl_idx = 23,\n+\t.reject_info = {\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n+\t\t.cond_start_idx = 20,\n+\t\t.cond_nums = 0 }\n+\t},\n+\t/* act_tid: 6, wh_plus, egress */\n+\t[6] = {\n+\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.num_tbls = 6,\n+\t.start_tbl_idx = 29,\n+\t.reject_info = {\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n+\t\t.cond_start_idx = 23,\n+\t\t.cond_nums = 0 }\n \t}\n };\n \n@@ -42,13 +82,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 9,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.key_start_idx = 0,\n \t.blob_key_bit_size = 1,\n \t.key_bit_size = 1,\n@@ -63,14 +104,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 0,\n \t.result_bit_size = 64,\n@@ -84,14 +126,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 11,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 1,\n \t.result_bit_size = 0,\n@@ -106,14 +149,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 13,\n \t.result_bit_size = 128,\n@@ -128,19 +172,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.result_start_idx = 39,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.encap_num_fields = 12\n+\t},\n+\t{ /* act_tid: 2, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 12,\n+\t\t.cond_nums = 0 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n \t{ /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -149,16 +207,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 12,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 65,\n+\t.result_start_idx = 77,\n \t.result_bit_size = 32,\n \t.result_num_fields = 6\n \t},\n@@ -169,16 +229,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 12,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 71,\n+\t.result_start_idx = 83,\n \t.result_bit_size = 64,\n \t.result_num_fields = 1\n \t},\n@@ -190,16 +252,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 13,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 72,\n+\t.result_start_idx = 84,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -212,19 +276,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 13,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 98,\n+\t.result_start_idx = 110,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.encap_num_fields = 12\n \t},\n \t{ /* act_tid: 2, wh_plus, table: mirror_tbl.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n@@ -233,7 +299,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 13,\n \t\t.cond_nums = 0 },\n@@ -242,7 +309,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 124,\n+\t.result_start_idx = 148,\n \t.result_bit_size = 32,\n \t.result_num_fields = 6\n \t},\n@@ -253,133 +320,3643 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 13,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.key_start_idx = 1,\n \t.blob_key_bit_size = 1,\n \t.key_bit_size = 1,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 130,\n+\t.result_start_idx = 154,\n \t.result_bit_size = 34,\n \t.result_num_fields = 2\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC\n-\t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC\n+\t{ /* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_STATS_64,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 13,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 156,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST\n+\t{ /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 14,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 157,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST\n+\t{ /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 158,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST\n+\t{ /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n+\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.result_start_idx = 159,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 12\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t{ /* act_tid: 3, wh_plus, table: int_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 171,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID\n+\t{ /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_EXT,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 197,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 12\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP\n+\t{ /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_STATS_64,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 235,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE\n+\t{ /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 17,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 236,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 12\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t{ /* act_tid: 4, wh_plus, table: int_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 18,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 248,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t{ /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_EXT,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 18,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 274,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 12\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = {\n-\t/* act_tid: 1, wh_plus, table: shared_mirror_record.rd */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"shared_index\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"shared_index\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,\n-\t\t\tBNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}\n-\t\t}\n+\t{ /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_EXT,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 19,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 312,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 12\n \t},\n-\t/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"shared_index\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"shared_index\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}\n-\t\t}\n+\t{ /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_STATS_64,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 20,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 350,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 21,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 351,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 22,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 352,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 23,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n+\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.result_start_idx = 353,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 12\n+\t},\n+\t{ /* act_tid: 5, wh_plus, table: int_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 23,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 365,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n+\t},\n+\t{ /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_EXT,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 23,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 391,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 12\n+\t},\n+\t{ /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_STATS_64,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 23,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 429,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 24,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 430,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 3\n+\t},\n+\t{ /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 25,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 433,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 3\n+\t},\n+\t{ /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 26,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 436,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 12\n+\t},\n+\t{ /* act_tid: 6, wh_plus, table: int_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 26,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 448,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n+\t},\n+\t{ /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_EXT,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 26,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 474,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 12\n \t}\n };\n \n-struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n-\t/* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */\n+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {\n+\t/* cond_reject: wh_plus, act_tid: 1 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP\n+\t},\n+\t/* cond_execute: act_tid: 1, shared_mirror_record.rd */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE\n+\t},\n+\t/* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t},\n+\t/* cond_execute: act_tid: 1, int_vtag_encap_record.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n+\t/* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t},\n+\t/* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t},\n+\t/* cond_execute: act_tid: 3, act_modify_ipv4_src.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC\n+\t},\n+\t/* cond_execute: act_tid: 3, act_modify_ipv4_dst.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST\n+\t},\n+\t/* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t},\n+\t/* cond_execute: act_tid: 4, int_vtag_encap_record.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n+\t/* cond_execute: act_tid: 4, ext_full_act_record.no_tag */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n+\t/* cond_execute: act_tid: 4, ext_full_act_record.one_tag */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n+\t},\n+\t/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t},\n+\t/* cond_execute: act_tid: 5, act_modify_ipv4_src.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC\n+\t},\n+\t/* cond_execute: act_tid: 5, act_modify_ipv4_dst.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST\n+\t},\n+\t/* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n+\t},\n+\t/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG\n+\t},\n+\t/* cond_execute: act_tid: 6, sp_smac_ipv6.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = {\n+\t/* act_tid: 1, wh_plus, table: shared_mirror_record.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"shared_index\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"shared_index\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,\n+\t\t\tBNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}\n+\t\t}\n+\t},\n+\t/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"shared_index\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"shared_index\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}\n+\t\t}\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n+\t/* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */\n+\t{\n+\t.description = \"count\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 80,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 1, wh_plus, table: int_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_NONE}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"type\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 1, wh_plus, table: ext_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"flow_cntr_ext\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_NONE}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 0,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 2, wh_plus, table: mirror_tbl.alloc */\n+\t{\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"copy\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ign_drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"reserved\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"sp_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */\n+\t{\n+\t.description = \"count\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 2, wh_plus, table: int_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"type\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 2, wh_plus, table: ext_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"flow_cntr_ext\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 0,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 2, wh_plus, table: mirror_tbl.wr */\n+\t{\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"copy\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ign_drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"reserved\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"sp_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */\n+\t{\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"mirror_id\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\t(1 >> 8) & 0xff,\n+\t\t1 & 0xff}\n+\t},\n+\t/* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */\n+\t{\n+\t.description = \"count\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */\n+\t{\n+\t.description = \"ipv4_addr\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}\n+\t},\n+\t/* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */\n+\t{\n+\t.description = \"ipv4_addr\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}\n+\t},\n+\t/* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 80,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 3, wh_plus, table: int_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TL2},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_L2}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"type\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 3, wh_plus, table: ext_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"flow_cntr_ext\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"encap_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TL2},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_L2}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 0,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */\n+\t{\n+\t.description = \"count\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 80,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 4, wh_plus, table: int_full_act_record.0 */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"type\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"flow_cntr_ext\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 0,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */\n+\t{\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n+\t},\n+\t{\n+\t.description = \"flow_cntr_ext\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"encap_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t},\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 0,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */\n+\t{\n+\t.description = \"count\",\n+\t.field_bit_size = 64,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */\n+\t{\n+\t.description = \"ipv4_addr\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}\n+\t},\n+\t/* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */\n \t{\n-\t.description = \"count\",\n-\t.field_bit_size = 64,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"ipv4_addr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}\n \t},\n-\t/* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */\n+\t/* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n@@ -406,16 +3983,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n \t},\n \t{\n \t.description = \"ecv_vtag_type\",\n \t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_custom_en\",\n@@ -429,25 +4006,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"vtag_tpid\",\n \t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_vid\",\n \t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_de\",\n@@ -459,11 +4034,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"vtag_pcp\",\n \t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"spare\",\n@@ -472,7 +4045,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* act_tid: 1, wh_plus, table: int_full_act_record.0 */\n+\t/* act_tid: 5, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -543,10 +4116,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n+\t\t(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n@@ -574,7 +4147,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n \t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n@@ -602,7 +4175,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n \t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n@@ -646,22 +4219,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n \t.field_cond_opr = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\tULP_WP_SYM_DECAP_FUNC_THRU_TUN},\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TL2},\n \t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr2 = {\n-\t\tULP_WP_SYM_DECAP_FUNC_NONE}\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_L2}\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n@@ -669,23 +4242,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n-\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n@@ -697,36 +4262,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n-\t.field_cond_opr = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n-\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n@@ -742,7 +4287,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* act_tid: 1, wh_plus, table: ext_full_act_record.0 */\n+\t/* act_tid: 5, wh_plus, table: ext_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -819,16 +4364,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}\n \t},\n \t{\n \t.description = \"encap_rec_int\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n@@ -856,7 +4405,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n \t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n@@ -884,7 +4433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n \t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n@@ -894,122 +4443,270 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_rdir\",\n-\t.field_bit_size = 1,\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"l3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t},\n+\t{\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TL2},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_L2}\n+\t},\n+\t{\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"pop_vlan\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"meter\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L2_EN_YES}\n+\t},\n+\t{\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"ecv_valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_tpid\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_vid\",\n+\t.field_bit_size = 12,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_de\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"vtag_pcp\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"spare\",\n+\t.field_bit_size = 0,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */\n \t{\n-\t.description = \"tl3_rdir\",\n-\t.field_bit_size = 1,\n+\t.description = \"count\",\n+\t.field_bit_size = 64,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */\n \t{\n-\t.description = \"l3_ttl_dec\",\n-\t.field_bit_size = 1,\n+\t.description = \"smac\",\n+\t.field_bit_size = 48,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}\n \t},\n \t{\n-\t.description = \"tl3_ttl_dec\",\n-\t.field_bit_size = 1,\n+\t.description = \"ipv4_src_addr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}\n \t},\n \t{\n-\t.description = \"decap_func\",\n-\t.field_bit_size = 4,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n-\t.field_cond_opr = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\tULP_WP_SYM_DECAP_FUNC_THRU_TUN},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr2 = {\n-\t\tULP_WP_SYM_DECAP_FUNC_NONE}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 48,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */\n \t{\n-\t.description = \"vnic_or_vport\",\n-\t.field_bit_size = 12,\n+\t.description = \"smac\",\n+\t.field_bit_size = 48,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}\n \t},\n \t{\n-\t.description = \"pop_vlan\",\n-\t.field_bit_size = 1,\n+\t.description = \"ipv6_src_addr\",\n+\t.field_bit_size = 128,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}\n \t},\n \t{\n-\t.description = \"meter\",\n-\t.field_bit_size = 1,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */\n \t{\n-\t.description = \"mirror\",\n-\t.field_bit_size = 2,\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}\n+\t\tULP_WP_SYM_ECV_TUN_TYPE_VXLAN}\n \t},\n \t{\n-\t.description = \"drop\",\n-\t.field_bit_size = 1,\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n+\t\tULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}\n \t},\n-\t/* act_tid: 2, wh_plus, table: mirror_tbl.alloc */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}\n \t},\n \t{\n-\t.description = \"enable\",\n+\t.description = \"ecv_l2_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -1018,42 +4715,85 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t\t1}\n \t},\n \t{\n-\t.description = \"copy\",\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ign_drop\",\n+\t.description = \"ecv_valid\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 2,\n+\t.description = \"encap_l2_dmac\",\n+\t.field_bit_size = 48,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"encap_vtag\",\n+\t.field_bit_size = 0,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}\n \t},\n \t{\n-\t.description = \"sp_ptr\",\n-\t.field_bit_size = 11,\n+\t.description = \"encap_ip\",\n+\t.field_bit_size = 0,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}\n \t},\n-\t/* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */\n \t{\n-\t.description = \"count\",\n-\t.field_bit_size = 64,\n+\t.description = \"encap_udp\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}\n+\t},\n+\t{\n+\t.description = \"encap_tun\",\n+\t.field_bit_size = 0,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff}\n \t},\n-\t/* act_tid: 2, wh_plus, table: int_full_act_record.0 */\n+\t/* act_tid: 6, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -1123,9 +4863,11 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n@@ -1203,8 +4945,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n@@ -1223,14 +4965,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr2 = {\n-\t\t1}\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n@@ -1253,7 +4990,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* act_tid: 2, wh_plus, table: ext_full_act_record.0 */\n+\t/* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -1417,23 +5154,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n-\t.field_opr1 = {\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n@@ -1445,14 +5174,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr2 = {\n-\t\t1}\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n@@ -1461,18 +5185,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* act_tid: 2, wh_plus, table: mirror_tbl.wr */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 16,\n+\t.description = \"ecv_tun_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t\tULP_WP_SYM_ECV_TUN_TYPE_VXLAN}\n \t},\n \t{\n-\t.description = \"enable\",\n+\t.description = \"ecv_l4_type\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}\n+\t},\n+\t{\n+\t.description = \"ecv_l3_type\",\n+\t.field_bit_size = 3,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}\n+\t},\n+\t{\n+\t.description = \"ecv_l2_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -1481,55 +5222,80 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t\t1}\n \t},\n \t{\n-\t.description = \"copy\",\n+\t.description = \"ecv_vtag_type\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}\n+\t},\n+\t{\n+\t.description = \"ecv_custom_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ign_drop\",\n+\t.description = \"ecv_valid\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 2,\n+\t.description = \"encap_l2_dmac\",\n+\t.field_bit_size = 48,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"encap_vtag\",\n+\t.field_bit_size = 0,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}\n \t},\n \t{\n-\t.description = \"sp_ptr\",\n-\t.field_bit_size = 11,\n+\t.description = \"encap_ip\",\n+\t.field_bit_size = 0,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}\n \t},\n-\t/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */\n \t{\n-\t.description = \"rid\",\n+\t.description = \"encap_udp\",\n \t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_FID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_FID & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}\n \t},\n \t{\n-\t.description = \"mirror_id\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.description = \"encap_tun\",\n+\t.field_bit_size = 80,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},\n-\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr2 = {\n-\t\t(1 >> 8) & 0xff,\n-\t\t1 & 0xff}\n+\t\t(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,\n+\t\tBNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff}\n \t}\n };\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\nindex 608150dce8..85e4301bb3 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Tue Dec  8 14:57:13 2020 */\n+/* date: Thu Dec 17 17:35:03 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -22,41 +22,41 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 0 }\n \t},\n-\t/* class_tid: 2, wh_plus, ingress */\n+\t/* class_tid: 2, wh_plus, egress */\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 6,\n+\t.num_tbls = 11,\n \t.start_tbl_idx = 11,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 6,\n+\t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 }\n \t},\n-\t/* class_tid: 3, wh_plus, egress */\n+\t/* class_tid: 3, wh_plus, ingress */\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 8,\n-\t.start_tbl_idx = 17,\n+\t.start_tbl_idx = 22,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 6,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 4, wh_plus, egress */\n \t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 8,\n-\t.start_tbl_idx = 25,\n+\t.num_tbls = 14,\n+\t.start_tbl_idx = 30,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 5, wh_plus, egress */\n \t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 7,\n-\t.start_tbl_idx = 33,\n+\t.num_tbls = 9,\n+\t.start_tbl_idx = 44,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 14,\n@@ -65,39 +65,72 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t/* class_tid: 6, wh_plus, egress */\n \t[6] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n+\t.num_tbls = 9,\n+\t.start_tbl_idx = 53,\n+\t.reject_info = {\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 }\n+\t},\n+\t/* class_tid: 7, wh_plus, egress */\n+\t[7] = {\n+\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 1,\n-\t.start_tbl_idx = 40,\n+\t.start_tbl_idx = 62,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 16,\n \t\t.cond_nums = 0 }\n \t}\n };\n \n struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n+\t{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 2,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 0,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 0,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 0,\n+\t.ident_nums = 1\n+\t},\n \t{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 0,\n+\t.key_start_idx = 1,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n \t.result_start_idx = 0,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 0,\n+\t.ident_start_idx = 1,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n@@ -107,81 +140,86 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 13,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 14,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.ident_start_idx = 1,\n+\t.ident_start_idx = 2,\n \t.ident_nums = 3\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: branch.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n+\t{ /* class_tid: 1, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 4,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 4,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n+\t{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 2,\n+\t\t.cond_true_goto  = 2,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 1,\n+\t\t.cond_start_idx = 2,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 16,\n+\t.key_start_idx = 17,\n \t.blob_key_bit_size = 81,\n \t.key_bit_size = 81,\n \t.key_num_fields = 43,\n \t.result_start_idx = 13,\n \t.result_bit_size = 38,\n-\t.result_num_fields = 8,\n-\t.ident_start_idx = 4,\n+\t.result_num_fields = 17,\n+\t.ident_start_idx = 5,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n+\t{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 3,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 59,\n+\t.key_start_idx = 60,\n \t.blob_key_bit_size = 81,\n \t.key_bit_size = 81,\n \t.key_num_fields = 43,\n-\t.result_start_idx = 21,\n+\t.result_start_idx = 30,\n \t.result_bit_size = 38,\n-\t.result_num_fields = 8,\n-\t.ident_start_idx = 5,\n+\t.result_num_fields = 17,\n+\t.ident_start_idx = 6,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n@@ -191,858 +229,6669 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 3,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 102,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 103,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.result_start_idx = 29,\n+\t.result_start_idx = 47,\n \t.result_bit_size = 66,\n \t.result_num_fields = 5\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: em.ipv4_0 */\n+\t{ /* class_tid: 1, wh_plus, table: em.ipv4 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n \t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 3,\n \t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 105,\n+\t.key_start_idx = 106,\n \t.blob_key_bit_size = 176,\n \t.key_bit_size = 176,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 34,\n+\t.result_start_idx = 52,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: eem.ipv4_0 */\n+\t{ /* class_tid: 1, wh_plus, table: eem.ipv4 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n \t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 3,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 3,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 4,\n+\t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 115,\n+\t.key_start_idx = 116,\n \t.blob_key_bit_size = 448,\n \t.key_bit_size = 448,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 43,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 61,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: em.ipv6_0 */\n+\t{ /* class_tid: 1, wh_plus, table: em.ipv6 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n \t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 125,\n+\t.key_start_idx = 127,\n \t.blob_key_bit_size = 416,\n \t.key_bit_size = 416,\n \t.key_num_fields = 11,\n-\t.result_start_idx = 52,\n+\t.result_start_idx = 70,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: eem.ipv6_0 */\n+\t{ /* class_tid: 1, wh_plus, table: eem.ipv6 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n \t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 5,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 4,\n+\t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 136,\n+\t.key_start_idx = 138,\n \t.blob_key_bit_size = 448,\n \t.key_bit_size = 448,\n \t.key_num_fields = 11,\n-\t.result_start_idx = 61,\n+\t.result_start_idx = 79,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: branch.last */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_goto = 0,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n-\t\t.cond_nums = 0 },\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: int_full_act_record.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n-\t.direction = TF_DIR_RX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t\t.cond_true_goto  = 2,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 4,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 70,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 149,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 7,\n+\t.ident_nums = 1\n \t},\n \t{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.direction = TF_DIR_RX,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n+\t\t.cond_start_idx = 5,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 147,\n+\t.key_start_idx = 150,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 96,\n+\t.result_start_idx = 88,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 6,\n+\t.ident_start_idx = 8,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t{ /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 160,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.result_start_idx = 109,\n-\t.result_bit_size = 62,\n-\t.result_num_fields = 4\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 113,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 114,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n-\t.direction = TF_DIR_RX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n+\t\t.cond_start_idx = 5,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 115,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 163,\n+\t.blob_key_bit_size = 14,\n+\t.key_bit_size = 14,\n+\t.key_num_fields = 3,\n+\t.ident_start_idx = 9,\n+\t.ident_nums = 3\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t{ /* class_tid: 2, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 6,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 4,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 5,\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 116,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t{ /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 2,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 6,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 161,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 142,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 7,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 7,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 174,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 7,\n+\t.key_start_idx = 166,\n+\t.blob_key_bit_size = 81,\n+\t.key_bit_size = 81,\n+\t.key_num_fields = 43,\n+\t.result_start_idx = 101,\n+\t.result_bit_size = 38,\n+\t.result_num_fields = 17,\n+\t.ident_start_idx = 12,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{ /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 8,\n-\t\t.cond_nums = 2 },\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 7,\n+\t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 175,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 155,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 8,\n+\t.key_start_idx = 209,\n+\t.blob_key_bit_size = 81,\n+\t.key_bit_size = 81,\n+\t.key_num_fields = 43,\n+\t.result_start_idx = 118,\n+\t.result_bit_size = 38,\n+\t.result_num_fields = 17,\n+\t.ident_start_idx = 13,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t{ /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n-\t\t.cond_start_idx = 10,\n-\t\t.cond_nums = 2 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 188,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.result_start_idx = 168,\n-\t.result_bit_size = 62,\n-\t.result_num_fields = 4\n-\t},\n-\t{ /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 7,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 172,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 252,\n+\t.blob_key_bit_size = 14,\n+\t.key_bit_size = 14,\n+\t.key_num_fields = 3,\n+\t.result_start_idx = 135,\n+\t.result_bit_size = 66,\n+\t.result_num_fields = 5\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n+\t{ /* class_tid: 2, wh_plus, table: em.ipv4 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n+\t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 12,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 7,\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 173,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 255,\n+\t.blob_key_bit_size = 176,\n+\t.key_bit_size = 176,\n+\t.key_num_fields = 10,\n+\t.result_start_idx = 140,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n-\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n+\t{ /* class_tid: 2, wh_plus, table: eem.ipv4 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n+\t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 174,\n-\t.result_bit_size = 32,\n-\t.result_num_fields = 1\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 265,\n+\t.blob_key_bit_size = 448,\n+\t.key_bit_size = 448,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 149,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t{ /* class_tid: 2, wh_plus, table: em.ipv6 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n+\t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 189,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.ident_start_idx = 9,\n-\t.ident_nums = 1\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 276,\n+\t.blob_key_bit_size = 416,\n+\t.key_bit_size = 416,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 158,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t{ /* class_tid: 2, wh_plus, table: eem.ipv6 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n+\t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_TX,\n+\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 175,\n-\t.result_bit_size = 0,\n-\t.result_num_fields = 0,\n-\t.encap_num_fields = 12\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n+\t.key_start_idx = 287,\n+\t.blob_key_bit_size = 448,\n+\t.key_bit_size = 448,\n+\t.key_num_fields = 11,\n+\t.result_start_idx = 167,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 9\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */\n+\t{ /* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n-\t.direction = TF_DIR_TX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 12,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 187,\n+\t.result_start_idx = 176,\n \t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.result_num_fields = 26\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 12,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.key_start_idx = 190,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 213,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 10,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 13,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 203,\n-\t.blob_key_bit_size = 8,\n-\t.key_bit_size = 8,\n-\t.key_num_fields = 1,\n-\t.result_start_idx = 226,\n-\t.result_bit_size = 62,\n-\t.result_num_fields = 4\n-\t},\n-\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n-\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 8,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 230,\n-\t.result_bit_size = 128,\n-\t.result_num_fields = 26,\n-\t.encap_num_fields = 0\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 298,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 14,\n+\t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t{ /* class_tid: 3, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 8,\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 204,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 256,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 10,\n-\t.ident_nums = 0\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 217,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 269,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.ident_start_idx = 10,\n-\t.ident_nums = 0\n-\t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n-\t.direction = TF_DIR_TX,\n-\t.execute_info = {\n-\t\t.cond_goto = 1,\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.key_start_idx = 230,\n+\t.key_start_idx = 299,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 282,\n+\t.result_start_idx = 202,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 10,\n+\t.ident_start_idx = 14,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.key_start_idx = 243,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 312,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 295,\n+\t.result_start_idx = 215,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n+\t{ /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 299,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 219,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */\n+\t{ /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 300,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 220,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */\n+\t{ /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n-\t.direction = TF_DIR_TX,\n+\t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 9,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n-\t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 301,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 221,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: int_full_act_record.ing */\n+\t{ /* class_tid: 4, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 6,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 9,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.vfr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n-\t.direction = TF_DIR_RX,\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 1,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n-\t.result_start_idx = 302,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.result_start_idx = 222,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 10,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 313,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 15,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: control.1 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 10,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_RX,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 14,\n+\t\t.cond_start_idx = 11,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n+\t.key_start_idx = 314,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 248,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 15,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 11,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 327,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 261,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 11,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 328,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 15,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: control.2 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 11,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 12,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 244,\n+\t.key_start_idx = 329,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 328,\n+\t.result_start_idx = 265,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n-\t.ident_start_idx = 11,\n-\t.ident_nums = 0\n+\t.ident_start_idx = 15,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n+\t\t.cond_start_idx = 12,\n+\t\t.cond_nums = 2 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 342,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 278,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: int_full_act_record.0 */\n+\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n-\t\t.cond_goto = 0,\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 14,\n \t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n-\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 341,\n+\t.result_start_idx = 282,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n-\t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n-\t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t{ /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 14,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 308,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6\n+\t{ /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 14,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 309,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6\n+\t{ /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 14,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,\n+\t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 310,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n-\t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 14,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 343,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 0\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n+\t{ /* class_tid: 5, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 14,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.key_start_idx = 344,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 311,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 0\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 357,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 324,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n+\t{ /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.result_start_idx = 328,\n+\t.result_bit_size = 0,\n+\t.result_num_fields = 0,\n+\t.encap_num_fields = 12\n \t},\n-\t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t{ /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.result_start_idx = 340,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n+\t},\n+\t{ /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.result_start_idx = 366,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26\n+\t},\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.key_start_idx = 358,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 392,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.key_start_idx = 371,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 405,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 384,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: control.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 15,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,\n+\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.key_start_idx = 385,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 418,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 16,\n+\t.ident_nums = 1\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.key_start_idx = 398,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.result_start_idx = 431,\n+\t.result_bit_size = 62,\n+\t.result_num_fields = 4\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n+\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 435,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n+\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 436,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n+\t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,\n+\t.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.result_start_idx = 437,\n+\t.result_bit_size = 32,\n+\t.result_num_fields = 1\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: int_full_act_record.ing */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 1,\n+\t\t.cond_false_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n+\t.result_start_idx = 438,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 0\n+\t},\n+\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n+\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,\n+\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n+\t.pri_operand = 0,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n+\t.key_start_idx = 399,\n+\t.blob_key_bit_size = 167,\n+\t.key_bit_size = 167,\n+\t.key_num_fields = 13,\n+\t.result_start_idx = 464,\n+\t.result_bit_size = 64,\n+\t.result_num_fields = 13,\n+\t.ident_start_idx = 17,\n+\t.ident_nums = 0\n+\t},\n+\t{ /* class_tid: 7, wh_plus, table: int_full_act_record.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n+\t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n+\t.direction = TF_DIR_TX,\n+\t.execute_info = {\n+\t\t.cond_true_goto  = 0,\n+\t\t.cond_false_goto = 0,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 16,\n+\t\t.cond_nums = 0 },\n+\t.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,\n+\t.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n+\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n+\t.result_start_idx = 477,\n+\t.result_bit_size = 128,\n+\t.result_num_fields = 26,\n+\t.encap_num_fields = 0\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n+\t/* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n+\t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC\n+\t},\n+\t/* cond_execute: class_tid: 1, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 1, profile_tcam.ipv4 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t},\n+\t/* cond_execute: class_tid: 1, em.ipv4 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t},\n+\t/* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n+\t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC\n+\t},\n+\t/* cond_execute: class_tid: 2, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 2, profile_tcam.ipv4 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t},\n+\t/* cond_execute: class_tid: 2, em.ipv4 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n+\t},\n+\t/* cond_execute: class_tid: 3, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 4, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n+\t},\n+\t/* cond_execute: class_tid: 4, control.1 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 4, control.2 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.wr */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n+\t},\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 5, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t},\n+\t/* cond_execute: class_tid: 6, control.0 */\n+\t{\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n+\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n+\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: em.ipv4 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: eem.ipv4 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: em.ipv6 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 1, wh_plus, table: eem.ipv6 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ONES,\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_L4 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_flags\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_err\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tun_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_is_udp_tcp\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl4_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_dst\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_ipv6_cmp_src\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_isIP\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl3_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_two_vtags\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_vtag_present\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_uc_mc_bc\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_hdr_valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hrec_next\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"reserved\",\n+\t\t.field_bit_size = 9,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"agg_error\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_0\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"pkt_type_1\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"recycle_cnt\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"prof_func_id\",\n+\t\t.field_bit_size = 7,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"hdr_sig_id\",\n+\t\t.field_bit_size = 5,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: em.ipv4 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.dst\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv4.src\",\n+\t\t.field_bit_size = 32,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: eem.ipv4 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 2, wh_plus, table: em.ipv6 */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.field_info_mask = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t\t}\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n-\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n-\t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1050,7 +6899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n+\t\t.description = \"o_eth.dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n@@ -1059,7 +6908,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n+\t\t.description = \"o_eth.dmac\",\n \t\t.field_bit_size = 48,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n@@ -1070,51 +6919,57 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 2, wh_plus, table: eem.ipv6 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"spare\",\n+\t\t.field_bit_size = 35,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1122,15 +6977,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n+\t\t.description = \"local_cos\",\n+\t\t.field_bit_size = 3,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1138,51 +6993,83 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.description = \"o_l4.dport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n+\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.description = \"o_l4.sport\",\n+\t\t.field_bit_size = 16,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"o_ipv6.ip_proto\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1190,33 +7077,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"o_ipv6.dst\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"o_ipv6.src\",\n+\t\t.field_bit_size = 128,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"o_eth.smac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1224,47 +7133,49 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"o_eth.dmac\",\n+\t\t.field_bit_size = 48,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n \t\t.field_opr1 = {\n-\t\t\t1}\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n+\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"l2_cntxt_id\",\n+\t\t.field_bit_size = 10,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1272,19 +7183,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"em_profile_id\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1292,27 +7204,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1320,48 +7232,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1369,8 +7264,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1378,26 +7273,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L4_HDR_VALID_YES}\n+\t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1405,15 +7300,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1421,15 +7316,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1437,17 +7332,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1455,17 +7348,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1473,37 +7364,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1511,27 +7396,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -1540,7 +7405,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -1549,8 +7414,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1558,17 +7423,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1576,17 +7444,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1594,26 +7465,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1621,15 +7493,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1637,15 +7509,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1653,8 +7525,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1662,24 +7534,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1687,15 +7561,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1703,15 +7577,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1719,17 +7593,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1737,15 +7609,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1753,15 +7625,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1769,15 +7641,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1785,15 +7657,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1801,24 +7675,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_error\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_error\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1826,40 +7705,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1867,15 +7754,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1883,15 +7770,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1899,8 +7786,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -1908,24 +7795,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1933,15 +7822,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1949,35 +7838,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -1985,16 +7870,30 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n+\t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n+\t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2003,15 +7902,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2019,7 +7918,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_1\",\n+\t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2028,7 +7927,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_1\",\n+\t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2055,27 +7954,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n-\t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2083,48 +7966,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2132,26 +7987,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L4_HDR_VALID_YES}\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2159,15 +8015,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2175,15 +8031,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2191,8 +8047,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2200,28 +8056,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2229,37 +8083,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2267,36 +8115,30 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_uc_mc_bc\",\n+\t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2305,16 +8147,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_type\",\n+\t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_type\",\n+\t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2323,17 +8163,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2341,8 +8179,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2350,58 +8188,66 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2409,33 +8255,36 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n+\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2443,31 +8292,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2475,17 +8328,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2493,15 +8344,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2509,15 +8360,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2525,31 +8376,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t2}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2557,24 +8412,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2582,8 +8441,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2591,47 +8450,57 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_two_vtags\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_two_vtags\",\n+\t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2639,15 +8508,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2655,8 +8524,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2664,24 +8533,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2689,15 +8560,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2705,35 +8576,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2741,7 +8608,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n+\t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2750,7 +8617,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2759,23 +8644,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"pkt_type_1\",\n+\t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2784,7 +8673,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"pkt_type_1\",\n+\t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -2811,11 +8700,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2823,8 +8712,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n+\t\t}\n+\t},\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2832,28 +8740,40 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t}\n+\t},\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n@@ -2861,27 +8781,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.ipv4_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2889,17 +8808,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -2907,161 +8824,97 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -3069,28 +8922,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t\t1}\n \t\t}\n \t},\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n+\t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -3099,27 +8952,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n+\t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: eem.ipv4_0 */\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n+\t\t.description = \"l2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -3127,17 +8980,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"l2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -3145,75 +8996,23 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"mac0_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -3222,84 +9021,58 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n+\t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n+\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"sparif\",\n+\t\t.field_bit_size = 4,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n+\t\t.description = \"tl2_ivlan_vid\",\n+\t\t.field_bit_size = 12,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n+\t\t.description = \"tl2_ovlan_vid\",\n+\t\t.field_bit_size = 12,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -3307,57 +9080,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n+\t\t.description = \"mac1_addr\",\n+\t\t.field_bit_size = 48,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n+\t\t.description = \"l2_num_vtags\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.ipv6_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tl2_num_vtags\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -3365,17 +9128,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n+\t\t.description = \"tun_hdr_type\",\n+\t\t.field_bit_size = 4,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n@@ -3383,2477 +9144,1474 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n+\t\t.description = \"key_type\",\n+\t\t.field_bit_size = 2,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n \t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t0xff,\n \t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.description = \"valid\",\n+\t\t.field_bit_size = 1,\n+\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n+\t\t\t1}\n \t\t}\n+\t}\n+};\n+\n+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n+\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t},\n+\t{\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"bd_act_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"byp_sp_lkup\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"pri_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */\n+\t{\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv6.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv6.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n-\t\t}\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv6.dst\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv6.dst\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n-\t\t}\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv6.src\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv6.src\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n-\t\t}\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.dmac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.dmac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, wh_plus, table: eem.ipv6_0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 35,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 35,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr2 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv6.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv6.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n-\t\t.field_cond_opr = {\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n-\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n-\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n-\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr2 = {\n-\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n-\t\t}\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv6.dst\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv6.dst\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv6.src\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv6.src\",\n-\t\t.field_bit_size = 128,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t7}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.dmac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.dmac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n-\t\t}\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n-\t\t}\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t{\n+\t.description = \"profile_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n-\t\t}\n+\t.description = \"wm_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n+\t/* class_tid: 1, wh_plus, table: em.ipv4 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n-\t\t}\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t/* class_tid: 1, wh_plus, table: eem.ipv4 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(413 >> 8) & 0xff,\n+\t\t413 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n+\t/* class_tid: 1, wh_plus, table: em.ipv6 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n+\t/* class_tid: 1, wh_plus, table: eem.ipv6 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(413 >> 8) & 0xff,\n+\t\t413 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n+\t},\n+\t{\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"l2_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,\n+\t.field_cond_opr = {\n+\t\t(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_LOOPBACK_PARIF},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr2 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"bd_act_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"byp_sp_lkup\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"pri_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t4}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t2}\n-\t\t}\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n-\t\t}\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"wc_key_id\",\n+\t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"wc_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff,\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n-\t\t}\n+\t.description = \"wc_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.0\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.1\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"em_key_mask.2\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"em_key_mask.3\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.4\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.5\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.6\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.7\",\n+\t.field_bit_size = 1,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"em_key_mask.8\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_key_mask.9\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n-\t\t}\n+\t.description = \"em_key_id\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t7}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"em_search_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"pl_byp_lkup_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"profile_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"wm_profile_id\",\n+\t.field_bit_size = 8,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"flow_sig_id\",\n+\t.field_bit_size = 8,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n+\t/* class_tid: 2, wh_plus, table: em.ipv4 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t/* class_tid: 2, wh_plus, table: eem.ipv4 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t\t.field_opr1 = {\n-\t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n-\t\t}\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(413 >> 8) & 0xff,\n+\t\t413 & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n+\t/* class_tid: 2, wh_plus, table: em.ipv6 */\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t\t}\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t\t.field_opr1 = {\n-\t\t\t1}\n-\t\t}\n-\t}\n-};\n-\n-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n-\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n+\t\t3}\n \t},\n \t{\n-\t.description = \"l2_byp_lkup_en\",\n+\t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n+\t.description = \"valid\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t\t1}\n \t},\n+\t/* class_tid: 2, wh_plus, table: eem.ipv6 */\n \t{\n-\t.description = \"allowed_pri\",\n-\t.field_bit_size = 8,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 33,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t},\n+\t{\n+\t.description = \"ext_flow_cntr\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"default_pri\",\n-\t.field_bit_size = 3,\n+\t.description = \"act_rec_int\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n \t},\n \t{\n-\t.description = \"allowed_tpid\",\n-\t.field_bit_size = 6,\n+\t.description = \"act_rec_size\",\n+\t.field_bit_size = 5,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n+\t},\n+\t{\n+\t.description = \"key_size\",\n+\t.field_bit_size = 9,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(413 >> 8) & 0xff,\n+\t\t413 & 0xff}\n \t},\n \t{\n-\t.description = \"default_tpid\",\n-\t.field_bit_size = 3,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 11,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"bd_act_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"strength\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n-\t.description = \"sp_rec_ptr\",\n-\t.field_bit_size = 16,\n+\t.description = \"l1_cacheable\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"byp_sp_lkup\",\n+\t.description = \"valid\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -5861,259 +10619,270 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t\t1}\n \t},\n+\t/* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n \t{\n-\t.description = \"pri_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tpid_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n+\t.description = \"age_enable\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"tcpflags_mir\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask\",\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t},\n+\t{\n+\t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t(125 >> 8) & 0xff,\n-\t\t125 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 5,\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_search_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"pl_byp_lkup_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n \t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n+\t.description = \"l3_rdir\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"tl3_rdir\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wc_search_en\",\n+\t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_mask\",\n-\t.field_bit_size = 10,\n+\t.description = \"tl3_ttl_dec\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t(249 >> 8) & 0xff,\n-\t\t249 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 5,\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t7}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}\n \t},\n \t{\n-\t.description = \"em_search_en\",\n+\t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"pl_byp_lkup_en\",\n+\t.description = \"meter\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n \t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"profile_tcam_index\",\n-\t.field_bit_size = 10,\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"wm_profile_id\",\n-\t.field_bit_size = 8,\n+\t.description = \"type\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t{\n-\t.description = \"flow_sig_id\",\n-\t.field_bit_size = 8,\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.ipv4_0 */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.description = \"prof_func_id\",\n+\t.field_bit_size = 7,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n+\t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t},\n+\t{\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"bd_act_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n+\t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n@@ -6121,416 +10890,404 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_opr1 = {\n \t\t1}\n \t},\n-\t/* class_tid: 1, wh_plus, table: eem.ipv4_0 */\n \t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.description = \"pri_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n+\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t(173 >> 8) & 0xff,\n-\t\t173 & 0xff}\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t3}\n-\t},\n-\t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n+\t/* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n \t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.ipv6_0 */\n+\t/* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n \t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n+\t/* class_tid: 4, wh_plus, table: int_full_act_record.vfr */\n \t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n+\t.description = \"flow_cntr_ptr\",\n+\t.field_bit_size = 14,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_int\",\n+\t.description = \"age_enable\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n+\t.description = \"agg_cntr_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"rate_cntr_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"flow_cntr_en\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"tcpflags_key\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n+\t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n+\t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n-\t},\n-\t/* class_tid: 1, wh_plus, table: eem.ipv6_0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n+\t.description = \"encap_ptr\",\n+\t.field_bit_size = 11,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n+\t.description = \"dst_ip_ptr\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n-\t},\n-\t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n+\t.description = \"tcp_dst_port\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t(413 >> 8) & 0xff,\n-\t\t413 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n+\t.description = \"src_ip_ptr\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n+\t.description = \"tcp_src_port\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t3}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n+\t.description = \"meter_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"valid\",\n+\t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: int_full_act_record.0 */\n-\t{\n-\t.description = \"flow_cntr_ptr\",\n-\t.field_bit_size = 14,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"age_enable\",\n+\t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"agg_cntr_en\",\n+\t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"rate_cntr_en\",\n+\t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"flow_cntr_en\",\n-\t.field_bit_size = 1,\n+\t.description = \"decap_func\",\n+\t.field_bit_size = 4,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tcpflags_key\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"vnic_or_vport\",\n+\t.field_bit_size = 12,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}\n \t},\n \t{\n-\t.description = \"tcpflags_mir\",\n+\t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tcpflags_match\",\n+\t.description = \"meter\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"encap_ptr\",\n-\t.field_bit_size = 11,\n+\t.description = \"mirror\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"dst_ip_ptr\",\n-\t.field_bit_size = 10,\n+\t.description = \"drop\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tcp_dst_port\",\n-\t.field_bit_size = 16,\n+\t.description = \"hit\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"src_ip_ptr\",\n-\t.field_bit_size = 10,\n+\t.description = \"type\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */\n \t{\n-\t.description = \"tcp_src_port\",\n+\t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meter_id\",\n-\t.field_bit_size = 10,\n+\t.description = \"reserved\",\n+\t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_rdir\",\n+\t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.description = \"tl3_rdir\",\n-\t.field_bit_size = 1,\n+\t.description = \"parif\",\n+\t.field_bit_size = 4,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n+\t},\n+\t{\n+\t.description = \"allowed_pri\",\n+\t.field_bit_size = 8,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"l3_ttl_dec\",\n-\t.field_bit_size = 1,\n+\t.description = \"default_pri\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"tl3_ttl_dec\",\n-\t.field_bit_size = 1,\n+\t.description = \"allowed_tpid\",\n+\t.field_bit_size = 6,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"decap_func\",\n-\t.field_bit_size = 4,\n+\t.description = \"default_tpid\",\n+\t.field_bit_size = 3,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"vnic_or_vport\",\n-\t.field_bit_size = 12,\n+\t.description = \"bd_act_en\",\n+\t.field_bit_size = 1,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}\n+\t\t1}\n \t},\n \t{\n-\t.description = \"pop_vlan\",\n-\t.field_bit_size = 1,\n+\t.description = \"sp_rec_ptr\",\n+\t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"meter\",\n+\t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n-\t.description = \"mirror\",\n+\t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"drop\",\n-\t.field_bit_size = 1,\n+\t.description = \"tpid_anti_spoof_ctl\",\n+\t.field_bit_size = 2,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */\n \t{\n-\t.description = \"hit\",\n-\t.field_bit_size = 1,\n+\t.description = \"rid\",\n+\t.field_bit_size = 32,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_tcam_index\",\n+\t.field_bit_size = 10,\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n+\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n+\t},\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"type\",\n-\t.field_bit_size = 1,\n+\t.description = \"src_property_ptr\",\n+\t.field_bit_size = 10,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n@@ -6562,8 +11319,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n@@ -6630,7 +11387,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -6665,37 +11422,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t/* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n+\t/* class_tid: 4, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -6880,140 +11607,66 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t/* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t{\n-\t.description = \"act_record_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"l2_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n+\t/* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */\n \t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n-\t},\n-\t{\n-\t.description = \"allowed_pri\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"default_pri\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"allowed_tpid\",\n-\t.field_bit_size = 6,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"default_tpid\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n+\t/* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t{\n-\t.description = \"bd_act_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n+\t.description = \"act_rec_ptr\",\n+\t.field_bit_size = 32,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n \t.field_opr1 = {\n-\t\t1}\n+\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n-\t.description = \"sp_rec_ptr\",\n+\t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n-\t.description = \"byp_sp_lkup\",\n+\t.description = \"reserved\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n-\t},\n-\t{\n-\t.description = \"pri_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"tpid_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n-\t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n@@ -7048,7 +11701,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n@@ -7080,7 +11735,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -7102,11 +11757,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n+\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n@@ -7115,37 +11768,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t/* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t/* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n-\t},\n-\t/* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */\n+\t/* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n@@ -7195,7 +11818,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_bit_size = 1,\n \t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"vtag_tpid\",\n@@ -7237,7 +11862,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */\n+\t/* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -7425,138 +12050,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n-\t{\n-\t.description = \"act_record_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"l2_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n-\t},\n-\t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"allowed_pri\",\n-\t.field_bit_size = 8,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"default_pri\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"allowed_tpid\",\n-\t.field_bit_size = 6,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"default_tpid\",\n-\t.field_bit_size = 3,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"bd_act_en\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n-\t},\n-\t{\n-\t.description = \"sp_rec_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"byp_sp_lkup\",\n-\t.field_bit_size = 1,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n-\t.field_opr1 = {\n-\t\t1}\n-\t},\n-\t{\n-\t.description = \"pri_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"tpid_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n-\t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n-\t},\n-\t{\n-\t.description = \"l2_cntxt_tcam_index\",\n-\t.field_bit_size = 10,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n-\t},\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t{\n-\t.description = \"src_property_ptr\",\n-\t.field_bit_size = 10,\n-\t.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,\n-\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n-\t},\n-\t/* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */\n+\t/* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -7743,7 +12237,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -7841,7 +12335,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -7939,7 +12433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n@@ -7969,10 +12463,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n-\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n-\t.field_opr1 = {\n-\t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff}\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {ULP_WP_SYM_LOOPBACK_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n@@ -8039,7 +12531,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n@@ -8074,7 +12566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n+\t/* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -8084,7 +12576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */\n+\t/* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -8094,7 +12586,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */\n+\t/* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n@@ -8104,7 +12596,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n \t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 5, wh_plus, table: int_full_act_record.ing */\n+\t/* class_tid: 6, wh_plus, table: int_full_act_record.ing */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -8289,7 +12781,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n@@ -8387,7 +12879,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n \t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, wh_plus, table: int_full_act_record.0 */\n+\t/* class_tid: 7, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n@@ -8576,6 +13068,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n };\n \n struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n+\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 42\n+\t},\n \t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -8587,10 +13086,10 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n \t{\n-\t.description = \"profile_tcam_index\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 32\n+\t.description = \"em_profile_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 42\n \t},\n \t{\n \t.description = \"flow_sig_id\",\n@@ -8599,12 +13098,12 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_pos = 58\n \t},\n \t{\n-\t.description = \"em_profile_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 42\n+\t.description = \"profile_tcam_index\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 32\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -8613,7 +13112,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -8622,6 +13121,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 42\n+\t},\n \t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -8631,13 +13137,43 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */\n \t{\n-\t.description = \"l2_cntxt_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n-\t.ident_bit_size = 10,\n+\t.description = \"em_profile_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n \t.ident_bit_pos = 42\n \t},\n+\t{\n+\t.description = \"flow_sig_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 58\n+\t},\n+\t{\n+\t.description = \"profile_tcam_index\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 32\n+\t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_EM_PROF,\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 28\n+\t},\n+\t/* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */\n+\t{\n+\t.description = \"em_profile_id\",\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_EM_PROF,\n+\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n+\t.ident_bit_size = 8,\n+\t.ident_bit_pos = 28\n+\t},\n \t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -8647,14 +13183,16 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n-\t.description = \"l2_cntxt_tcam_index\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n+\t.description = \"l2_cntxt_id\",\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n+\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n-\t.ident_bit_pos = 32\n+\t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\nindex af28283385..20a988a03a 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n@@ -81,6 +81,8 @@ struct ulp_rte_parser_params {\n \tstruct bnxt_ulp_context\t\t*ulp_ctx;\n \tuint32_t\t\t\thdr_sig_id;\n \tuint32_t\t\t\tflow_sig_id;\n+\tuint32_t\t\t\tflow_pattern_id;\n+\tuint32_t\t\t\tact_pattern_id;\n };\n \n /* Flow Parser Header Information Structure */\n@@ -128,6 +130,7 @@ struct bnxt_ulp_class_match_info {\n \tuint8_t\t\t\twc_pri;\n \tuint32_t\t\thdr_sig_id;\n \tuint32_t\t\tflow_sig_id;\n+\tuint32_t\t\tflow_pattern_id;\n };\n \n /* Flow Matcher templates Structure for class entries */\n@@ -144,6 +147,7 @@ struct bnxt_ulp_act_match_info {\n \tstruct ulp_rte_bitmap\tact_sig;\n \tuint32_t\t\tact_hid;\n \tuint32_t\t\tact_tid;\n+\tuint32_t\t\tact_pattern_id;\n };\n \n /* Flow Matcher templates Structure for action entries */\n@@ -160,7 +164,8 @@ struct bnxt_ulp_mapper_cond_list_info {\n \tenum bnxt_ulp_cond_list_opc cond_list_opcode;\n \tuint32_t cond_start_idx;\n \tuint32_t cond_nums;\n-\tuint32_t cond_goto;\n+\tint32_t cond_true_goto;\n+\tint32_t cond_false_goto;\n };\n \n struct bnxt_ulp_template_device_tbls {\n",
    "prefixes": [
        "v2",
        "39/58"
    ]
}