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GET /api/patches/938/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 938,
    "url": "https://patches.dpdk.org/api/patches/938/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1414070340-19128-10-git-send-email-jijiang.liu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1414070340-19128-10-git-send-email-jijiang.liu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1414070340-19128-10-git-send-email-jijiang.liu@intel.com",
    "date": "2014-10-23T13:18:59",
    "name": "[dpdk-dev,v7,09/10] i40e:support VxLAN Tx checksum offload",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "a71d31620942d262c4f6125f00d0e0bfa28198de",
    "submitter": {
        "id": 52,
        "url": "https://patches.dpdk.org/api/people/52/?format=api",
        "name": "Jijiang Liu",
        "email": "jijiang.liu@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1414070340-19128-10-git-send-email-jijiang.liu@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/938/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/938/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C92CB7EDB;\n\tThu, 23 Oct 2014 15:11:20 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 730C27EA8\n\tfor <dev@dpdk.org>; Thu, 23 Oct 2014 15:11:05 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP; 23 Oct 2014 06:19:28 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 23 Oct 2014 06:19:27 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s9NDJPkl026018;\n\tThu, 23 Oct 2014 21:19:25 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s9NDJNpD019227; Thu, 23 Oct 2014 21:19:25 +0800",
            "(from jijiangl@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s9NDJN7r019223; \n\tThu, 23 Oct 2014 21:19:23 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,774,1406617200\"; d=\"scan'208\";a=\"609960372\"",
        "From": "Jijiang Liu <jijiang.liu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Thu, 23 Oct 2014 21:18:59 +0800",
        "Message-Id": "<1414070340-19128-10-git-send-email-jijiang.liu@intel.com>",
        "X-Mailer": "git-send-email 1.7.12.2",
        "In-Reply-To": "<1414070340-19128-1-git-send-email-jijiang.liu@intel.com>",
        "References": "<1414070340-19128-1-git-send-email-jijiang.liu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v7 09/10] i40e:support VxLAN Tx checksum offload",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Support VxLAN Tx checksum offload, which include\n  - outer L3(IP) checksum offload\n  - inner L3(IP) checksum offload\n  - inner L4(UDP, TCP and SCTP) checksum offload\n\nSigned-off-by: Jijiang Liu <jijiang.liu@intel.com>\n---\n lib/librte_mbuf/rte_mbuf.h      |    1 +\n lib/librte_pmd_i40e/i40e_rxtx.c |   46 +++++++++++++++++++++++++++++++++-----\n 2 files changed, 41 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h\nindex 9af3bd9..a86dedf 100644\n--- a/lib/librte_mbuf/rte_mbuf.h\n+++ b/lib/librte_mbuf/rte_mbuf.h\n@@ -96,6 +96,7 @@ extern \"C\" {\n \n #define PKT_TX_VLAN_PKT      (1ULL << 55) /**< TX packet is a 802.1q VLAN packet. */\n #define PKT_TX_IP_CKSUM      (1ULL << 54) /**< IP cksum of TX pkt. computed by NIC. */\n+#define PKT_TX_VXLAN_CKSUM   (1ULL << 50) /**< TX checksum of VxLAN computed by NIC */\n #define PKT_TX_IPV4_CSUM     PKT_TX_IP_CKSUM /**< Alias of PKT_TX_IP_CKSUM. */\n #define PKT_TX_IPV4          PKT_RX_IPV4_HDR /**< IPv4 with no IP checksum offload. */\n #define PKT_TX_IPV6          PKT_RX_IPV6_HDR /**< IPv6 packet */\ndiff --git a/lib/librte_pmd_i40e/i40e_rxtx.c b/lib/librte_pmd_i40e/i40e_rxtx.c\nindex 2108290..7599df9 100644\n--- a/lib/librte_pmd_i40e/i40e_rxtx.c\n+++ b/lib/librte_pmd_i40e/i40e_rxtx.c\n@@ -411,11 +411,14 @@ i40e_rxd_ptype_to_pkt_flags(uint64_t qword)\n }\n \n static inline void\n-i40e_txd_enable_checksum(uint32_t ol_flags,\n+i40e_txd_enable_checksum(uint64_t ol_flags,\n \t\t\tuint32_t *td_cmd,\n \t\t\tuint32_t *td_offset,\n \t\t\tuint8_t l2_len,\n-\t\t\tuint8_t l3_len)\n+\t\t\tuint16_t l3_len,\n+\t\t\tuint8_t inner_l2_len,\n+\t\t\tuint16_t inner_l3_len,\n+\t\t\tuint32_t *cd_tunneling)\n {\n \tif (!l2_len) {\n \t\tPMD_DRV_LOG(DEBUG, \"L2 length set to 0\");\n@@ -428,6 +431,27 @@ i40e_txd_enable_checksum(uint32_t ol_flags,\n \t\treturn;\n \t}\n \n+\t/* VxLAN packet TX checksum offload */\n+\tif (unlikely(ol_flags & PKT_TX_VXLAN_CKSUM)) {\n+\t\tuint8_t l4tun_len;\n+\n+\t\tl4tun_len = ETHER_VXLAN_HLEN + inner_l2_len;\n+\n+\t\tif (ol_flags & PKT_TX_IPV4_CSUM)\n+\t\t\t*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;\n+\t\telse if (ol_flags & PKT_TX_IPV6)\n+\t\t\t*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;\n+\n+\t\t/* Now set the ctx descriptor fields */\n+\t\t*cd_tunneling |= (l3_len >> 2) <<\n+\t\t\t\tI40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |\n+\t\t\t\tI40E_TXD_CTX_UDP_TUNNELING |\n+\t\t\t\t(l4tun_len >> 1) <<\n+\t\t\t\tI40E_TXD_CTX_QW0_NATLEN_SHIFT;\n+\n+\t\tl3_len = inner_l3_len;\n+\t}\n+\n \t/* Enable L3 checksum offloads */\n \tif (ol_flags & PKT_TX_IPV4_CSUM) {\n \t\t*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;\n@@ -1077,7 +1101,10 @@ i40e_recv_scattered_pkts(void *rx_queue,\n static inline uint16_t\n i40e_calc_context_desc(uint64_t flags)\n {\n-\tuint16_t mask = 0;\n+\tuint64_t mask = 0ULL;\n+\n+\tif (flags | PKT_TX_VXLAN_CKSUM)\n+\t\tmask |= PKT_TX_VXLAN_CKSUM;\n \n #ifdef RTE_LIBRTE_IEEE1588\n \tmask |= PKT_TX_IEEE1588_TMST;\n@@ -1098,6 +1125,7 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tvolatile struct i40e_tx_desc *txr;\n \tstruct rte_mbuf *tx_pkt;\n \tstruct rte_mbuf *m_seg;\n+\tuint32_t cd_tunneling_params;\n \tuint16_t tx_id;\n \tuint16_t nb_tx;\n \tuint32_t td_cmd;\n@@ -1106,7 +1134,9 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tuint32_t td_tag;\n \tuint64_t ol_flags;\n \tuint8_t l2_len;\n-\tuint8_t l3_len;\n+\tuint16_t l3_len;\n+\tuint8_t inner_l2_len;\n+\tuint16_t inner_l3_len;\n \tuint16_t nb_used;\n \tuint16_t nb_ctx;\n \tuint16_t tx_last;\n@@ -1134,7 +1164,9 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \n \t\tol_flags = tx_pkt->ol_flags;\n \t\tl2_len = tx_pkt->l2_len;\n+\t\tinner_l2_len = tx_pkt->inner_l2_len;\n \t\tl3_len = tx_pkt->l3_len;\n+\t\tinner_l3_len = tx_pkt->inner_l3_len;\n \n \t\t/* Calculate the number of context descriptors needed. */\n \t\tnb_ctx = i40e_calc_context_desc(ol_flags);\n@@ -1182,15 +1214,17 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\ttd_cmd |= I40E_TX_DESC_CMD_ICRC;\n \n \t\t/* Enable checksum offloading */\n+\t\tcd_tunneling_params = 0;\n \t\ti40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,\n-\t\t\t\t\t\t\tl2_len, l3_len);\n+\t\t\t\t\t\tl2_len, l3_len, inner_l2_len,\n+\t\t\t\t\t\tinner_l3_len,\n+\t\t\t\t\t\t&cd_tunneling_params);\n \n \t\tif (unlikely(nb_ctx)) {\n \t\t\t/* Setup TX context descriptor if required */\n \t\t\tvolatile struct i40e_tx_context_desc *ctx_txd =\n \t\t\t\t(volatile struct i40e_tx_context_desc *)\\\n \t\t\t\t\t\t\t&txr[tx_id];\n-\t\t\tuint32_t cd_tunneling_params = 0;\n \t\t\tuint16_t cd_l2tag2 = 0;\n \t\t\tuint64_t cd_type_cmd_tso_mss =\n \t\t\t\tI40E_TX_DESC_DTYPE_CONTEXT;\n",
    "prefixes": [
        "dpdk-dev",
        "v7",
        "09/10"
    ]
}