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GET /api/patches/93679/?format=api
{ "id": 93679, "url": "https://patches.dpdk.org/api/patches/93679/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210601030644.3318-3-chenbo.xia@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210601030644.3318-3-chenbo.xia@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210601030644.3318-3-chenbo.xia@intel.com", "date": "2021-06-01T03:06:40", "name": "[RFC,v3,2/6] bus/pci: avoid depending on private value in kernel source", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "49d60aefe4610939fb13b46621800fa8b8a41eab", "submitter": { "id": 1276, "url": "https://patches.dpdk.org/api/people/1276/?format=api", "name": "Chenbo Xia", "email": "chenbo.xia@intel.com" }, "delegate": { "id": 24651, "url": "https://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210601030644.3318-3-chenbo.xia@intel.com/mbox/", "series": [ { "id": 17176, "url": "https://patches.dpdk.org/api/series/17176/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17176", "date": "2021-06-01T03:06:38", "name": "Add mdev (Mediated device) support in DPDK", "version": 3, "mbox": "https://patches.dpdk.org/series/17176/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/93679/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/93679/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 288EFA0524;\n\tTue, 1 Jun 2021 05:17:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1682F40DF7;\n\tTue, 1 Jun 2021 05:17:46 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 3970140040\n for <dev@dpdk.org>; Tue, 1 Jun 2021 05:17:44 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 31 May 2021 20:17:43 -0700", "from npg-dpdk-virtio-xiachenbo-nw.sh.intel.com ([10.67.118.250])\n by fmsmga002.fm.intel.com with ESMTP; 31 May 2021 20:17:35 -0700" ], "IronPort-SDR": [ "\n iJJi2XcnrGBMTsoW9PAvTU16UY3Af5VkHlm+Lj/dUamAGZifjOt8rHq1gUpLKB+YtOUNW4oPkO\n n2iaVLrBhslg==", "\n 6Aodv40XfJIh8masBc+PWu4B4keVaSrlV8DoFtzSbLDPjVZHHeRrwGjiMFSqscsiZf7dcer3gH\n JObLKpw4rc7g==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10001\"; a=\"267339139\"", "E=Sophos;i=\"5.83,239,1616482800\"; d=\"scan'208\";a=\"267339139\"", "E=Sophos;i=\"5.83,239,1616482800\"; d=\"scan'208\";a=\"482315408\"" ], "X-ExtLoop1": "1", "From": "Chenbo Xia <chenbo.xia@intel.com>", "To": "dev@dpdk.org, thomas@monjalon.net, cunming.liang@intel.com,\n jingjing.wu@intel.com", "Cc": "anatoly.burakov@intel.com, ferruh.yigit@intel.com, mdr@ashroe.eu,\n nhorman@tuxdriver.com, bruce.richardson@intel.com,\n david.marchand@redhat.com, stephen@networkplumber.org,\n konstantin.ananyev@intel.com, Tiwei Bie <tiwei.bie@intel.com>", "Date": "Tue, 1 Jun 2021 11:06:40 +0800", "Message-Id": "<20210601030644.3318-3-chenbo.xia@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210601030644.3318-1-chenbo.xia@intel.com>", "References": "<20190715075214.16616-6-tiwei.bie@intel.com>\n <20210601030644.3318-1-chenbo.xia@intel.com>", "Subject": "[dpdk-dev] [RFC v3 2/6] bus/pci: avoid depending on private value\n in kernel source", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tiwei Bie <tiwei.bie@intel.com>\n\nThe value 40 used in VFIO_GET_REGION_ADDR() is a private value\n(VFIO_PCI_OFFSET_SHIFT) defined in Linux kernel source [1]. It\nis not part of VFIO API, and we should not depend on it.\n\n[1] https://github.com/torvalds/linux/blob/v5.12/drivers/vfio/pci/vfio_pci_private.h\n\nSigned-off-by: Tiwei Bie <tiwei.bie@intel.com>\n---\n drivers/bus/pci/linux/pci.c | 4 +-\n drivers/bus/pci/linux/pci_init.h | 4 +-\n drivers/bus/pci/linux/pci_vfio.c | 176 ++++++++++++++++++++++++-------\n drivers/bus/pci/private.h | 9 ++\n 4 files changed, 153 insertions(+), 40 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c\nindex 6dbba10657..8f1fddbf20 100644\n--- a/drivers/bus/pci/linux/pci.c\n+++ b/drivers/bus/pci/linux/pci.c\n@@ -647,7 +647,7 @@ int rte_pci_read_config(const struct rte_pci_device *device,\n \t\treturn pci_uio_read_config(intr_handle, buf, len, offset);\n #ifdef VFIO_PRESENT\n \tcase RTE_PCI_KDRV_VFIO:\n-\t\treturn pci_vfio_read_config(intr_handle, buf, len, offset);\n+\t\treturn pci_vfio_read_config(device, buf, len, offset);\n #endif\n \tdefault:\n \t\trte_pci_device_name(&device->addr, devname,\n@@ -671,7 +671,7 @@ int rte_pci_write_config(const struct rte_pci_device *device,\n \t\treturn pci_uio_write_config(intr_handle, buf, len, offset);\n #ifdef VFIO_PRESENT\n \tcase RTE_PCI_KDRV_VFIO:\n-\t\treturn pci_vfio_write_config(intr_handle, buf, len, offset);\n+\t\treturn pci_vfio_write_config(device, buf, len, offset);\n #endif\n \tdefault:\n \t\trte_pci_device_name(&device->addr, devname,\ndiff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h\nindex dcea726186..9f6659ba6e 100644\n--- a/drivers/bus/pci/linux/pci_init.h\n+++ b/drivers/bus/pci/linux/pci_init.h\n@@ -66,9 +66,9 @@ int pci_uio_ioport_unmap(struct rte_pci_ioport *p);\n #endif\n \n /* access config space */\n-int pci_vfio_read_config(const struct rte_intr_handle *intr_handle,\n+int pci_vfio_read_config(const struct rte_pci_device *dev,\n \t\t\t void *buf, size_t len, off_t offs);\n-int pci_vfio_write_config(const struct rte_intr_handle *intr_handle,\n+int pci_vfio_write_config(const struct rte_pci_device *dev,\n \t\t\t const void *buf, size_t len, off_t offs);\n \n int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,\ndiff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex 07706f7338..012e7f72c1 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -43,35 +43,82 @@ static struct rte_tailq_elem rte_vfio_tailq = {\n };\n EAL_REGISTER_TAILQ(rte_vfio_tailq)\n \n+static int\n+pci_vfio_get_region(const struct rte_pci_device *dev, int index,\n+\t\t uint64_t *size, uint64_t *offset)\n+{\n+\tconst struct rte_pci_device_internal *pdev =\n+\t\tRTE_PCI_DEVICE_INTERNAL_CONST(dev);\n+\n+\tif (index >= VFIO_PCI_NUM_REGIONS || index >= RTE_MAX_PCI_REGIONS)\n+\t\treturn -1;\n+\n+\tif (pdev->region[index].size == 0 && pdev->region[index].offset == 0)\n+\t\treturn -1;\n+\n+\t*size = pdev->region[index].size;\n+\t*offset = pdev->region[index].offset;\n+\n+\treturn 0;\n+}\n+\n int\n-pci_vfio_read_config(const struct rte_intr_handle *intr_handle,\n+pci_vfio_read_config(const struct rte_pci_device *dev,\n \t\t void *buf, size_t len, off_t offs)\n {\n-\treturn pread64(intr_handle->vfio_dev_fd, buf, len,\n-\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);\n+\tuint64_t size, offset;\n+\tint fd;\n+\n+\tfd = dev->intr_handle.vfio_dev_fd;\n+\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t\t\t&size, &offset) != 0)\n+\t\treturn -1;\n+\n+\tif ((uint64_t)len + offs > size)\n+\t\treturn -1;\n+\n+\treturn pread64(fd, buf, len, offset + offs);\n }\n \n int\n-pci_vfio_write_config(const struct rte_intr_handle *intr_handle,\n+pci_vfio_write_config(const struct rte_pci_device *dev,\n \t\t const void *buf, size_t len, off_t offs)\n {\n-\treturn pwrite64(intr_handle->vfio_dev_fd, buf, len,\n-\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);\n+\tuint64_t size, offset;\n+\tint fd;\n+\n+\tfd = dev->intr_handle.vfio_dev_fd;\n+\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t\t\t&size, &offset) != 0)\n+\t\treturn -1;\n+\n+\tif ((uint64_t)len + offs > size)\n+\t\treturn -1;\n+\n+\treturn pwrite64(fd, buf, len, offset + offs);\n }\n \n /* get PCI BAR number where MSI-X interrupts are */\n static int\n-pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n+pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,\n+\t\tstruct pci_msix_table *msix_table)\n {\n \tint ret;\n \tuint32_t reg;\n \tuint16_t flags;\n \tuint8_t cap_id, cap_offset;\n+\tuint64_t size, offset;\n+\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n \n \t/* read PCI capability pointer from config space */\n-\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\tPCI_CAPABILITY_LIST);\n+\tret = pread64(fd, ®, sizeof(reg), offset + PCI_CAPABILITY_LIST);\n \tif (ret != sizeof(reg)) {\n \t\tRTE_LOG(ERR, EAL,\n \t\t\t\"Cannot read capability pointer from PCI config space!\\n\");\n@@ -84,9 +131,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \twhile (cap_offset) {\n \n \t\t/* read PCI capability ID */\n-\t\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\tcap_offset);\n+\t\tret = pread64(fd, ®, sizeof(reg), offset + cap_offset);\n \t\tif (ret != sizeof(reg)) {\n \t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\"Cannot read capability ID from PCI config space!\\n\");\n@@ -99,8 +144,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \t\t/* if we haven't reached MSI-X, check next capability */\n \t\tif (cap_id != PCI_CAP_ID_MSIX) {\n \t\t\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\t\tcap_offset);\n+\t\t\t\toffset + cap_offset);\n \t\t\tif (ret != sizeof(reg)) {\n \t\t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\t\"Cannot read capability pointer from PCI config space!\\n\");\n@@ -116,8 +160,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \t\telse {\n \t\t\t/* table offset resides in the next 4 bytes */\n \t\t\tret = pread64(fd, ®, sizeof(reg),\n-\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\t\tcap_offset + 4);\n+\t\t\t\toffset + cap_offset + 4);\n \t\t\tif (ret != sizeof(reg)) {\n \t\t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\t\"Cannot read table offset from PCI config space!\\n\");\n@@ -125,8 +168,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)\n \t\t\t}\n \n \t\t\tret = pread64(fd, &flags, sizeof(flags),\n-\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\t\t\tcap_offset + 2);\n+\t\t\t\toffset + cap_offset + 2);\n \t\t\tif (ret != sizeof(flags)) {\n \t\t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\t\"Cannot read table flags from PCI config space!\\n\");\n@@ -178,14 +220,19 @@ pci_vfio_enable_bus_memory(int dev_fd)\n \n /* set PCI bus mastering */\n static int\n-pci_vfio_set_bus_master(int dev_fd, bool op)\n+pci_vfio_set_bus_master(const struct rte_pci_device *dev, int dev_fd, bool op)\n {\n+\tuint64_t size, offset;\n \tuint16_t reg;\n \tint ret;\n \n-\tret = pread64(dev_fd, ®, sizeof(reg),\n-\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\tPCI_COMMAND);\n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tret = pread64(dev_fd, ®, sizeof(reg), offset + PCI_COMMAND);\n \tif (ret != sizeof(reg)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot read command from PCI config space!\\n\");\n \t\treturn -1;\n@@ -197,10 +244,7 @@ pci_vfio_set_bus_master(int dev_fd, bool op)\n \telse\n \t\treg &= ~(PCI_COMMAND_MASTER);\n \n-\tret = pwrite64(dev_fd, ®, sizeof(reg),\n-\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n-\t\t\tPCI_COMMAND);\n-\n+\tret = pwrite64(dev_fd, ®, sizeof(reg), offset + PCI_COMMAND);\n \tif (ret != sizeof(reg)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot write command to PCI config space!\\n\");\n \t\treturn -1;\n@@ -429,14 +473,21 @@ pci_vfio_disable_notifier(struct rte_pci_device *dev)\n #endif\n \n static int\n-pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)\n+pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd,\n+\tint bar_index)\n {\n+\tuint64_t size, offset;\n \tuint32_t ioport_bar;\n \tint ret;\n \n+\tif (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,\n+\t\t&size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of CONFIG region.\\n\");\n+\t\treturn -1;\n+\t}\n+\n \tret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),\n-\t\t\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)\n-\t\t\t + PCI_BASE_ADDRESS_0 + bar_index*4);\n+\t\t\t offset + PCI_BASE_ADDRESS_0 + bar_index * 4);\n \tif (ret != sizeof(ioport_bar)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot read command (%x) from config space!\\n\",\n \t\t\tPCI_BASE_ADDRESS_0 + bar_index*4);\n@@ -460,7 +511,7 @@ pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)\n \t}\n \n \t/* set bus mastering for the device */\n-\tif (pci_vfio_set_bus_master(vfio_dev_fd, true)) {\n+\tif (pci_vfio_set_bus_master(dev, vfio_dev_fd, true)) {\n \t\tRTE_LOG(ERR, EAL, \"Cannot set up bus mastering!\\n\");\n \t\treturn -1;\n \t}\n@@ -690,11 +741,40 @@ pci_vfio_msix_is_mappable(int vfio_dev_fd, int msix_region)\n \treturn ret;\n }\n \n+static int\n+pci_vfio_fill_regions(struct rte_pci_device *dev, int vfio_dev_fd,\n+\t\t struct vfio_device_info *device_info)\n+{\n+\tstruct rte_pci_device_internal *pdev = RTE_PCI_DEVICE_INTERNAL(dev);\n+\tstruct vfio_region_info *reg = NULL;\n+\tint nb_maps, i, ret;\n+\n+\tnb_maps = RTE_MIN((int)device_info->num_regions,\n+\t\t\tVFIO_PCI_CONFIG_REGION_INDEX + 1);\n+\n+\tfor (i = 0; i < nb_maps; i++) {\n+\t\tret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);\n+\t\tif (ret < 0) {\n+\t\t\tRTE_LOG(DEBUG, EAL, \"%s cannot get device region info error %i (%s)\\n\",\n+\t\t\t\tdev->name, errno, strerror(errno));\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tpdev->region[i].size = reg->size;\n+\t\tpdev->region[i].offset = reg->offset;\n+\n+\t\tfree(reg);\n+\t}\n+\n+\treturn 0;\n+}\n \n static int\n pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n {\n+\tstruct rte_pci_device_internal *pdev = RTE_PCI_DEVICE_INTERNAL(dev);\n \tstruct vfio_device_info device_info = { .argsz = sizeof(device_info) };\n+\tstruct vfio_region_info *reg = NULL;\n \tchar pci_addr[PATH_MAX] = {0};\n \tint vfio_dev_fd;\n \tstruct rte_pci_addr *loc = &dev->addr;\n@@ -735,11 +815,22 @@ pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n \t/* map BARs */\n \tmaps = vfio_res->maps;\n \n+\tret = pci_vfio_get_region_info(vfio_dev_fd, ®,\n+\t\tVFIO_PCI_CONFIG_REGION_INDEX);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, EAL, \"%s cannot get device region info error %i (%s)\\n\",\n+\t\t\tdev->name, errno, strerror(errno));\n+\t\tgoto err_vfio_res;\n+\t}\n+\tpdev->region[VFIO_PCI_CONFIG_REGION_INDEX].size = reg->size;\n+\tpdev->region[VFIO_PCI_CONFIG_REGION_INDEX].offset = reg->offset;\n+\tfree(reg);\n+\n \tvfio_res->msix_table.bar_index = -1;\n \t/* get MSI-X BAR, if any (we have to know where it is because we can't\n \t * easily mmap it when using VFIO)\n \t */\n-\tret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);\n+\tret = pci_vfio_get_msix_bar(dev, vfio_dev_fd, &vfio_res->msix_table);\n \tif (ret < 0) {\n \t\tRTE_LOG(ERR, EAL, \"%s cannot get MSI-X BAR number!\\n\",\n \t\t\t\tpci_addr);\n@@ -760,7 +851,6 @@ pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n \t}\n \n \tfor (i = 0; i < vfio_res->nb_maps; i++) {\n-\t\tstruct vfio_region_info *reg = NULL;\n \t\tvoid *bar_addr;\n \n \t\tret = pci_vfio_get_region_info(vfio_dev_fd, ®, i);\n@@ -771,8 +861,11 @@ pci_vfio_map_resource_primary(struct rte_pci_device *dev)\n \t\t\tgoto err_vfio_res;\n \t\t}\n \n+\t\tpdev->region[i].size = reg->size;\n+\t\tpdev->region[i].offset = reg->offset;\n+\n \t\t/* chk for io port region */\n-\t\tret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);\n+\t\tret = pci_vfio_is_ioport_bar(dev, vfio_dev_fd, i);\n \t\tif (ret < 0) {\n \t\t\tfree(reg);\n \t\t\tgoto err_vfio_res;\n@@ -882,6 +975,10 @@ pci_vfio_map_resource_secondary(struct rte_pci_device *dev)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = pci_vfio_fill_regions(dev, vfio_dev_fd, &device_info);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* map BARs */\n \tmaps = vfio_res->maps;\n \n@@ -988,7 +1085,7 @@ pci_vfio_unmap_resource_primary(struct rte_pci_device *dev)\n \t\treturn -1;\n \t}\n \n-\tif (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {\n+\tif (pci_vfio_set_bus_master(dev, dev->intr_handle.vfio_dev_fd, false)) {\n \t\tRTE_LOG(ERR, EAL, \"%s cannot unset bus mastering for PCI device!\\n\",\n \t\t\t\tpci_addr);\n \t\treturn -1;\n@@ -1064,14 +1161,21 @@ int\n pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,\n \t\t struct rte_pci_ioport *p)\n {\n+\tuint64_t size, offset;\n+\n \tif (bar < VFIO_PCI_BAR0_REGION_INDEX ||\n \t bar > VFIO_PCI_BAR5_REGION_INDEX) {\n \t\tRTE_LOG(ERR, EAL, \"invalid bar (%d)!\\n\", bar);\n \t\treturn -1;\n \t}\n \n+\tif (pci_vfio_get_region(dev, bar, &size, &offset) != 0) {\n+\t\tRTE_LOG(ERR, EAL, \"Cannot get offset of region %d.\\n\", bar);\n+\t\treturn -1;\n+\t}\n+\n \tp->dev = dev;\n-\tp->base = VFIO_GET_REGION_ADDR(bar);\n+\tp->base = offset;\n \treturn 0;\n }\n \ndiff --git a/drivers/bus/pci/private.h b/drivers/bus/pci/private.h\nindex 49a29d45cf..8b5fa70641 100644\n--- a/drivers/bus/pci/private.h\n+++ b/drivers/bus/pci/private.h\n@@ -12,6 +12,8 @@\n #include <rte_os_shim.h>\n #include <rte_pci.h>\n \n+#define RTE_MAX_PCI_REGIONS\t9\n+\n /*\n * Convert struct rte_pci_device to struct rte_pci_device_internal\n */\n@@ -25,8 +27,15 @@ extern struct rte_pci_bus rte_pci_bus;\n struct rte_pci_driver;\n struct rte_pci_device;\n \n+struct rte_pci_region {\n+\tuint64_t size;\n+\tuint64_t offset;\n+};\n+\n struct rte_pci_device_internal {\n \tstruct rte_pci_device device;\n+\t/* PCI regions provided by e.g. VFIO. */\n+\tstruct rte_pci_region region[RTE_MAX_PCI_REGIONS];\n };\n \n /**\n", "prefixes": [ "RFC", "v3", "2/6" ] }