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{
    "id": 93408,
    "url": "https://patches.dpdk.org/api/patches/93408/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210524114833.4056-2-ivan.malov@oktetlabs.ru/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210524114833.4056-2-ivan.malov@oktetlabs.ru>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210524114833.4056-2-ivan.malov@oktetlabs.ru",
    "date": "2021-05-24T11:48:31",
    "name": "[v4,1/3] common/sfc_efx/base: update MCDI headers",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "e2a7e74f8a953a636901531201c65409bcbdefd1",
    "submitter": {
        "id": 869,
        "url": "https://patches.dpdk.org/api/people/869/?format=api",
        "name": "Ivan Malov",
        "email": "Ivan.Malov@oktetlabs.ru"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210524114833.4056-2-ivan.malov@oktetlabs.ru/mbox/",
    "series": [
        {
            "id": 17102,
            "url": "https://patches.dpdk.org/api/series/17102/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17102",
            "date": "2021-05-24T11:48:30",
            "name": "Match On VLAN Presence In Transfer Flows",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/17102/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/93408/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/93408/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A3827A0547;\n\tMon, 24 May 2021 13:48:57 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 84F594111A;\n\tMon, 24 May 2021 13:48:57 +0200 (CEST)",
            "from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113])\n by mails.dpdk.org (Postfix) with ESMTP id 208994003C\n for <dev@dpdk.org>; Mon, 24 May 2021 13:48:56 +0200 (CEST)",
            "from localhost.localdomain (unknown [5.144.120.251])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by shelob.oktetlabs.ru (Postfix) with ESMTPSA id A1FA87F51A;\n Mon, 24 May 2021 14:48:55 +0300 (MSK)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru A1FA87F51A",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=simple/simple; d=oktetlabs.ru;\n s=default; t=1621856935;\n bh=f3ph+QIH3OyjMkbcVt2//z4lBWt2Gd+IodL9F5BOSzo=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References;\n b=VumvarH7icrNXqsN7f7Ur+JiIDs8TretVT+DcAJSFql072oYHwXfNLG7592JtyIga\n o07hmBPEQjv5QNyw3/82uqIaYH/iJlc+TgNhHBOgnPM73pvTqUoeLIXyMKgeTWsby0\n 9t9o8EjQfj0zhaVVxnU7+YlikJX7wdEhrp9x7MqE=",
        "From": "Ivan Malov <ivan.malov@oktetlabs.ru>",
        "To": "dev@dpdk.org",
        "Cc": "Ray Kinsella <mdr@ashroe.eu>, Ferruh Yigit <ferruh.yigit@intel.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>",
        "Date": "Mon, 24 May 2021 14:48:31 +0300",
        "Message-Id": "<20210524114833.4056-2-ivan.malov@oktetlabs.ru>",
        "X-Mailer": "git-send-email 2.20.1",
        "In-Reply-To": "<20210524114833.4056-1-ivan.malov@oktetlabs.ru>",
        "References": "<20210428094926.22185-1-ivan.malov@oktetlabs.ru>\n <20210524114833.4056-1-ivan.malov@oktetlabs.ru>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v4 1/3] common/sfc_efx/base: update MCDI headers",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>\n\nSigned-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>\nSigned-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>\n---\n drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 3532 +++++++++++++++--\n .../common/sfc_efx/base/efx_regs_mcdi_aoe.h   |  142 +-\n .../common/sfc_efx/base/efx_regs_mcdi_strs.h  |    2 +-\n 3 files changed, 3331 insertions(+), 345 deletions(-)",
    "diff": "diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h\nindex 976db37d6..a3c9f076e 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h\n@@ -6,7 +6,7 @@\n \n /*\n  * This file is automatically generated. DO NOT EDIT IT.\n- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and\n+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and\n  * rebuild this file with \"make mcdi_headers_v5\".\n  */\n \n@@ -410,6 +410,48 @@\n #define\tMC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff\n #define\tMC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */\n \n+/* MC_CMD_FPGA_FLASH_INDEX enum */\n+#define\tMC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */\n+#define\tMC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */\n+\n+/* MC_CMD_EXTERNAL_MAE_LINK_MODE enum */\n+/* enum: Legacy mode as described in XN-200039-TC. */\n+#define\tMC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0\n+/* enum: Switchdev mode as described in XN-200039-TC. */\n+#define\tMC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1\n+/* enum: Bootstrap mode as described in XN-200039-TC. */\n+#define\tMC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2\n+/* enum: Link-mode change is in-progress as described in XN-200039-TC. */\n+#define\tMC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf\n+\n+/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe\n+ * interfaces. There is a need to refer to interfaces explicitly from drivers\n+ * (for example, a management driver on one interface administering a function\n+ * on another interface). This enumeration provides stable identifiers to all\n+ * interfaces present on a product. Product documentation will specify which\n+ * interfaces exist and their associated identifier. In general, drivers,\n+ * should not assign special meanings to specific values. Instead, behaviour\n+ * should be determined by NIC configuration, which will identify interfaces\n+ * where appropriate.\n+ */\n+/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)\n+ * the interface exposed on the edge connector (or form factor equivalent).\n+ */\n+#define\tPCIE_INTERFACE_HOST_PRIMARY 0x0\n+/* enum: Riverhead and keystone products have a second PCIe interface to which\n+ * an on-NIC ARM module is expected to be connected.\n+ */\n+#define\tPCIE_INTERFACE_NIC_EMBEDDED 0x1\n+/* enum: For MCDI commands issued over a PCIe interface, this value is\n+ * translated into the interface over which the command was issued. Not\n+ * meaningful for other MCDI transports.\n+ */\n+#define\tPCIE_INTERFACE_CALLER 0xffffffff\n+\n+/* MC_CLIENT_ID_SPECIFIER enum */\n+/* enum: Equivalent to the caller's client ID */\n+#define\tMC_CMD_CLIENT_ID_SELF 0xffffffff\n+\n /* MAE_FIELD_SUPPORT_STATUS enum */\n /* enum: The NIC does not support this field. The driver must ensure that any\n  * mask associated with this field in a match rule is zeroed. The NIC may\n@@ -470,6 +512,20 @@\n #define\tMAE_FIELD_CT_PRIVATE_FLAGS 0x8\n /* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */\n #define\tMAE_FIELD_IS_FROM_NETWORK 0x9\n+/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */\n+#define\tMAE_FIELD_HAS_OVLAN 0xa\n+/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */\n+#define\tMAE_FIELD_HAS_IVLAN 0xb\n+/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present\n+ * when encap\n+ */\n+#define\tMAE_FIELD_ENC_HAS_OVLAN 0xc\n+/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present\n+ * when encap\n+ */\n+#define\tMAE_FIELD_ENC_HAS_IVLAN 0xd\n+/* enum: Packet is IP fragment */\n+#define\tMAE_FIELD_ENC_IP_FRAG 0xe\n #define\tMAE_FIELD_ETHER_TYPE 0x21 /* enum */\n #define\tMAE_FIELD_VLAN0_TCI 0x22 /* enum */\n #define\tMAE_FIELD_VLAN0_PROTO 0x23 /* enum */\n@@ -508,6 +564,10 @@\n #define\tMAE_FIELD_L4_DPORT 0x33\n /* enum: Inner when encap */\n #define\tMAE_FIELD_TCP_FLAGS 0x34\n+/* enum: TCP packet with any of SYN, FIN or RST flag set */\n+#define\tMAE_FIELD_TCP_SYN_FIN_RST 0x35\n+/* enum: Packet is IP fragment with fragment offset 0 */\n+#define\tMAE_FIELD_IP_FIRST_FRAG 0x36\n /* enum: The type of encapsulated used for this packet. Value as per\n  * ENCAP_TYPE_*.\n  */\n@@ -550,8 +610,8 @@\n #define\tMAE_FIELD_ENC_L4_SPORT 0x52\n /* enum: Outer; only present when encap */\n #define\tMAE_FIELD_ENC_L4_DPORT 0x53\n-/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Outer; only present when\n- * encap\n+/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key\n+ * (when L2GRE) Outer; only present when encap\n  */\n #define\tMAE_FIELD_ENC_VNET_ID 0x54\n \n@@ -566,6 +626,14 @@\n #define\tMAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */\n #define\tMAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */\n \n+/* MAE_MPORT_END enum: Selects which end of the logical link identified by an\n+ * MPORT_SELECTOR is targeted by an operation.\n+ */\n+/* enum: Selects the port on the MAE virtual switch */\n+#define\tMAE_MPORT_END_MAE 0x1\n+/* enum: Selects the virtual NIC plugged into the MAE switch */\n+#define\tMAE_MPORT_END_VNIC 0x2\n+\n /* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100\n  * platforms\n  */\n@@ -647,17 +715,21 @@\n #define\tMCDI_EVENT_TX_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_TX_ERR_TYPE_LBN 12\n #define\tMCDI_EVENT_TX_ERR_TYPE_WIDTH 4\n-/* enum: Descriptor loader reported failure */\n+/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */\n #define\tMCDI_EVENT_TX_ERR_DL_FAIL 0x1\n-/* enum: Descriptor ring empty and no EOP seen for packet */\n+/* enum: Descriptor ring empty and no EOP seen for packet. Specific to\n+ * EF10-family NICs\n+ */\n #define\tMCDI_EVENT_TX_ERR_NO_EOP 0x2\n-/* enum: Overlength packet */\n+/* enum: Overlength packet. Specific to EF10-family NICs. */\n #define\tMCDI_EVENT_TX_ERR_2BIG 0x3\n-/* enum: Malformed option descriptor */\n+/* enum: Malformed option descriptor. Specific to EF10-family NICs. */\n #define\tMCDI_EVENT_TX_BAD_OPTDESC 0x5\n-/* enum: Option descriptor part way through a packet */\n+/* enum: Option descriptor part way through a packet. Specific to EF10-family\n+ * NICs.\n+ */\n #define\tMCDI_EVENT_TX_OPT_IN_PKT 0x8\n-/* enum: DMA or PIO data access error */\n+/* enum: DMA or PIO data access error. Specific to EF10-family NICs */\n #define\tMCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9\n #define\tMCDI_EVENT_TX_ERR_INFO_OFST 0\n #define\tMCDI_EVENT_TX_ERR_INFO_LBN 16\n@@ -1270,7 +1342,13 @@\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LBN 64\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_WIDTH 32\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LBN 96\n+#define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_WIDTH 32\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30\n #define\tFCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126\n@@ -1384,6 +1462,7 @@\n  * has additional checks to reject insecure calls.\n  */\n #define\tMC_CMD_READ32 0x1\n+#define\tMC_CMD_READ32_MSGSET 0x1\n #undef\tMC_CMD_0x1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -1413,6 +1492,7 @@\n  * Write multiple 32byte words to MC memory.\n  */\n #define\tMC_CMD_WRITE32 0x2\n+#define\tMC_CMD_WRITE32_MSGSET 0x2\n #undef\tMC_CMD_0x2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -1442,6 +1522,7 @@\n  * has additional checks to reject insecure calls.\n  */\n #define\tMC_CMD_COPYCODE 0x3\n+#define\tMC_CMD_COPYCODE_MSGSET 0x3\n #undef\tMC_CMD_0x3_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -1505,6 +1586,7 @@\n  * Select function for function-specific commands.\n  */\n #define\tMC_CMD_SET_FUNC 0x4\n+#define\tMC_CMD_SET_FUNC_MSGSET 0x4\n #undef\tMC_CMD_0x4_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -1524,6 +1606,7 @@\n  * Get the instruction address from which the MC booted.\n  */\n #define\tMC_CMD_GET_BOOT_STATUS 0x5\n+#define\tMC_CMD_GET_BOOT_STATUS_MSGSET 0x5\n #undef\tMC_CMD_0x5_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -1558,6 +1641,7 @@\n  * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS\n  */\n #define\tMC_CMD_GET_ASSERTS 0x6\n+#define\tMC_CMD_GET_ASSERTS_MSGSET 0x6\n #undef\tMC_CMD_0x6_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -1682,12 +1766,24 @@\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32\n /* MC firmware version number */\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176\n+#define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32\n /* MC firmware security level */\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276\n #define\tMC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4\n@@ -1705,6 +1801,7 @@\n  * sensor notifications and MCDI completions\n  */\n #define\tMC_CMD_LOG_CTRL 0x7\n+#define\tMC_CMD_LOG_CTRL_MSGSET 0x7\n #undef\tMC_CMD_0x7_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -1731,6 +1828,7 @@\n  * Get version information about adapter components.\n  */\n #define\tMC_CMD_GET_VERSION 0x8\n+#define\tMC_CMD_GET_VERSION_MSGSET 0x8\n #undef\tMC_CMD_0x8_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -1771,7 +1869,13 @@\n #define\tMC_CMD_GET_VERSION_OUT_VERSION_OFST 24\n #define\tMC_CMD_GET_VERSION_OUT_VERSION_LEN 8\n #define\tMC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32\n #define\tMC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224\n+#define\tMC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32\n \n /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */\n #define\tMC_CMD_GET_VERSION_EXT_OUT_LEN 48\n@@ -1787,7 +1891,13 @@\n #define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24\n #define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8\n #define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32\n #define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224\n+#define\tMC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32\n /* extra info */\n #define\tMC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32\n #define\tMC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16\n@@ -1811,7 +1921,13 @@\n #define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24\n #define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8\n #define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192\n+#define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32\n #define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28\n+#define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224\n+#define\tMC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32\n /* extra info */\n #define\tMC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32\n #define\tMC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16\n@@ -1833,6 +1949,33 @@\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5\n+#define\tMC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6\n+#define\tMC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1\n /* MC firmware unique build ID (as binary SHA-1 value) */\n #define\tMC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52\n #define\tMC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20\n@@ -1850,7 +1993,13 @@\n #define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156\n #define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8\n #define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32\n #define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32\n /* The ID of the SUC chip. This is specific to the platform but typically\n  * indicates family, memory sizes etc. See SF-116728-SW for further details.\n  */\n@@ -1864,7 +2013,13 @@\n #define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184\n #define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8\n #define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32\n #define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32\n /* FPGA version as three numbers. On Riverhead based systems this field uses\n  * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):\n  * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1\n@@ -1886,12 +2041,496 @@\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64\n \n+/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version\n+ * information for all adapter components. For Riverhead based designs, base MC\n+ * firmware version fields refer to NMC firmware, while CMC firmware data is in\n+ * dedicated CMC fields. Flags indicate which data is present in the response\n+ * (depending on which components exist on a particular adapter)\n+ */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_LEN 328\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4\n+/* 128bit mask of functions supported by the current firmware */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224\n+#define\tMC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32\n+/* extra info */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32\n+#define\tMC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16\n+/* Flags indicating which extended fields are valid */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1\n+/* MC firmware unique build ID (as binary SHA-1 value) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20\n+/* MC firmware security level */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4\n+/* MC firmware build name (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76\n+#define\tMC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64\n+/* The SUC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4\n+/* SUC firmware build date (as 64-bit Unix timestamp) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32\n+/* The ID of the SUC chip. This is specific to the platform but typically\n+ * indicates family, memory sizes etc. See SF-116728-SW for further details.\n+ */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164\n+#define\tMC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4\n+/* The CMC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4\n+/* CMC firmware build date (as 64-bit Unix timestamp) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504\n+#define\tMC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32\n+/* FPGA version as three numbers. On Riverhead based systems this field uses\n+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):\n+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1\n+ * => B, ...) FPGA_VERSION[2]: Sub-revision number\n+ */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3\n+/* Extra FPGA revision information (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204\n+#define\tMC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16\n+/* Board name / adapter model (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16\n+/* Board revision number */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4\n+/* Board serial number (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240\n+#define\tMC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64\n+/* The version of the datapath hardware design as three number - a.b.c */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3\n+/* The version of the firmware library used to control the datapath as three\n+ * number - a.b.c\n+ */\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3\n+\n+/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC\n+ * version information\n+ */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_LEN 392\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4\n+/* 128bit mask of functions supported by the current firmware */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224\n+#define\tMC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32\n+/* extra info */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32\n+#define\tMC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16\n+/* Flags indicating which extended fields are valid */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1\n+/* MC firmware unique build ID (as binary SHA-1 value) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20\n+/* MC firmware security level */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4\n+/* MC firmware build name (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76\n+#define\tMC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64\n+/* The SUC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4\n+/* SUC firmware build date (as 64-bit Unix timestamp) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32\n+/* The ID of the SUC chip. This is specific to the platform but typically\n+ * indicates family, memory sizes etc. See SF-116728-SW for further details.\n+ */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4\n+/* The CMC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4\n+/* CMC firmware build date (as 64-bit Unix timestamp) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504\n+#define\tMC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32\n+/* FPGA version as three numbers. On Riverhead based systems this field uses\n+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):\n+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1\n+ * => B, ...) FPGA_VERSION[2]: Sub-revision number\n+ */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3\n+/* Extra FPGA revision information (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204\n+#define\tMC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16\n+/* Board name / adapter model (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16\n+/* Board revision number */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4\n+/* Board serial number (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240\n+#define\tMC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64\n+/* The version of the datapath hardware design as three number - a.b.c */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3\n+/* The version of the firmware library used to control the datapath as three\n+ * number - a.b.c\n+ */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3\n+/* The SOC boot version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4\n+/* The SOC uboot version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4\n+/* The SOC main rootfs version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4\n+/* The SOC recovery buildroot version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4\n+\n+/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle\n+ * and board version information\n+ */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_LEN 424\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */\n+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4\n+/* 128bit mask of functions supported by the current firmware */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224\n+#define\tMC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32\n+/* extra info */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32\n+#define\tMC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16\n+/* Flags indicating which extended fields are valid */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1\n+/* MC firmware unique build ID (as binary SHA-1 value) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20\n+/* MC firmware security level */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4\n+/* MC firmware build name (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76\n+#define\tMC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64\n+/* The SUC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4\n+/* SUC firmware build date (as 64-bit Unix timestamp) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32\n+/* The ID of the SUC chip. This is specific to the platform but typically\n+ * indicates family, memory sizes etc. See SF-116728-SW for further details.\n+ */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4\n+/* The CMC firmware version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4\n+/* CMC firmware build date (as 64-bit Unix timestamp) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504\n+#define\tMC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32\n+/* FPGA version as three numbers. On Riverhead based systems this field uses\n+ * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):\n+ * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1\n+ * => B, ...) FPGA_VERSION[2]: Sub-revision number\n+ */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3\n+/* Extra FPGA revision information (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204\n+#define\tMC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16\n+/* Board name / adapter model (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16\n+/* Board revision number */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4\n+/* Board serial number (as null-terminated US-ASCII string) */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64\n+/* The version of the datapath hardware design as three number - a.b.c */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3\n+/* The version of the firmware library used to control the datapath as three\n+ * number - a.b.c\n+ */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3\n+/* The SOC boot version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4\n+/* The SOC uboot version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4\n+/* The SOC main rootfs version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4\n+/* The SOC recovery buildroot version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4\n+/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the\n+ * BOARD_REVISION field\n+ */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4\n+/* Bundle version as four numbers - a.b.c.d */\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4\n+#define\tMC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4\n+\n \n /***********************************/\n /* MC_CMD_PTP\n  * Perform PTP operation\n  */\n #define\tMC_CMD_PTP 0xb\n+#define\tMC_CMD_PTP_MSGSET 0xb\n #undef\tMC_CMD_0xb_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -2066,7 +2705,13 @@\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_OFST 8\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_LEN 8\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32\n #define\tMC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96\n+#define\tMC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32\n /* enum: Number of fractional bits in frequency adjustment */\n #define\tMC_CMD_PTP_IN_ADJUST_BITS 0x28\n /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ\n@@ -2097,7 +2742,13 @@\n #define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8\n #define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8\n #define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32\n #define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96\n+#define\tMC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32\n /* enum: Number of fractional bits in frequency adjustment */\n /*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */\n /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ\n@@ -2136,7 +2787,13 @@\n #define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12\n #define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8\n #define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128\n+#define\tMC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32\n \n /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */\n #define\tMC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8\n@@ -2252,7 +2909,13 @@\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32\n #define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96\n+#define\tMC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */\n \n@@ -2283,7 +2946,13 @@\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32\n #define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128\n+#define\tMC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32\n \n /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */\n #define\tMC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16\n@@ -2745,6 +3414,7 @@\n  * Read 32bit words from the indirect memory map.\n  */\n #define\tMC_CMD_CSR_READ32 0xc\n+#define\tMC_CMD_CSR_READ32_MSGSET 0xc\n #undef\tMC_CMD_0xc_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -2778,6 +3448,7 @@\n  * Write 32bit dwords to the indirect memory map.\n  */\n #define\tMC_CMD_CSR_WRITE32 0xd\n+#define\tMC_CMD_CSR_WRITE32_MSGSET 0xd\n #undef\tMC_CMD_0xd_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -2811,6 +3482,7 @@\n  * MCDI command to avoid creating too many MCDI commands.\n  */\n #define\tMC_CMD_HP 0x54\n+#define\tMC_CMD_HP_MSGSET 0x54\n #undef\tMC_CMD_0x54_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -2834,7 +3506,13 @@\n #define\tMC_CMD_HP_IN_OCSD_ADDR_OFST 4\n #define\tMC_CMD_HP_IN_OCSD_ADDR_LEN 8\n #define\tMC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_LO_LBN 32\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_LO_WIDTH 32\n #define\tMC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_HI_LBN 64\n+#define\tMC_CMD_HP_IN_OCSD_ADDR_HI_WIDTH 32\n /* The requested update interval, in seconds. (Or the sub-command if ADDR is\n  * NULL.)\n  */\n@@ -2858,6 +3536,7 @@\n  * Get stack information.\n  */\n #define\tMC_CMD_STACKINFO 0xf\n+#define\tMC_CMD_STACKINFO_MSGSET 0xf\n #undef\tMC_CMD_0xf_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -2884,6 +3563,7 @@\n  * MDIO register read.\n  */\n #define\tMC_CMD_MDIO_READ 0x10\n+#define\tMC_CMD_MDIO_READ_MSGSET 0x10\n #undef\tMC_CMD_0x10_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -2932,6 +3612,7 @@\n  * MDIO register write.\n  */\n #define\tMC_CMD_MDIO_WRITE 0x11\n+#define\tMC_CMD_MDIO_WRITE_MSGSET 0x11\n #undef\tMC_CMD_0x11_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -2980,6 +3661,7 @@\n  * Write DBI register(s).\n  */\n #define\tMC_CMD_DBI_WRITE 0x12\n+#define\tMC_CMD_DBI_WRITE_MSGSET 0x12\n #undef\tMC_CMD_0x12_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -3033,6 +3715,7 @@\n  * access is implied by the Shared memory channel used.\n  */\n #define\tMC_CMD_PORT_READ32 0x14\n+#define\tMC_CMD_PORT_READ32_MSGSET 0x14\n \n /* MC_CMD_PORT_READ32_IN msgrequest */\n #define\tMC_CMD_PORT_READ32_IN_LEN 4\n@@ -3056,6 +3739,7 @@\n  * access is implied by the Shared memory channel used.\n  */\n #define\tMC_CMD_PORT_WRITE32 0x15\n+#define\tMC_CMD_PORT_WRITE32_MSGSET 0x15\n \n /* MC_CMD_PORT_WRITE32_IN msgrequest */\n #define\tMC_CMD_PORT_WRITE32_IN_LEN 8\n@@ -3079,6 +3763,7 @@\n  * access is implied by the Shared memory channel used.\n  */\n #define\tMC_CMD_PORT_READ128 0x16\n+#define\tMC_CMD_PORT_READ128_MSGSET 0x16\n \n /* MC_CMD_PORT_READ128_IN msgrequest */\n #define\tMC_CMD_PORT_READ128_IN_LEN 4\n@@ -3102,6 +3787,7 @@\n  * access is implied by the Shared memory channel used.\n  */\n #define\tMC_CMD_PORT_WRITE128 0x17\n+#define\tMC_CMD_PORT_WRITE128_MSGSET 0x17\n \n /* MC_CMD_PORT_WRITE128_IN msgrequest */\n #define\tMC_CMD_PORT_WRITE128_IN_LEN 20\n@@ -3150,6 +3836,7 @@\n  * Returns the MC firmware configuration structure.\n  */\n #define\tMC_CMD_GET_BOARD_CFG 0x18\n+#define\tMC_CMD_GET_BOARD_CFG_MSGSET 0x18\n #undef\tMC_CMD_0x18_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -3225,6 +3912,7 @@\n  * Read DBI register(s) -- extended functionality\n  */\n #define\tMC_CMD_DBI_READX 0x19\n+#define\tMC_CMD_DBI_READX_MSGSET 0x19\n #undef\tMC_CMD_0x19_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -3239,7 +3927,13 @@\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_OFST 0\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_LEN 8\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_LO_WIDTH 32\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_HI_LBN 32\n+#define\tMC_CMD_DBI_READX_IN_DBIRDOP_HI_WIDTH 32\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31\n #define\tMC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127\n@@ -3283,6 +3977,7 @@\n  * Set the 16byte seed for the MC pseudo-random generator.\n  */\n #define\tMC_CMD_SET_RAND_SEED 0x1a\n+#define\tMC_CMD_SET_RAND_SEED_MSGSET 0x1a\n #undef\tMC_CMD_0x1a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -3302,6 +3997,7 @@\n  * Retrieve the history of the LTSSM, if the build supports it.\n  */\n #define\tMC_CMD_LTSSM_HIST 0x1b\n+#define\tMC_CMD_LTSSM_HIST_MSGSET 0x1b\n \n /* MC_CMD_LTSSM_HIST_IN msgrequest */\n #define\tMC_CMD_LTSSM_HIST_IN_LEN 0\n@@ -3330,6 +4026,7 @@\n  * platforms.\n  */\n #define\tMC_CMD_DRV_ATTACH 0x1c\n+#define\tMC_CMD_DRV_ATTACH_MSGSET 0x1c\n #undef\tMC_CMD_0x1c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -3524,6 +4221,7 @@\n  * Route UART output to circular buffer in shared memory instead.\n  */\n #define\tMC_CMD_SHMUART 0x1f\n+#define\tMC_CMD_SHMUART_MSGSET 0x1f\n \n /* MC_CMD_SHMUART_IN msgrequest */\n #define\tMC_CMD_SHMUART_IN_LEN 4\n@@ -3542,6 +4240,7 @@\n  * use MC_CMD_ENTITY_RESET instead.\n  */\n #define\tMC_CMD_PORT_RESET 0x20\n+#define\tMC_CMD_PORT_RESET_MSGSET 0x20\n #undef\tMC_CMD_0x20_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -3560,6 +4259,7 @@\n  * extended version of the deprecated MC_CMD_PORT_RESET with added fields.\n  */\n #define\tMC_CMD_ENTITY_RESET 0x20\n+#define\tMC_CMD_ENTITY_RESET_MSGSET 0x20\n /*      MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */\n \n /* MC_CMD_ENTITY_RESET_IN msgrequest */\n@@ -3582,6 +4282,7 @@\n  * Read instantaneous and minimum flow control thresholds.\n  */\n #define\tMC_CMD_PCIE_CREDITS 0x21\n+#define\tMC_CMD_PCIE_CREDITS_MSGSET 0x21\n \n /* MC_CMD_PCIE_CREDITS_IN msgrequest */\n #define\tMC_CMD_PCIE_CREDITS_IN_LEN 8\n@@ -3617,6 +4318,7 @@\n  * Get histogram of RX queue fill level.\n  */\n #define\tMC_CMD_RXD_MONITOR 0x22\n+#define\tMC_CMD_RXD_MONITOR_MSGSET 0x22\n \n /* MC_CMD_RXD_MONITOR_IN msgrequest */\n #define\tMC_CMD_RXD_MONITOR_IN_LEN 12\n@@ -3676,6 +4378,7 @@\n  * Copy the given ASCII string out onto UART and/or out of the network port.\n  */\n #define\tMC_CMD_PUTS 0x23\n+#define\tMC_CMD_PUTS_MSGSET 0x23\n #undef\tMC_CMD_0x23_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -3712,6 +4415,7 @@\n  * 'zombie' state. Locks required: None\n  */\n #define\tMC_CMD_GET_PHY_CFG 0x24\n+#define\tMC_CMD_GET_PHY_CFG_MSGSET 0x24\n #undef\tMC_CMD_0x24_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -3868,6 +4572,7 @@\n  * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)\n  */\n #define\tMC_CMD_START_BIST 0x25\n+#define\tMC_CMD_START_BIST_MSGSET 0x25\n #undef\tMC_CMD_0x25_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -3908,6 +4613,7 @@\n  * EACCES (if PHY_LOCK is not held).\n  */\n #define\tMC_CMD_POLL_BIST 0x26\n+#define\tMC_CMD_POLL_BIST_MSGSET 0x26\n #undef\tMC_CMD_0x26_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -4077,6 +4783,7 @@\n  * returns). The driver must still wait for flush done/failure events as usual.\n  */\n #define\tMC_CMD_FLUSH_RX_QUEUES 0x27\n+#define\tMC_CMD_FLUSH_RX_QUEUES_MSGSET 0x27\n \n /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */\n #define\tMC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4\n@@ -4099,6 +4806,7 @@\n  * Returns a bitmask of loopback modes available at each speed.\n  */\n #define\tMC_CMD_GET_LOOPBACK_MODES 0x28\n+#define\tMC_CMD_GET_LOOPBACK_MODES_MSGSET 0x28\n #undef\tMC_CMD_0x28_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -4112,7 +4820,13 @@\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32\n /* enum: None. */\n #define\tMC_CMD_LOOPBACK_NONE 0x0\n /* enum: Data. */\n@@ -4195,28 +4909,52 @@\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n \n@@ -4228,7 +4966,13 @@\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32\n /* enum: None. */\n /*               MC_CMD_LOOPBACK_NONE 0x0 */\n /* enum: Data. */\n@@ -4311,49 +5055,91 @@\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported 25G loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported 50 loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n /* Supported 100G loopbacks. */\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32\n #define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480\n+#define\tMC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               100M */\n \n@@ -4395,6 +5181,7 @@\n  * ETIME.\n  */\n #define\tMC_CMD_GET_LINK 0x29\n+#define\tMC_CMD_GET_LINK_MSGSET 0x29\n #undef\tMC_CMD_0x29_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -4596,6 +5383,7 @@\n  * code: 0, EINVAL, ETIME, EAGAIN\n  */\n #define\tMC_CMD_SET_LINK 0x2a\n+#define\tMC_CMD_SET_LINK_MSGSET 0x2a\n #undef\tMC_CMD_0x2a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -4686,6 +5474,7 @@\n  * Set identification LED state. Locks required: None. Return code: 0, EINVAL\n  */\n #define\tMC_CMD_SET_ID_LED 0x2b\n+#define\tMC_CMD_SET_ID_LED_MSGSET 0x2b\n #undef\tMC_CMD_0x2b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -4708,6 +5497,7 @@\n  * Set MAC configuration. Locks required: None. Return code: 0, EINVAL\n  */\n #define\tMC_CMD_SET_MAC 0x2c\n+#define\tMC_CMD_SET_MAC_MSGSET 0x2c\n #undef\tMC_CMD_0x2c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -4724,7 +5514,13 @@\n #define\tMC_CMD_SET_MAC_IN_ADDR_OFST 8\n #define\tMC_CMD_SET_MAC_IN_ADDR_LEN 8\n #define\tMC_CMD_SET_MAC_IN_ADDR_LO_OFST 8\n+#define\tMC_CMD_SET_MAC_IN_ADDR_LO_LEN 4\n+#define\tMC_CMD_SET_MAC_IN_ADDR_LO_LBN 64\n+#define\tMC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32\n #define\tMC_CMD_SET_MAC_IN_ADDR_HI_OFST 12\n+#define\tMC_CMD_SET_MAC_IN_ADDR_HI_LEN 4\n+#define\tMC_CMD_SET_MAC_IN_ADDR_HI_LBN 96\n+#define\tMC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32\n #define\tMC_CMD_SET_MAC_IN_REJECT_OFST 16\n #define\tMC_CMD_SET_MAC_IN_REJECT_LEN 4\n #define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16\n@@ -4765,7 +5561,13 @@\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96\n+#define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16\n@@ -4816,6 +5618,129 @@\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1\n \n+/* MC_CMD_SET_MAC_V3_IN msgrequest */\n+#define\tMC_CMD_SET_MAC_V3_IN_LEN 40\n+/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of\n+ * EtherII, VLAN, bug16011 padding).\n+ */\n+#define\tMC_CMD_SET_MAC_V3_IN_MTU_OFST 0\n+#define\tMC_CMD_SET_MAC_V3_IN_MTU_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4\n+#define\tMC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_OFST 8\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_LEN 8\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96\n+#define\tMC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_OFST 16\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1\n+#define\tMC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20\n+#define\tMC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4\n+/* enum: Flow control is off. */\n+/*               MC_CMD_FCNTL_OFF 0x0 */\n+/* enum: Respond to flow control. */\n+/*               MC_CMD_FCNTL_RESPOND 0x1 */\n+/* enum: Respond to and Issue flow control. */\n+/*               MC_CMD_FCNTL_BIDIR 0x2 */\n+/* enum: Auto neg flow control. */\n+/*               MC_CMD_FCNTL_AUTO 0x3 */\n+/* enum: Priority flow control (eftest builds only). */\n+/*               MC_CMD_FCNTL_QBB 0x4 */\n+/* enum: Issue flow control. */\n+/*               MC_CMD_FCNTL_GENERATE 0x5 */\n+#define\tMC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24\n+#define\tMC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24\n+#define\tMC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0\n+#define\tMC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1\n+/* Select which parameters to configure. A parameter will only be modified if\n+ * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in\n+ * capabilities then this field is ignored (and all flags are assumed to be\n+ * set).\n+ */\n+#define\tMC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28\n+#define\tMC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1\n+/* Identifies the MAC to update by the specifying the end of a logical MAE\n+ * link. Setting TARGET to MAE_LINK_ENDPOINT_COMPAT is equivalent to using the\n+ * previous version of the command (MC_CMD_SET_MAC_EXT). Not all possible\n+ * combinations of MPORT_END and MPORT_SELECTOR in TARGET will work in all\n+ * circumstances. 1. Some will always work (e.g. a VF can always address its\n+ * logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC), 2. Some are not\n+ * meaningful and will always fail with EINVAL (e.g. attempting to address the\n+ * VNIC end of a link to a physical port), 3. Some are meaningful but require\n+ * the MCDI client to have the required permission and fail with EPERM\n+ * otherwise (e.g. trying to set the MAC on a VF the caller cannot administer),\n+ * and 4. Some could be implementation-specific and fail with ENOTSUP if not\n+ * available (no examples exist right now). See SF-123581-TC section 4.3 for\n+ * more details.\n+ */\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LEN 8\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288\n+#define\tMC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32\n+\n /* MC_CMD_SET_MAC_OUT msgresponse */\n #define\tMC_CMD_SET_MAC_OUT_LEN 0\n \n@@ -4839,6 +5764,7 @@\n  * Returns: 0, ETIME\n  */\n #define\tMC_CMD_PHY_STATS 0x2d\n+#define\tMC_CMD_PHY_STATS_MSGSET 0x2d\n #undef\tMC_CMD_0x2d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -4849,7 +5775,13 @@\n #define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0\n #define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32\n+#define\tMC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32\n \n /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */\n #define\tMC_CMD_PHY_STATS_OUT_DMA_LEN 0\n@@ -4921,6 +5853,7 @@\n  * effect. Returns: 0, ETIME\n  */\n #define\tMC_CMD_MAC_STATS 0x2e\n+#define\tMC_CMD_MAC_STATS_MSGSET 0x2e\n #undef\tMC_CMD_0x2e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -4931,7 +5864,13 @@\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32\n+#define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_MAC_STATS_IN_CMD_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_CMD_LEN 4\n #define\tMC_CMD_MAC_STATS_IN_DMA_OFST 8\n@@ -4974,7 +5913,13 @@\n #define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0\n #define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8\n #define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS\n #define\tMC_CMD_MAC_GENERATION_START 0x0 /* enum */\n #define\tMC_CMD_MAC_DMABUF_START 0x1 /* enum */\n@@ -5130,7 +6075,13 @@\n #define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0\n #define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8\n #define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2\n /* enum: Start of FEC stats buffer space, Medford2 and up */\n #define\tMC_CMD_MAC_FEC_DMABUF_START 0x61\n@@ -5163,7 +6114,13 @@\n #define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0\n #define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8\n #define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3\n /* enum: Start of CTPIO stats buffer space, Medford2 and up */\n #define\tMC_CMD_MAC_CTPIO_DMABUF_START 0x68\n@@ -5237,7 +6194,13 @@\n #define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0\n #define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8\n #define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4\n /* enum: Start of V4 stats buffer space */\n #define\tMC_CMD_MAC_V4_DMABUF_START 0x79\n@@ -5266,6 +6229,7 @@\n  * to be documented\n  */\n #define\tMC_CMD_SRIOV 0x30\n+#define\tMC_CMD_SRIOV_MSGSET 0x30\n \n /* MC_CMD_SRIOV_IN msgrequest */\n #define\tMC_CMD_SRIOV_IN_LEN 12\n@@ -5297,7 +6261,13 @@\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LBN 64\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_WIDTH 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LBN 96\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_WIDTH 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16\n@@ -5308,7 +6278,13 @@\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LBN 160\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_WIDTH 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LBN 192\n+#define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_WIDTH 32\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64\n #define\tMC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28\n@@ -5338,6 +6314,7 @@\n  * Returns: 0, EINVAL (invalid RID)\n  */\n #define\tMC_CMD_MEMCPY 0x31\n+#define\tMC_CMD_MEMCPY_MSGSET 0x31\n \n /* MC_CMD_MEMCPY_IN msgrequest */\n #define\tMC_CMD_MEMCPY_IN_LENMIN 32\n@@ -5361,6 +6338,7 @@\n  * Set a WoL filter.\n  */\n #define\tMC_CMD_WOL_FILTER_SET 0x32\n+#define\tMC_CMD_WOL_FILTER_SET_MSGSET 0x32\n #undef\tMC_CMD_0x32_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -5401,7 +6379,13 @@\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32\n #define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96\n+#define\tMC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32\n \n /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */\n #define\tMC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20\n@@ -5476,6 +6460,7 @@\n  * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS\n  */\n #define\tMC_CMD_WOL_FILTER_REMOVE 0x33\n+#define\tMC_CMD_WOL_FILTER_REMOVE_MSGSET 0x33\n #undef\tMC_CMD_0x33_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -5495,6 +6480,7 @@\n  * ENOSYS\n  */\n #define\tMC_CMD_WOL_FILTER_RESET 0x34\n+#define\tMC_CMD_WOL_FILTER_RESET_MSGSET 0x34\n #undef\tMC_CMD_0x34_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -5515,6 +6501,7 @@\n  * Set the MCAST hash value without otherwise reconfiguring the MAC\n  */\n #define\tMC_CMD_SET_MCAST_HASH 0x35\n+#define\tMC_CMD_SET_MCAST_HASH_MSGSET 0x35\n \n /* MC_CMD_SET_MCAST_HASH_IN msgrequest */\n #define\tMC_CMD_SET_MCAST_HASH_IN_LEN 32\n@@ -5533,6 +6520,7 @@\n  * Locks required: none. Returns: 0\n  */\n #define\tMC_CMD_NVRAM_TYPES 0x36\n+#define\tMC_CMD_NVRAM_TYPES_MSGSET 0x36\n #undef\tMC_CMD_0x36_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5595,6 +6583,7 @@\n  * EINVAL (bad type).\n  */\n #define\tMC_CMD_NVRAM_INFO 0x37\n+#define\tMC_CMD_NVRAM_INFO_MSGSET 0x37\n #undef\tMC_CMD_0x37_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5692,6 +6681,7 @@\n  * EPERM.\n  */\n #define\tMC_CMD_NVRAM_UPDATE_START 0x38\n+#define\tMC_CMD_NVRAM_UPDATE_START_MSGSET 0x38\n #undef\tMC_CMD_0x38_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5732,6 +6722,7 @@\n  * PHY_LOCK required and not held)\n  */\n #define\tMC_CMD_NVRAM_READ 0x39\n+#define\tMC_CMD_NVRAM_READ_MSGSET 0x39\n #undef\tMC_CMD_0x39_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5803,6 +6794,7 @@\n  * PHY_LOCK required and not held)\n  */\n #define\tMC_CMD_NVRAM_WRITE 0x3a\n+#define\tMC_CMD_NVRAM_WRITE_MSGSET 0x3a\n #undef\tMC_CMD_0x3a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5838,6 +6830,7 @@\n  * PHY_LOCK required and not held)\n  */\n #define\tMC_CMD_NVRAM_ERASE 0x3b\n+#define\tMC_CMD_NVRAM_ERASE_MSGSET 0x3b\n #undef\tMC_CMD_0x3b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5868,6 +6861,7 @@\n  * the error EPERM.\n  */\n #define\tMC_CMD_NVRAM_UPDATE_FINISH 0x3c\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_MSGSET 0x3c\n #undef\tMC_CMD_0x3c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -5906,6 +6900,9 @@\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1\n \n /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH\n  * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code\n@@ -6036,6 +7033,7 @@\n  * DATALEN=0\n  */\n #define\tMC_CMD_REBOOT 0x3d\n+#define\tMC_CMD_REBOOT_MSGSET 0x3d\n #undef\tMC_CMD_0x3d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -6057,6 +7055,7 @@\n  * thread address.\n  */\n #define\tMC_CMD_SCHEDINFO 0x3e\n+#define\tMC_CMD_SCHEDINFO_MSGSET 0x3e\n #undef\tMC_CMD_0x3e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -6083,6 +7082,7 @@\n  * mode to the specified value. Returns the old mode.\n  */\n #define\tMC_CMD_REBOOT_MODE 0x3f\n+#define\tMC_CMD_REBOOT_MODE_MSGSET 0x3f\n #undef\tMC_CMD_0x3f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -6141,6 +7141,7 @@\n  * Locks required: None Returns: 0\n  */\n #define\tMC_CMD_SENSOR_INFO 0x41\n+#define\tMC_CMD_SENSOR_INFO_MSGSET 0x41\n #undef\tMC_CMD_0x41_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -6380,7 +7381,13 @@\n #define\tMC_CMD_SENSOR_ENTRY_OFST 4\n #define\tMC_CMD_SENSOR_ENTRY_LEN 8\n #define\tMC_CMD_SENSOR_ENTRY_LO_OFST 4\n+#define\tMC_CMD_SENSOR_ENTRY_LO_LEN 4\n+#define\tMC_CMD_SENSOR_ENTRY_LO_LBN 32\n+#define\tMC_CMD_SENSOR_ENTRY_LO_WIDTH 32\n #define\tMC_CMD_SENSOR_ENTRY_HI_OFST 8\n+#define\tMC_CMD_SENSOR_ENTRY_HI_LEN 4\n+#define\tMC_CMD_SENSOR_ENTRY_HI_LBN 64\n+#define\tMC_CMD_SENSOR_ENTRY_HI_WIDTH 32\n #define\tMC_CMD_SENSOR_ENTRY_MINNUM 0\n #define\tMC_CMD_SENSOR_ENTRY_MAXNUM 31\n #define\tMC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127\n@@ -6402,7 +7409,13 @@\n /*            MC_CMD_SENSOR_ENTRY_OFST 4 */\n /*            MC_CMD_SENSOR_ENTRY_LEN 8 */\n /*            MC_CMD_SENSOR_ENTRY_LO_OFST 4 */\n+/*            MC_CMD_SENSOR_ENTRY_LO_LEN 4 */\n+/*            MC_CMD_SENSOR_ENTRY_LO_LBN 32 */\n+/*            MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */\n /*            MC_CMD_SENSOR_ENTRY_HI_OFST 8 */\n+/*            MC_CMD_SENSOR_ENTRY_HI_LEN 4 */\n+/*            MC_CMD_SENSOR_ENTRY_HI_LBN 64 */\n+/*            MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */\n /*            MC_CMD_SENSOR_ENTRY_MINNUM 0 */\n /*            MC_CMD_SENSOR_ENTRY_MAXNUM 31 */\n /*            MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */\n@@ -6445,6 +7458,7 @@\n  * STATE_WARNING. Otherwise the board should not be expected to function.\n  */\n #define\tMC_CMD_READ_SENSORS 0x42\n+#define\tMC_CMD_READ_SENSORS_MSGSET 0x42\n #undef\tMC_CMD_0x42_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -6459,7 +7473,13 @@\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32\n+#define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32\n \n /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_LEN 12\n@@ -6471,7 +7491,13 @@\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32\n /* Size in bytes of host buffer. */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8\n #define\tMC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4\n@@ -6486,7 +7512,13 @@\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32\n /* Size in bytes of host buffer. */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4\n@@ -6540,6 +7572,7 @@\n  * code: 0\n  */\n #define\tMC_CMD_GET_PHY_STATE 0x43\n+#define\tMC_CMD_GET_PHY_STATE_MSGSET 0x43\n #undef\tMC_CMD_0x43_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -6563,6 +7596,7 @@\n  * disable 802.Qbb for a given priority.\n  */\n #define\tMC_CMD_SETUP_8021QBB 0x44\n+#define\tMC_CMD_SETUP_8021QBB_MSGSET 0x44\n \n /* MC_CMD_SETUP_8021QBB_IN msgrequest */\n #define\tMC_CMD_SETUP_8021QBB_IN_LEN 32\n@@ -6578,6 +7612,7 @@\n  * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS\n  */\n #define\tMC_CMD_WOL_FILTER_GET 0x45\n+#define\tMC_CMD_WOL_FILTER_GET_MSGSET 0x45\n #undef\tMC_CMD_0x45_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -6597,6 +7632,7 @@\n  * Returns: 0, ENOSYS\n  */\n #define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46\n+#define\tMC_CMD_ADD_LIGHTSOUT_OFFLOAD_MSGSET 0x46\n #undef\tMC_CMD_0x46_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -6649,6 +7685,7 @@\n  * None. Returns: 0, ENOSYS\n  */\n #define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47\n+#define\tMC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_MSGSET 0x47\n #undef\tMC_CMD_0x47_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK\n@@ -6669,6 +7706,7 @@\n  * Restore MAC after block reset. Locks required: None. Returns: 0.\n  */\n #define\tMC_CMD_MAC_RESET_RESTORE 0x48\n+#define\tMC_CMD_MAC_RESET_RESTORE_MSGSET 0x48\n \n /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */\n #define\tMC_CMD_MAC_RESET_RESTORE_IN_LEN 0\n@@ -6684,6 +7722,7 @@\n  * required: None Returns: 0\n  */\n #define\tMC_CMD_TESTASSERT 0x49\n+#define\tMC_CMD_TESTASSERT_MSGSET 0x49\n #undef\tMC_CMD_0x49_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -6727,6 +7766,7 @@\n  * basis. Locks required: None. Returns: 0, EINVAL .\n  */\n #define\tMC_CMD_WORKAROUND 0x4a\n+#define\tMC_CMD_WORKAROUND_MSGSET 0x4a\n #undef\tMC_CMD_0x4a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -6790,6 +7830,7 @@\n  * Anything else: currently undefined. Locks required: None. Return code: 0.\n  */\n #define\tMC_CMD_GET_PHY_MEDIA_INFO 0x4b\n+#define\tMC_CMD_GET_PHY_MEDIA_INFO_MSGSET 0x4b\n #undef\tMC_CMD_0x4b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -6821,6 +7862,7 @@\n  * on the type of partition).\n  */\n #define\tMC_CMD_NVRAM_TEST 0x4c\n+#define\tMC_CMD_NVRAM_TEST_MSGSET 0x4c\n #undef\tMC_CMD_0x4c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -6851,6 +7893,7 @@\n  * they are configured first. Locks required: None. Return code: 0, EINVAL.\n  */\n #define\tMC_CMD_MRSFP_TWEAK 0x4d\n+#define\tMC_CMD_MRSFP_TWEAK_MSGSET 0x4d\n \n /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */\n #define\tMC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16\n@@ -6894,6 +7937,7 @@\n  * of range.\n  */\n #define\tMC_CMD_SENSOR_SET_LIMS 0x4e\n+#define\tMC_CMD_SENSOR_SET_LIMS_MSGSET 0x4e\n #undef\tMC_CMD_0x4e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -6925,6 +7969,7 @@\n /* MC_CMD_GET_RESOURCE_LIMITS\n  */\n #define\tMC_CMD_GET_RESOURCE_LIMITS 0x4f\n+#define\tMC_CMD_GET_RESOURCE_LIMITS_MSGSET 0x4f\n \n /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */\n #define\tMC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0\n@@ -6947,6 +7992,7 @@\n  * none. Returns: 0, EINVAL (bad type).\n  */\n #define\tMC_CMD_NVRAM_PARTITIONS 0x51\n+#define\tMC_CMD_NVRAM_PARTITIONS_MSGSET 0x51\n #undef\tMC_CMD_0x51_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -6977,6 +8023,7 @@\n  * none. Returns: 0, EINVAL (bad type).\n  */\n #define\tMC_CMD_NVRAM_METADATA 0x52\n+#define\tMC_CMD_NVRAM_METADATA_MSGSET 0x52\n #undef\tMC_CMD_0x52_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -7035,6 +8082,7 @@\n  * Returns the base MAC, count and stride for the requesting function\n  */\n #define\tMC_CMD_GET_MAC_ADDRESSES 0x55\n+#define\tMC_CMD_GET_MAC_ADDRESSES_MSGSET 0x55\n #undef\tMC_CMD_0x55_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -7066,6 +8114,7 @@\n  * SF-120509-TC and SF-117282-PS.\n  */\n #define\tMC_CMD_CLP 0x56\n+#define\tMC_CMD_CLP_MSGSET 0x56\n #undef\tMC_CMD_0x56_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -7188,6 +8237,7 @@\n  * Perform a MUM operation\n  */\n #define\tMC_CMD_MUM 0x57\n+#define\tMC_CMD_MUM_MSGSET 0x57\n #undef\tMC_CMD_0x57_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -7604,7 +8654,13 @@\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LBN 32\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_WIDTH 32\n #define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LBN 64\n+#define\tMC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_WIDTH 32\n \n /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */\n #define\tMC_CMD_MUM_OUT_RAW_CMD_LENMIN 1\n@@ -7789,7 +8845,13 @@\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LBN 64\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_WIDTH 32\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LBN 96\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_WIDTH 32\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126\n@@ -7986,6 +9048,7 @@\n  * sensor_query SPHINX service.\n  */\n #define\tMC_CMD_DYNAMIC_SENSORS_LIST 0x66\n+#define\tMC_CMD_DYNAMIC_SENSORS_LIST_MSGSET 0x66\n #undef\tMC_CMD_0x66_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -8031,6 +9094,7 @@\n  * `get_descriptions` in the sensor_query SPHINX service.\n  */\n #define\tMC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67\n+#define\tMC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_MSGSET 0x67\n #undef\tMC_CMD_0x67_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -8080,6 +9144,7 @@\n  * in the sensor_query SPHINX service.\n  */\n #define\tMC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68\n+#define\tMC_CMD_DYNAMIC_SENSORS_GET_READINGS_MSGSET 0x68\n #undef\tMC_CMD_0x68_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -8117,6 +9182,7 @@\n  * receive (Riverhead).\n  */\n #define\tMC_CMD_EVENT_CTRL 0x69\n+#define\tMC_CMD_EVENT_CTRL_MSGSET 0x69\n #undef\tMC_CMD_0x69_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -8197,7 +9263,13 @@\n #define\tBUFTBL_ENTRY_RAWADDR_OFST 4\n #define\tBUFTBL_ENTRY_RAWADDR_LEN 8\n #define\tBUFTBL_ENTRY_RAWADDR_LO_OFST 4\n+#define\tBUFTBL_ENTRY_RAWADDR_LO_LEN 4\n+#define\tBUFTBL_ENTRY_RAWADDR_LO_LBN 32\n+#define\tBUFTBL_ENTRY_RAWADDR_LO_WIDTH 32\n #define\tBUFTBL_ENTRY_RAWADDR_HI_OFST 8\n+#define\tBUFTBL_ENTRY_RAWADDR_HI_LEN 4\n+#define\tBUFTBL_ENTRY_RAWADDR_HI_LBN 64\n+#define\tBUFTBL_ENTRY_RAWADDR_HI_WIDTH 32\n #define\tBUFTBL_ENTRY_RAWADDR_LBN 32\n #define\tBUFTBL_ENTRY_RAWADDR_WIDTH 64\n \n@@ -8207,14 +9279,25 @@\n #define\tNVRAM_PARTITION_TYPE_ID_LEN 2\n /* enum: Primary MC firmware partition */\n #define\tNVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100\n+/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100\n /* enum: Secondary MC firmware partition */\n #define\tNVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200\n /* enum: Expansion ROM partition */\n #define\tNVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300\n /* enum: Static configuration TLV partition */\n #define\tNVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400\n+/* enum: Factory configuration TLV partition (this is intentionally an alias of\n+ * STATIC_CONFIG)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400\n /* enum: Dynamic configuration TLV partition */\n #define\tNVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500\n+/* enum: User configuration TLV partition (this is intentionally an alias of\n+ * DYNAMIC_CONFIG)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_USER_CONFIG 0x500\n /* enum: Expansion ROM configuration data for port 0 */\n #define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600\n /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */\n@@ -8227,10 +9310,16 @@\n #define\tNVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603\n /* enum: Non-volatile log output partition */\n #define\tNVRAM_PARTITION_TYPE_LOG 0x700\n+/* enum: Non-volatile log output partition for NMC firmware (this is\n+ * intentionally an alias of LOG)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_NMC_LOG 0x700\n /* enum: Non-volatile log output of second core on dual-core device */\n #define\tNVRAM_PARTITION_TYPE_LOG_SLAVE 0x701\n /* enum: Device state dump output partition */\n #define\tNVRAM_PARTITION_TYPE_DUMP 0x800\n+/* enum: Crash log partition for NMC firmware */\n+#define\tNVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801\n /* enum: Application license key storage partition */\n #define\tNVRAM_PARTITION_TYPE_LICENSE 0x900\n /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */\n@@ -8247,6 +9336,20 @@\n #define\tNVRAM_PARTITION_TYPE_FC_LICENSE 0xb03\n /* enum: Non-volatile log output partition for FC */\n #define\tNVRAM_PARTITION_TYPE_FC_LOG 0xb04\n+/* enum: FPGA Stage 1 bitstream */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05\n+/* enum: FPGA Stage 2 bitstream */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06\n+/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07\n+/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07\n+/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1\n+ * bitstream\n+ */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08\n+/* enum: FPGA Validate XCLBIN */\n+#define\tNVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09\n /* enum: MUM firmware partition */\n #define\tNVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00\n /* enum: SUC firmware partition (this is intentionally an alias of\n@@ -8255,6 +9358,10 @@\n #define\tNVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00\n /* enum: MUM Non-volatile log output partition. */\n #define\tNVRAM_PARTITION_TYPE_MUM_LOG 0xc01\n+/* enum: SUC Non-volatile log output partition (this is intentionally an alias\n+ * of MUM_LOG).\n+ */\n+#define\tNVRAM_PARTITION_TYPE_SUC_LOG 0xc01\n /* enum: MUM Application table partition. */\n #define\tNVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02\n /* enum: MUM boot rom partition. */\n@@ -8269,6 +9376,10 @@\n #define\tNVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00\n /* enum: Used by the expansion ROM for logging */\n #define\tNVRAM_PARTITION_TYPE_PXE_LOG 0x1000\n+/* enum: Non-volatile log output partition for Expansion ROM (this is\n+ * intentionally an alias of PXE_LOG).\n+ */\n+#define\tNVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000\n /* enum: Used for XIP code of shmbooted images */\n #define\tNVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100\n /* enum: Spare partition 2 */\n@@ -8277,6 +9388,10 @@\n  * between XJTAG and Manftest.\n  */\n #define\tNVRAM_PARTITION_TYPE_MANUFACTURING 0x1300\n+/* enum: Deployment configuration TLV partition (this is intentionally an alias\n+ * of MANUFACTURING)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300\n /* enum: Spare partition 4 */\n #define\tNVRAM_PARTITION_TYPE_SPARE_4 0x1400\n /* enum: Spare partition 5 */\n@@ -8312,14 +9427,43 @@\n #define\tNVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02\n /* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */\n #define\tNVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03\n+/* enum: Test partition on SmartNIC system microcontroller (SUC) */\n+#define\tNVRAM_PARTITION_TYPE_SUC_TEST 0x1f00\n+/* enum: System microcontroller access to primary FPGA flash. */\n+#define\tNVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01\n+/* enum: System microcontroller access to secondary FPGA flash (if present) */\n+#define\tNVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02\n+/* enum: System microcontroller access to primary System-on-Chip flash */\n+#define\tNVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03\n+/* enum: System microcontroller access to secondary System-on-Chip flash (if\n+ * present)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04\n+/* enum: System microcontroller critical failure logs. Contains structured\n+ * details of sensors leading up to a critical failure (where the board is shut\n+ * down).\n+ */\n+#define\tNVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05\n+/* enum: System-on-Chip configuration information (see XN-200467-PS). */\n+#define\tNVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07\n+/* enum: System-on-Chip update information. */\n+#define\tNVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003\n /* enum: Start of reserved value range (firmware may use for any purpose) */\n #define\tNVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00\n /* enum: End of reserved value range (firmware may use for any purpose) */\n #define\tNVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd\n /* enum: Recovery partition map (provided if real map is missing or corrupt) */\n #define\tNVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe\n+/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is\n+ * intentionally an alias of RECOVERY_MAP)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe\n /* enum: Partition map (real map as stored in flash) */\n #define\tNVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff\n+/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an\n+ * alias of PARTITION_MAP)\n+ */\n+#define\tNVRAM_PARTITION_TYPE_FPT 0xffff\n #define\tNVRAM_PARTITION_TYPE_ID_LBN 0\n #define\tNVRAM_PARTITION_TYPE_ID_WIDTH 16\n \n@@ -8368,7 +9512,13 @@\n #define\tLICENSED_FEATURES_MASK_OFST 0\n #define\tLICENSED_FEATURES_MASK_LEN 8\n #define\tLICENSED_FEATURES_MASK_LO_OFST 0\n+#define\tLICENSED_FEATURES_MASK_LO_LEN 4\n+#define\tLICENSED_FEATURES_MASK_LO_LBN 0\n+#define\tLICENSED_FEATURES_MASK_LO_WIDTH 32\n #define\tLICENSED_FEATURES_MASK_HI_OFST 4\n+#define\tLICENSED_FEATURES_MASK_HI_LEN 4\n+#define\tLICENSED_FEATURES_MASK_HI_LBN 32\n+#define\tLICENSED_FEATURES_MASK_HI_WIDTH 32\n #define\tLICENSED_FEATURES_RX_CUT_THROUGH_OFST 0\n #define\tLICENSED_FEATURES_RX_CUT_THROUGH_LBN 0\n #define\tLICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1\n@@ -8408,7 +9558,13 @@\n #define\tLICENSED_V3_APPS_MASK_OFST 0\n #define\tLICENSED_V3_APPS_MASK_LEN 8\n #define\tLICENSED_V3_APPS_MASK_LO_OFST 0\n+#define\tLICENSED_V3_APPS_MASK_LO_LEN 4\n+#define\tLICENSED_V3_APPS_MASK_LO_LBN 0\n+#define\tLICENSED_V3_APPS_MASK_LO_WIDTH 32\n #define\tLICENSED_V3_APPS_MASK_HI_OFST 4\n+#define\tLICENSED_V3_APPS_MASK_HI_LEN 4\n+#define\tLICENSED_V3_APPS_MASK_HI_LBN 32\n+#define\tLICENSED_V3_APPS_MASK_HI_WIDTH 32\n #define\tLICENSED_V3_APPS_ONLOAD_OFST 0\n #define\tLICENSED_V3_APPS_ONLOAD_LBN 0\n #define\tLICENSED_V3_APPS_ONLOAD_WIDTH 1\n@@ -8466,7 +9622,13 @@\n #define\tLICENSED_V3_FEATURES_MASK_OFST 0\n #define\tLICENSED_V3_FEATURES_MASK_LEN 8\n #define\tLICENSED_V3_FEATURES_MASK_LO_OFST 0\n+#define\tLICENSED_V3_FEATURES_MASK_LO_LEN 4\n+#define\tLICENSED_V3_FEATURES_MASK_LO_LBN 0\n+#define\tLICENSED_V3_FEATURES_MASK_LO_WIDTH 32\n #define\tLICENSED_V3_FEATURES_MASK_HI_OFST 4\n+#define\tLICENSED_V3_FEATURES_MASK_HI_LEN 4\n+#define\tLICENSED_V3_FEATURES_MASK_HI_LBN 32\n+#define\tLICENSED_V3_FEATURES_MASK_HI_WIDTH 32\n #define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0\n #define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0\n #define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1\n@@ -8617,6 +9779,7 @@\n  * Get a dump of the MCPU registers\n  */\n #define\tMC_CMD_READ_REGS 0x50\n+#define\tMC_CMD_READ_REGS_MSGSET 0x50\n #undef\tMC_CMD_0x50_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -8643,6 +9806,7 @@\n  * end with an address for each 4k of host memory required to back the EVQ.\n  */\n #define\tMC_CMD_INIT_EVQ 0x80\n+#define\tMC_CMD_INIT_EVQ_MSGSET 0x80\n #undef\tMC_CMD_0x80_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -8657,7 +9821,8 @@\n #define\tMC_CMD_INIT_EVQ_IN_SIZE_OFST 0\n #define\tMC_CMD_INIT_EVQ_IN_SIZE_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4\n #define\tMC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4\n@@ -8729,7 +9894,13 @@\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 288\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 320\n+#define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64\n #define\tMC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64\n@@ -8750,7 +9921,8 @@\n #define\tMC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0\n #define\tMC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4\n #define\tMC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4\n@@ -8847,7 +10019,13 @@\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 288\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 320\n+#define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64\n #define\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64\n@@ -8900,6 +10078,7 @@\n  * the RXQ.\n  */\n #define\tMC_CMD_INIT_RXQ 0x81\n+#define\tMC_CMD_INIT_RXQ_MSGSET 0x81\n #undef\tMC_CMD_0x81_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -8923,7 +10102,8 @@\n #define\tMC_CMD_INIT_RXQ_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_RXQ_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4\n@@ -8964,7 +10144,13 @@\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28\n #define\tMC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124\n@@ -8988,7 +10174,8 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4\n@@ -9062,7 +10249,13 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64\n /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540\n@@ -9085,7 +10278,8 @@\n #define\tMC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4\n@@ -9159,7 +10353,13 @@\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64\n /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n #define\tMC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540\n@@ -9211,7 +10411,8 @@\n #define\tMC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4\n@@ -9285,7 +10486,13 @@\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64\n /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n #define\tMC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540\n@@ -9350,7 +10557,8 @@\n #define\tMC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4\n@@ -9424,7 +10632,13 @@\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64\n /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */\n #define\tMC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540\n@@ -9497,6 +10711,7 @@\n /* MC_CMD_INIT_TXQ\n  */\n #define\tMC_CMD_INIT_TXQ 0x82\n+#define\tMC_CMD_INIT_TXQ_MSGSET 0x82\n #undef\tMC_CMD_0x82_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -9521,7 +10736,8 @@\n #define\tMC_CMD_INIT_TXQ_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_TXQ_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4\n@@ -9565,7 +10781,13 @@\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28\n #define\tMC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124\n@@ -9586,7 +10808,8 @@\n #define\tMC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8\n #define\tMC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12\n #define\tMC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4\n@@ -9648,7 +10871,13 @@\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 224\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 256\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64\n #define\tMC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64\n@@ -9674,6 +10903,7 @@\n  * or the operation will fail with EBUSY\n  */\n #define\tMC_CMD_FINI_EVQ 0x83\n+#define\tMC_CMD_FINI_EVQ_MSGSET 0x83\n #undef\tMC_CMD_0x83_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -9695,6 +10925,7 @@\n  * Teardown a RXQ.\n  */\n #define\tMC_CMD_FINI_RXQ 0x84\n+#define\tMC_CMD_FINI_RXQ_MSGSET 0x84\n #undef\tMC_CMD_0x84_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -9714,6 +10945,7 @@\n  * Teardown a TXQ.\n  */\n #define\tMC_CMD_FINI_TXQ 0x85\n+#define\tMC_CMD_FINI_TXQ_MSGSET 0x85\n #undef\tMC_CMD_0x85_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -9733,6 +10965,7 @@\n  * Generate an event on an EVQ belonging to the function issuing the command.\n  */\n #define\tMC_CMD_DRIVER_EVENT 0x86\n+#define\tMC_CMD_DRIVER_EVENT_MSGSET 0x86\n #undef\tMC_CMD_0x86_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -9746,7 +10979,13 @@\n #define\tMC_CMD_DRIVER_EVENT_IN_DATA_OFST 4\n #define\tMC_CMD_DRIVER_EVENT_IN_DATA_LEN 8\n #define\tMC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 32\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 32\n #define\tMC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 64\n+#define\tMC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 32\n \n /* MC_CMD_DRIVER_EVENT_OUT msgresponse */\n #define\tMC_CMD_DRIVER_EVENT_OUT_LEN 0\n@@ -9760,6 +10999,7 @@\n  * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.\n  */\n #define\tMC_CMD_PROXY_CMD 0x5b\n+#define\tMC_CMD_PROXY_CMD_MSGSET 0x5b\n #undef\tMC_CMD_0x5b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -9828,6 +11068,7 @@\n  * a designated admin function\n  */\n #define\tMC_CMD_PROXY_CONFIGURE 0x58\n+#define\tMC_CMD_PROXY_CONFIGURE_MSGSET 0x58\n #undef\tMC_CMD_0x58_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -9845,7 +11086,13 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LBN 32\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LBN 64\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_WIDTH 32\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12\n #define\tMC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4\n@@ -9855,7 +11102,13 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LBN 128\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LBN 160\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4\n@@ -9866,7 +11119,13 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LBN 224\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LBN 256\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_WIDTH 32\n /* Must be a power of 2, or zero if this buffer is not provided */\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36\n #define\tMC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4\n@@ -9890,7 +11149,13 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LBN 32\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LBN 64\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_WIDTH 32\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4\n@@ -9900,7 +11165,13 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LBN 128\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LBN 160\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_WIDTH 32\n /* Must be a power of 2 */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4\n@@ -9911,7 +11182,13 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LBN 224\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_WIDTH 32\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LBN 256\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_WIDTH 32\n /* Must be a power of 2, or zero if this buffer is not provided */\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4\n@@ -9936,6 +11213,7 @@\n  * MC_CMD_PROXY_CONFIGURE).\n  */\n #define\tMC_CMD_PROXY_COMPLETE 0x5f\n+#define\tMC_CMD_PROXY_COMPLETE_MSGSET 0x5f\n #undef\tMC_CMD_0x5f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -9974,6 +11252,7 @@\n  * cannot do so). The buffer table entries will initially be zeroed.\n  */\n #define\tMC_CMD_ALLOC_BUFTBL_CHUNK 0x87\n+#define\tMC_CMD_ALLOC_BUFTBL_CHUNK_MSGSET 0x87\n #undef\tMC_CMD_0x87_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -10005,6 +11284,7 @@\n  * Reprogram a set of buffer table entries in the specified chunk.\n  */\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_MSGSET 0x88\n #undef\tMC_CMD_0x88_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -10027,7 +11307,13 @@\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LBN 96\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_WIDTH 32\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LBN 128\n+#define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_WIDTH 32\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32\n #define\tMC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32\n@@ -10040,6 +11326,7 @@\n /* MC_CMD_FREE_BUFTBL_CHUNK\n  */\n #define\tMC_CMD_FREE_BUFTBL_CHUNK 0x89\n+#define\tMC_CMD_FREE_BUFTBL_CHUNK_MSGSET 0x89\n #undef\tMC_CMD_0x89_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -10058,6 +11345,7 @@\n  * Multiplexed MCDI call for filter operations\n  */\n #define\tMC_CMD_FILTER_OP 0x8a\n+#define\tMC_CMD_FILTER_OP_MSGSET 0x8a\n #undef\tMC_CMD_0x8a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -10083,7 +11371,13 @@\n #define\tMC_CMD_FILTER_OP_IN_HANDLE_OFST 4\n #define\tMC_CMD_FILTER_OP_IN_HANDLE_LEN 8\n #define\tMC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 32\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 32\n #define\tMC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 64\n+#define\tMC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 32\n /* The port ID associated with the v-adaptor which should contain this filter.\n  */\n #define\tMC_CMD_FILTER_OP_IN_PORT_ID_OFST 12\n@@ -10239,7 +11533,13 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4\n #define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8\n #define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 32\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 32\n #define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 64\n+#define\tMC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 32\n /* The port ID associated with the v-adaptor which should contain this filter.\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12\n@@ -10518,7 +11818,13 @@\n #define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4\n #define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8\n #define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 32\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 32\n #define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 64\n+#define\tMC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 32\n /* The port ID associated with the v-adaptor which should contain this filter.\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12\n@@ -10779,15 +12085,15 @@\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156\n #define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16\n-/* Flags controlling mutations of the user_mark and user_flag fields of\n- * matching packets, with logic as follows: if (req.MATCH_BITOR_FLAG == 1)\n- * user_flag = req.MATCH_SET_FLAG bit_or user_flag; else user_flag =\n- * req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark = 0; else if\n- * (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK bit_or user_mark;\n- * else user_mark = req.MATCH_SET_MARK; N.B. These flags overlap with the\n- * MATCH_ACTION field, which is deprecated in favour of this field. For the\n- * cases where these flags induce a valid encoding of the MATCH_ACTION field,\n- * the semantics agree.\n+/* Flags controlling mutations of the packet and/or metadata when the filter is\n+ * matched. The user_mark and user_flag fields' logic is as follows: if\n+ * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;\n+ * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark\n+ * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK\n+ * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags\n+ * overlap with the MATCH_ACTION field, which is deprecated in favour of this\n+ * field. For the cases where these flags induce a valid encoding of the\n+ * MATCH_ACTION field, the semantics agree.\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4\n@@ -10803,6 +12109,9 @@\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1\n /* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the\n  * functionality of this field in an ABI-backwards-compatible manner, and\n  * should be used instead. Any future extensions should be made to the\n@@ -10848,7 +12157,13 @@\n #define\tMC_CMD_FILTER_OP_OUT_HANDLE_OFST 4\n #define\tMC_CMD_FILTER_OP_OUT_HANDLE_LEN 8\n #define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 32\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 32\n #define\tMC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 64\n+#define\tMC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 32\n /* enum: guaranteed invalid filter handle (low 32 bits) */\n #define\tMC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff\n /* enum: guaranteed invalid filter handle (high 32 bits) */\n@@ -10868,7 +12183,13 @@\n #define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4\n #define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8\n #define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 32\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 32\n #define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 64\n+#define\tMC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               MC_CMD_FILTER_OP_OUT/HANDLE */\n \n@@ -10878,6 +12199,7 @@\n  * Get information related to the parser-dispatcher subsystem\n  */\n #define\tMC_CMD_GET_PARSER_DISP_INFO 0xe4\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_MSGSET 0xe4\n #undef\tMC_CMD_0xe4_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11025,6 +12347,7 @@\n  * permitted.\n  */\n #define\tMC_CMD_PARSER_DISP_RW 0xe5\n+#define\tMC_CMD_PARSER_DISP_RW_MSGSET 0xe5\n #undef\tMC_CMD_0xe5_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -11115,6 +12438,7 @@\n  * Get number of PFs on the device.\n  */\n #define\tMC_CMD_GET_PF_COUNT 0xb6\n+#define\tMC_CMD_GET_PF_COUNT_MSGSET 0xb6\n #undef\tMC_CMD_0xb6_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11134,6 +12458,7 @@\n  * Set number of PFs on the device.\n  */\n #define\tMC_CMD_SET_PF_COUNT 0xb7\n+#define\tMC_CMD_SET_PF_COUNT_MSGSET 0xb7\n \n /* MC_CMD_SET_PF_COUNT_IN msgrequest */\n #define\tMC_CMD_SET_PF_COUNT_IN_LEN 4\n@@ -11150,6 +12475,7 @@\n  * Get port assignment for current PCI function.\n  */\n #define\tMC_CMD_GET_PORT_ASSIGNMENT 0xb8\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT_MSGSET 0xb8\n #undef\tMC_CMD_0xb8_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11175,6 +12501,7 @@\n  * Set port assignment for current PCI function.\n  */\n #define\tMC_CMD_SET_PORT_ASSIGNMENT 0xb9\n+#define\tMC_CMD_SET_PORT_ASSIGNMENT_MSGSET 0xb9\n #undef\tMC_CMD_0xb9_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -11194,6 +12521,7 @@\n  * Allocate VIs for current PCI function.\n  */\n #define\tMC_CMD_ALLOC_VIS 0x8b\n+#define\tMC_CMD_ALLOC_VIS_MSGSET 0x8b\n #undef\tMC_CMD_0x8b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11241,6 +12569,7 @@\n  * but not freed.\n  */\n #define\tMC_CMD_FREE_VIS 0x8c\n+#define\tMC_CMD_FREE_VIS_MSGSET 0x8c\n #undef\tMC_CMD_0x8c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11257,6 +12586,7 @@\n  * Get SRIOV config for this PF.\n  */\n #define\tMC_CMD_GET_SRIOV_CFG 0xba\n+#define\tMC_CMD_GET_SRIOV_CFG_MSGSET 0xba\n #undef\tMC_CMD_0xba_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11290,6 +12620,7 @@\n  * Set SRIOV config for this PF.\n  */\n #define\tMC_CMD_SET_SRIOV_CFG 0xbb\n+#define\tMC_CMD_SET_SRIOV_CFG_MSGSET 0xbb\n #undef\tMC_CMD_0xbb_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -11325,9 +12656,11 @@\n /***********************************/\n /* MC_CMD_GET_VI_ALLOC_INFO\n  * Get information about number of VI's and base VI number allocated to this\n- * function.\n+ * function. This message is not available to dynamic clients created by\n+ * MC_CMD_CLIENT_ALLOC.\n  */\n #define\tMC_CMD_GET_VI_ALLOC_INFO 0x8d\n+#define\tMC_CMD_GET_VI_ALLOC_INFO_MSGSET 0x8d\n #undef\tMC_CMD_0x8d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11352,9 +12685,12 @@\n \n /***********************************/\n /* MC_CMD_DUMP_VI_STATE\n- * For CmdClient use. Dump pertinent information on a specific absolute VI.\n+ * For CmdClient use. Dump pertinent information on a specific absolute VI. The\n+ * VI must be owned by the calling client or one of its ancestors; usership of\n+ * the VI (as set by MC_CMD_SET_VI_USER) is not sufficient.\n  */\n #define\tMC_CMD_DUMP_VI_STATE 0x8e\n+#define\tMC_CMD_DUMP_VI_STATE_MSGSET 0x8e\n #undef\tMC_CMD_0x8e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11366,7 +12702,7 @@\n #define\tMC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4\n \n /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */\n-#define\tMC_CMD_DUMP_VI_STATE_OUT_LEN 96\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_LEN 100\n /* The PF part of the function owning this VI. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2\n@@ -11389,12 +12725,24 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LBN 96\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LBN 128\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_WIDTH 32\n /* Raw evq timer table data. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LBN 160\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LBN 192\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_WIDTH 32\n /* Combined metadata field. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4\n@@ -11411,22 +12759,46 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LBN 256\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LBN 288\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_WIDTH 32\n /* TXDPCPU raw table data for queue. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LBN 320\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LBN 352\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_WIDTH 32\n /* TXDPCPU raw table data for queue. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LBN 384\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LBN 416\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_WIDTH 32\n /* Combined metadata field. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LBN 448\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LBN 480\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16\n@@ -11446,22 +12818,46 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LBN 512\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LBN 544\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_WIDTH 32\n /* RXDPCPU raw table data for queue. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LBN 576\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LBN 608\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_WIDTH 32\n /* Reserved, currently 0. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LBN 640\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LBN 672\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_WIDTH 32\n /* Combined metadata field. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LBN 704\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LBN 736\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_WIDTH 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16\n@@ -11474,6 +12870,9 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8\n+/* Current user, as assigned by MC_CMD_SET_VI_USER. */\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_OFST 96\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4\n \n \n /***********************************/\n@@ -11481,6 +12880,7 @@\n  * Allocate a push I/O buffer for later use with a tx queue.\n  */\n #define\tMC_CMD_ALLOC_PIOBUF 0x8f\n+#define\tMC_CMD_ALLOC_PIOBUF_MSGSET 0x8f\n #undef\tMC_CMD_0x8f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -11500,6 +12900,7 @@\n  * Free a push I/O buffer.\n  */\n #define\tMC_CMD_FREE_PIOBUF 0x90\n+#define\tMC_CMD_FREE_PIOBUF_MSGSET 0x90\n #undef\tMC_CMD_0x90_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -11516,9 +12917,12 @@\n \n /***********************************/\n /* MC_CMD_GET_VI_TLP_PROCESSING\n- * Get TLP steering and ordering information for a VI.\n+ * Get TLP steering and ordering information for a VI. The caller must have the\n+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or\n+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_GET_VI_TLP_PROCESSING 0xb0\n+#define\tMC_CMD_GET_VI_TLP_PROCESSING_MSGSET 0xb0\n #undef\tMC_CMD_0xb0_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11555,9 +12959,12 @@\n \n /***********************************/\n /* MC_CMD_SET_VI_TLP_PROCESSING\n- * Set TLP steering and ordering information for a VI.\n+ * Set TLP steering and ordering information for a VI. The caller must have the\n+ * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or\n+ * an ancestor of the current user (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_SET_VI_TLP_PROCESSING 0xb1\n+#define\tMC_CMD_SET_VI_TLP_PROCESSING_MSGSET 0xb1\n #undef\tMC_CMD_0xb1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -11597,6 +13004,7 @@\n  * Get global PCIe steering and transaction processing configuration.\n  */\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_MSGSET 0xbc\n #undef\tMC_CMD_0xbc_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -11681,6 +13089,7 @@\n  * Set global PCIe steering and transaction processing configuration.\n  */\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_MSGSET 0xbd\n #undef\tMC_CMD_0xbd_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -11746,6 +13155,7 @@\n  * Download a new set of images to the satellite CPUs from the host.\n  */\n #define\tMC_CMD_SATELLITE_DOWNLOAD 0x91\n+#define\tMC_CMD_SATELLITE_DOWNLOAD_MSGSET 0x91\n #undef\tMC_CMD_0x91_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -11873,6 +13283,7 @@\n  * reference inherent device capabilities as opposed to current NVRAM config.\n  */\n #define\tMC_CMD_GET_CAPABILITIES 0xbe\n+#define\tMC_CMD_GET_CAPABILITIES_MSGSET 0xbe\n #undef\tMC_CMD_0xbe_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -14813,6 +16224,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n #define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1\n \n /* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160\n@@ -15299,6 +16722,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1\n /* These bits are reserved for communicating test-specific capabilities to\n  * host-side test software. All production drivers should treat this field as\n  * opaque.\n@@ -15306,7 +16741,13 @@\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 1216\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 32\n #define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 1248\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 32\n \n /* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184\n@@ -15793,6 +17234,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1\n /* These bits are reserved for communicating test-specific capabilities to\n  * host-side test software. All production drivers should treat this field as\n  * opaque.\n@@ -15800,7 +17253,13 @@\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 1216\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 32\n #define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 1248\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 32\n /* The minimum size (in table entries) of indirection table to be allocated\n  * from the pool for an RSS context. Note that the table size used must be a\n  * power of 2.\n@@ -16322,6 +17781,18 @@\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1\n /* These bits are reserved for communicating test-specific capabilities to\n  * host-side test software. All production drivers should treat this field as\n  * opaque.\n@@ -16329,7 +17800,13 @@\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 1216\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 32\n #define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 1248\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 32\n /* The minimum size (in table entries) of indirection table to be allocated\n  * from the pool for an RSS context. Note that the table size used must be a\n  * power of 2.\n@@ -16386,6 +17863,7 @@\n  * Encapsulation for a v2 extended command\n  */\n #define\tMC_CMD_V2_EXTN 0x7f\n+#define\tMC_CMD_V2_EXTN_MSGSET 0x7f\n \n /* MC_CMD_V2_EXTN_IN msgrequest */\n #define\tMC_CMD_V2_EXTN_IN_LEN 4\n@@ -16417,6 +17895,7 @@\n  * Allocate a pacer bucket (for qau rp or a snapper test)\n  */\n #define\tMC_CMD_TCM_BUCKET_ALLOC 0xb2\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_MSGSET 0xb2\n #undef\tMC_CMD_0xb2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16436,6 +17915,7 @@\n  * Free a pacer bucket\n  */\n #define\tMC_CMD_TCM_BUCKET_FREE 0xb3\n+#define\tMC_CMD_TCM_BUCKET_FREE_MSGSET 0xb3\n #undef\tMC_CMD_0xb3_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16455,6 +17935,7 @@\n  * Initialise pacer bucket with a given rate\n  */\n #define\tMC_CMD_TCM_BUCKET_INIT 0xb4\n+#define\tMC_CMD_TCM_BUCKET_INIT_MSGSET 0xb4\n #undef\tMC_CMD_0xb4_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16489,6 +17970,7 @@\n  * Initialise txq in pacer with given options or set options\n  */\n #define\tMC_CMD_TCM_TXQ_INIT 0xb5\n+#define\tMC_CMD_TCM_TXQ_INIT_MSGSET 0xb5\n #undef\tMC_CMD_0xb5_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16579,6 +18061,7 @@\n  * Link a push I/O buffer to a TxQ\n  */\n #define\tMC_CMD_LINK_PIOBUF 0x92\n+#define\tMC_CMD_LINK_PIOBUF_MSGSET 0x92\n #undef\tMC_CMD_0x92_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -16588,7 +18071,7 @@\n /* Handle for allocated push I/O buffer. */\n #define\tMC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0\n #define\tMC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4\n-/* Function Local Instance (VI) number. */\n+/* Function Local Instance (VI) number which has a TxQ allocated to it. */\n #define\tMC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4\n #define\tMC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4\n \n@@ -16601,6 +18084,7 @@\n  * Unlink a push I/O buffer from a TxQ\n  */\n #define\tMC_CMD_UNLINK_PIOBUF 0x93\n+#define\tMC_CMD_UNLINK_PIOBUF_MSGSET 0x93\n #undef\tMC_CMD_0x93_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -16620,6 +18104,7 @@\n  * allocate and initialise a v-switch.\n  */\n #define\tMC_CMD_VSWITCH_ALLOC 0x94\n+#define\tMC_CMD_VSWITCH_ALLOC_MSGSET 0x94\n #undef\tMC_CMD_0x94_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16667,6 +18152,7 @@\n  * de-allocate a v-switch.\n  */\n #define\tMC_CMD_VSWITCH_FREE 0x95\n+#define\tMC_CMD_VSWITCH_FREE_MSGSET 0x95\n #undef\tMC_CMD_0x95_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16688,6 +18174,7 @@\n  * not, then the command returns ENOENT).\n  */\n #define\tMC_CMD_VSWITCH_QUERY 0x63\n+#define\tMC_CMD_VSWITCH_QUERY_MSGSET 0x63\n #undef\tMC_CMD_0x63_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16707,6 +18194,7 @@\n  * allocate a v-port.\n  */\n #define\tMC_CMD_VPORT_ALLOC 0x96\n+#define\tMC_CMD_VPORT_ALLOC_MSGSET 0x96\n #undef\tMC_CMD_0x96_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16774,6 +18262,7 @@\n  * de-allocate a v-port.\n  */\n #define\tMC_CMD_VPORT_FREE 0x97\n+#define\tMC_CMD_VPORT_FREE_MSGSET 0x97\n #undef\tMC_CMD_0x97_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16793,6 +18282,7 @@\n  * allocate a v-adaptor.\n  */\n #define\tMC_CMD_VADAPTOR_ALLOC 0x98\n+#define\tMC_CMD_VADAPTOR_ALLOC_MSGSET 0x98\n #undef\tMC_CMD_0x98_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16841,6 +18331,7 @@\n  * de-allocate a v-adaptor.\n  */\n #define\tMC_CMD_VADAPTOR_FREE 0x99\n+#define\tMC_CMD_VADAPTOR_FREE_MSGSET 0x99\n #undef\tMC_CMD_0x99_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16860,6 +18351,7 @@\n  * assign a new MAC address to a v-adaptor.\n  */\n #define\tMC_CMD_VADAPTOR_SET_MAC 0x5d\n+#define\tMC_CMD_VADAPTOR_SET_MAC_MSGSET 0x5d\n #undef\tMC_CMD_0x5d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16882,6 +18374,7 @@\n  * read the MAC address assigned to a v-adaptor.\n  */\n #define\tMC_CMD_VADAPTOR_GET_MAC 0x5e\n+#define\tMC_CMD_VADAPTOR_GET_MAC_MSGSET 0x5e\n #undef\tMC_CMD_0x5e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16904,6 +18397,7 @@\n  * read some config of v-adaptor.\n  */\n #define\tMC_CMD_VADAPTOR_QUERY 0x61\n+#define\tMC_CMD_VADAPTOR_QUERY_MSGSET 0x61\n #undef\tMC_CMD_0x61_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16932,6 +18426,7 @@\n  * assign a port to a PCI function.\n  */\n #define\tMC_CMD_EVB_PORT_ASSIGN 0x9a\n+#define\tMC_CMD_EVB_PORT_ASSIGN_MSGSET 0x9a\n #undef\tMC_CMD_0x9a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -16960,6 +18455,7 @@\n  * Assign the 64 bit region addresses.\n  */\n #define\tMC_CMD_RDWR_A64_REGIONS 0x9b\n+#define\tMC_CMD_RDWR_A64_REGIONS_MSGSET 0x9b\n #undef\tMC_CMD_0x9b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -16999,6 +18495,7 @@\n  * Allocate an Onload stack ID.\n  */\n #define\tMC_CMD_ONLOAD_STACK_ALLOC 0x9c\n+#define\tMC_CMD_ONLOAD_STACK_ALLOC_MSGSET 0x9c\n #undef\tMC_CMD_0x9c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -17021,6 +18518,7 @@\n  * Free an Onload stack ID.\n  */\n #define\tMC_CMD_ONLOAD_STACK_FREE 0x9d\n+#define\tMC_CMD_ONLOAD_STACK_FREE_MSGSET 0x9d\n #undef\tMC_CMD_0x9d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD\n@@ -17040,6 +18538,7 @@\n  * Allocate an RSS context.\n  */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC 0x9e\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_MSGSET 0x9e\n #undef\tMC_CMD_0x9e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17140,6 +18639,7 @@\n  * Free an RSS context.\n  */\n #define\tMC_CMD_RSS_CONTEXT_FREE 0x9f\n+#define\tMC_CMD_RSS_CONTEXT_FREE_MSGSET 0x9f\n #undef\tMC_CMD_0x9f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17159,6 +18659,7 @@\n  * Set the Toeplitz hash key for an RSS context.\n  */\n #define\tMC_CMD_RSS_CONTEXT_SET_KEY 0xa0\n+#define\tMC_CMD_RSS_CONTEXT_SET_KEY_MSGSET 0xa0\n #undef\tMC_CMD_0xa0_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17181,6 +18682,7 @@\n  * Get the Toeplitz hash key for an RSS context.\n  */\n #define\tMC_CMD_RSS_CONTEXT_GET_KEY 0xa1\n+#define\tMC_CMD_RSS_CONTEXT_GET_KEY_MSGSET 0xa1\n #undef\tMC_CMD_0xa1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17205,6 +18707,7 @@\n  * when the RSS context is allocated without specifying a table size.\n  */\n #define\tMC_CMD_RSS_CONTEXT_SET_TABLE 0xa2\n+#define\tMC_CMD_RSS_CONTEXT_SET_TABLE_MSGSET 0xa2\n #undef\tMC_CMD_0xa2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17229,6 +18732,7 @@\n  * when the RSS context is allocated without specifying a table size.\n  */\n #define\tMC_CMD_RSS_CONTEXT_GET_TABLE 0xa3\n+#define\tMC_CMD_RSS_CONTEXT_GET_TABLE_MSGSET 0xa3\n #undef\tMC_CMD_0xa3_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17253,6 +18757,7 @@\n  * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.\n  */\n #define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_MSGSET 0x13e\n #undef\tMC_CMD_0x13e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17299,6 +18804,7 @@\n  * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.\n  */\n #define\tMC_CMD_RSS_CONTEXT_READ_TABLE 0x13f\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_MSGSET 0x13f\n #undef\tMC_CMD_0x13f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17338,6 +18844,7 @@\n  * Set various control flags for an RSS context.\n  */\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_MSGSET 0xe1\n #undef\tMC_CMD_0xe1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17404,6 +18911,7 @@\n  * Get various control flags for an RSS context.\n  */\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_MSGSET 0xe2\n #undef\tMC_CMD_0xe2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17471,6 +18979,7 @@\n  * Allocate a .1p mapping.\n  */\n #define\tMC_CMD_DOT1P_MAPPING_ALLOC 0xa4\n+#define\tMC_CMD_DOT1P_MAPPING_ALLOC_MSGSET 0xa4\n #undef\tMC_CMD_0xa4_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -17504,6 +19013,7 @@\n  * Free a .1p mapping.\n  */\n #define\tMC_CMD_DOT1P_MAPPING_FREE 0xa5\n+#define\tMC_CMD_DOT1P_MAPPING_FREE_MSGSET 0xa5\n #undef\tMC_CMD_0xa5_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -17523,6 +19033,7 @@\n  * Set the mapping table for a .1p mapping.\n  */\n #define\tMC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6\n+#define\tMC_CMD_DOT1P_MAPPING_SET_TABLE_MSGSET 0xa6\n #undef\tMC_CMD_0xa6_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -17547,6 +19058,7 @@\n  * Get the mapping table for a .1p mapping.\n  */\n #define\tMC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7\n+#define\tMC_CMD_DOT1P_MAPPING_GET_TABLE_MSGSET 0xa7\n #undef\tMC_CMD_0xa7_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -17571,6 +19083,7 @@\n  * Get Interrupt Vector config for this PF.\n  */\n #define\tMC_CMD_GET_VECTOR_CFG 0xbf\n+#define\tMC_CMD_GET_VECTOR_CFG_MSGSET 0xbf\n #undef\tMC_CMD_0xbf_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17596,6 +19109,7 @@\n  * Set Interrupt Vector config for this PF.\n  */\n #define\tMC_CMD_SET_VECTOR_CFG 0xc0\n+#define\tMC_CMD_SET_VECTOR_CFG_MSGSET 0xc0\n #undef\tMC_CMD_0xc0_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17623,6 +19137,7 @@\n  * Add a MAC address to a v-port\n  */\n #define\tMC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8\n+#define\tMC_CMD_VPORT_ADD_MAC_ADDRESS_MSGSET 0xa8\n #undef\tMC_CMD_0xa8_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17645,6 +19160,7 @@\n  * Delete a MAC address from a v-port\n  */\n #define\tMC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9\n+#define\tMC_CMD_VPORT_DEL_MAC_ADDRESS_MSGSET 0xa9\n #undef\tMC_CMD_0xa9_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17667,6 +19183,7 @@\n  * Delete a MAC address from a v-port\n  */\n #define\tMC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa\n+#define\tMC_CMD_VPORT_GET_MAC_ADDRESSES_MSGSET 0xaa\n #undef\tMC_CMD_0xaa_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17701,6 +19218,7 @@\n  * function will be reset before applying the changes.\n  */\n #define\tMC_CMD_VPORT_RECONFIGURE 0xeb\n+#define\tMC_CMD_VPORT_RECONFIGURE_MSGSET 0xeb\n #undef\tMC_CMD_0xeb_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17756,6 +19274,7 @@\n  * read some config of v-port.\n  */\n #define\tMC_CMD_EVB_PORT_QUERY 0x62\n+#define\tMC_CMD_EVB_PORT_QUERY_MSGSET 0x62\n #undef\tMC_CMD_0x62_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17786,6 +19305,7 @@\n  * lifted in future.\n  */\n #define\tMC_CMD_DUMP_BUFTBL_ENTRIES 0xab\n+#define\tMC_CMD_DUMP_BUFTBL_ENTRIES_MSGSET 0xab\n #undef\tMC_CMD_0xab_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -17818,6 +19338,7 @@\n  * Set global RXDP configuration settings\n  */\n #define\tMC_CMD_SET_RXDP_CONFIG 0xc1\n+#define\tMC_CMD_SET_RXDP_CONFIG_MSGSET 0xc1\n #undef\tMC_CMD_0xc1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -17848,6 +19369,7 @@\n  * Get global RXDP configuration settings\n  */\n #define\tMC_CMD_GET_RXDP_CONFIG 0xc2\n+#define\tMC_CMD_GET_RXDP_CONFIG_MSGSET 0xc2\n #undef\tMC_CMD_0xc2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17874,6 +19396,7 @@\n  * Return the system and PDCPU clock frequencies.\n  */\n #define\tMC_CMD_GET_CLOCK 0xac\n+#define\tMC_CMD_GET_CLOCK_MSGSET 0xac\n #undef\tMC_CMD_0xac_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -17896,6 +19419,7 @@\n  * Control the system and DPCPU clock frequencies. Changes are lost reboot.\n  */\n #define\tMC_CMD_SET_CLOCK 0xad\n+#define\tMC_CMD_SET_CLOCK_MSGSET 0xad\n #undef\tMC_CMD_0xad_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -17982,6 +19506,7 @@\n  * Send an arbitrary DPCPU message.\n  */\n #define\tMC_CMD_DPCPU_RPC 0xae\n+#define\tMC_CMD_DPCPU_RPC_MSGSET 0xae\n #undef\tMC_CMD_0xae_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -18100,6 +19625,7 @@\n  * Trigger an interrupt by prodding the BIU.\n  */\n #define\tMC_CMD_TRIGGER_INTERRUPT 0xe3\n+#define\tMC_CMD_TRIGGER_INTERRUPT_MSGSET 0xe3\n #undef\tMC_CMD_0xe3_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -18119,6 +19645,7 @@\n  * Special operations to support (for now) shmboot.\n  */\n #define\tMC_CMD_SHMBOOT_OP 0xe6\n+#define\tMC_CMD_SHMBOOT_OP_MSGSET 0xe6\n #undef\tMC_CMD_0xe6_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -18140,6 +19667,7 @@\n  * Read multiple 64bit words from capture block memory\n  */\n #define\tMC_CMD_CAP_BLK_READ 0xe7\n+#define\tMC_CMD_CAP_BLK_READ_MSGSET 0xe7\n #undef\tMC_CMD_0xe7_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -18162,7 +19690,13 @@\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_WIDTH 32\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LBN 32\n+#define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_WIDTH 32\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31\n #define\tMC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM_MCDI2 127\n@@ -18173,6 +19707,7 @@\n  * Take a dump of the DUT state\n  */\n #define\tMC_CMD_DUMP_DO 0xe8\n+#define\tMC_CMD_DUMP_DO_MSGSET 0xe8\n #undef\tMC_CMD_0xe8_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -18253,6 +19788,7 @@\n  * Configure unsolicited dumps\n  */\n #define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9\n+#define\tMC_CMD_DUMP_CONFIGURE_UNSOLICITED_MSGSET 0xe9\n #undef\tMC_CMD_0xe9_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -18322,6 +19858,7 @@\n  * the parameter is out of range.\n  */\n #define\tMC_CMD_SET_PSU 0xea\n+#define\tMC_CMD_SET_PSU_MSGSET 0xea\n #undef\tMC_CMD_0xea_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -18348,6 +19885,7 @@\n  * Get function information. PF and VF number.\n  */\n #define\tMC_CMD_GET_FUNCTION_INFO 0xec\n+#define\tMC_CMD_GET_FUNCTION_INFO_MSGSET 0xec\n #undef\tMC_CMD_0xec_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -18370,6 +19908,7 @@\n  * reboot.\n  */\n #define\tMC_CMD_ENABLE_OFFLINE_BIST 0xed\n+#define\tMC_CMD_ENABLE_OFFLINE_BIST_MSGSET 0xed\n #undef\tMC_CMD_0xed_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -18388,6 +19927,7 @@\n  * forget.\n  */\n #define\tMC_CMD_UART_SEND_DATA 0xee\n+#define\tMC_CMD_UART_SEND_DATA_MSGSET 0xee\n #undef\tMC_CMD_0xee_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -18426,6 +19966,7 @@\n  * subject to change and not currently implemented.\n  */\n #define\tMC_CMD_UART_RECV_DATA 0xef\n+#define\tMC_CMD_UART_RECV_DATA_MSGSET 0xef\n #undef\tMC_CMD_0xef_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -18475,6 +20016,7 @@\n  * Read data programmed into the device One-Time-Programmable (OTP) Fuses\n  */\n #define\tMC_CMD_READ_FUSES 0xf0\n+#define\tMC_CMD_READ_FUSES_MSGSET 0xf0\n #undef\tMC_CMD_0xf0_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -18510,6 +20052,7 @@\n  * Get or set KR Serdes RXEQ and TX Driver settings\n  */\n #define\tMC_CMD_KR_TUNE 0xf1\n+#define\tMC_CMD_KR_TUNE_MSGSET 0xf1\n #undef\tMC_CMD_0xf1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -19066,6 +20609,7 @@\n  * Get or set PCIE Serdes RXEQ and TX Driver settings\n  */\n #define\tMC_CMD_PCIE_TUNE 0xf2\n+#define\tMC_CMD_PCIE_TUNE_MSGSET 0xf2\n #undef\tMC_CMD_0xf2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -19323,6 +20867,7 @@\n  * - not used for V3 licensing\n  */\n #define\tMC_CMD_LICENSING 0xf3\n+#define\tMC_CMD_LICENSING_MSGSET 0xf3\n #undef\tMC_CMD_0xf3_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19379,6 +20924,7 @@\n  * - V3 licensing (Medford)\n  */\n #define\tMC_CMD_LICENSING_V3 0xd0\n+#define\tMC_CMD_LICENSING_V3_MSGSET 0xd0\n #undef\tMC_CMD_0xd0_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19429,7 +20975,13 @@\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LBN 192\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_WIDTH 32\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LBN 224\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_WIDTH 32\n /* reserved for future use */\n #define\tMC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32\n #define\tMC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24\n@@ -19437,7 +20989,13 @@\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LBN 448\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_WIDTH 32\n #define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LBN 480\n+#define\tMC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_WIDTH 32\n /* reserved for future use */\n #define\tMC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64\n #define\tMC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24\n@@ -19449,6 +21007,7 @@\n  * partition - V3 licensing (Medford)\n  */\n #define\tMC_CMD_LICENSING_GET_ID_V3 0xd1\n+#define\tMC_CMD_LICENSING_GET_ID_V3_MSGSET 0xd1\n #undef\tMC_CMD_0xd1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19482,6 +21041,7 @@\n  * This will fail on a single-core system.\n  */\n #define\tMC_CMD_MC2MC_PROXY 0xf4\n+#define\tMC_CMD_MC2MC_PROXY_MSGSET 0xf4\n #undef\tMC_CMD_0xf4_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19500,6 +21060,7 @@\n  * or a reboot of the MC.) Not used for V3 licensing\n  */\n #define\tMC_CMD_GET_LICENSED_APP_STATE 0xf5\n+#define\tMC_CMD_GET_LICENSED_APP_STATE_MSGSET 0xf5\n #undef\tMC_CMD_0xf5_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19528,6 +21089,7 @@\n  * operation or a reboot of the MC.) Used for V3 licensing (Medford)\n  */\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE 0xd2\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_MSGSET 0xd2\n #undef\tMC_CMD_0xd2_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19540,7 +21102,13 @@\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_WIDTH 32\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LBN 32\n+#define\tMC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_WIDTH 32\n \n /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */\n #define\tMC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4\n@@ -19560,6 +21128,7 @@\n  * operation or a reboot of the MC.) Used for V3 licensing (Medford)\n  */\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_MSGSET 0xd3\n #undef\tMC_CMD_0xd3_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19572,7 +21141,13 @@\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_WIDTH 32\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LBN 32\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_WIDTH 32\n \n /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8\n@@ -19580,7 +21155,13 @@\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_WIDTH 32\n #define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LBN 32\n+#define\tMC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_WIDTH 32\n \n \n /***********************************/\n@@ -19589,6 +21170,7 @@\n  * licensing.\n  */\n #define\tMC_CMD_LICENSED_APP_OP 0xf6\n+#define\tMC_CMD_LICENSED_APP_OP_MSGSET 0xf6\n #undef\tMC_CMD_0xf6_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19672,6 +21254,7 @@\n  * (Medford)\n  */\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP 0xd4\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_MSGSET 0xd4\n #undef\tMC_CMD_0xd4_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19685,7 +21268,13 @@\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LBN 384\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_WIDTH 32\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LBN 416\n+#define\tMC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_WIDTH 32\n \n /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */\n #define\tMC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116\n@@ -19725,6 +21314,7 @@\n  * Mask features - V3 licensing (Medford)\n  */\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES 0xd5\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_MSGSET 0xd5\n #undef\tMC_CMD_0xd5_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -19735,7 +21325,13 @@\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_WIDTH 32\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LBN 32\n+#define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_WIDTH 32\n /* whether to turn on or turn off the masked features */\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8\n #define\tMC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4\n@@ -19757,6 +21353,7 @@\n  * erased when the adapter is power cycled\n  */\n #define\tMC_CMD_LICENSING_V3_TEMPORARY 0xd6\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_MSGSET 0xd6\n #undef\tMC_CMD_0xd6_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -19815,7 +21412,13 @@\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LBN 32\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_WIDTH 32\n #define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LBN 64\n+#define\tMC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_WIDTH 32\n \n \n /***********************************/\n@@ -19827,6 +21430,7 @@\n  * delivered to a specific queue, or a set of queues with RSS.\n  */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG 0xf7\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_MSGSET 0xf7\n #undef\tMC_CMD_0xf7_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -19870,6 +21474,7 @@\n  * the configuration.\n  */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG 0xf8\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_MSGSET 0xf8\n #undef\tMC_CMD_0xf8_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19908,6 +21513,7 @@\n  * Change configuration related to the parser-dispatcher subsystem.\n  */\n #define\tMC_CMD_SET_PARSER_DISP_CONFIG 0xf9\n+#define\tMC_CMD_SET_PARSER_DISP_CONFIG_MSGSET 0xf9\n #undef\tMC_CMD_0xf9_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19953,6 +21559,7 @@\n  * Read configuration related to the parser-dispatcher subsystem.\n  */\n #define\tMC_CMD_GET_PARSER_DISP_CONFIG 0xfa\n+#define\tMC_CMD_GET_PARSER_DISP_CONFIG_MSGSET 0xfa\n #undef\tMC_CMD_0xfa_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -19997,6 +21604,7 @@\n  * dedicated as TX sniff receivers.\n  */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfb\n #undef\tMC_CMD_0xfb_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -20037,6 +21645,7 @@\n  * the configuration.\n  */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_MSGSET 0xfc\n #undef\tMC_CMD_0xfc_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20072,6 +21681,7 @@\n  * Per queue rx error stats.\n  */\n #define\tMC_CMD_RMON_STATS_RX_ERRORS 0xfe\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_MSGSET 0xfe\n #undef\tMC_CMD_0xfe_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20104,6 +21714,7 @@\n  * Find out about available PCIE resources\n  */\n #define\tMC_CMD_GET_PCIE_RESOURCE_INFO 0xfd\n+#define\tMC_CMD_GET_PCIE_RESOURCE_INFO_MSGSET 0xfd\n #undef\tMC_CMD_0xfd_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20143,6 +21754,7 @@\n  * Find out about available port modes\n  */\n #define\tMC_CMD_GET_PORT_MODES 0xff\n+#define\tMC_CMD_GET_PORT_MODES_MSGSET 0xff\n #undef\tMC_CMD_0xff_PRIVILEGE_CTG\n \n #define\tMC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20199,6 +21811,7 @@\n  * the new port mode, as the override does not affect PF configuration.\n  */\n #define\tMC_CMD_OVERRIDE_PORT_MODE 0x137\n+#define\tMC_CMD_OVERRIDE_PORT_MODE_MSGSET 0x137\n #undef\tMC_CMD_0x137_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -20223,6 +21836,7 @@\n  * Sample voltages on the ATB\n  */\n #define\tMC_CMD_READ_ATB 0x100\n+#define\tMC_CMD_READ_ATB_MSGSET 0x100\n #undef\tMC_CMD_0x100_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20253,6 +21867,7 @@\n  * enums here must correspond with those in MC_CMD_WORKAROUND.\n  */\n #define\tMC_CMD_GET_WORKAROUNDS 0x59\n+#define\tMC_CMD_GET_WORKAROUNDS_MSGSET 0x59\n #undef\tMC_CMD_0x59_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20290,6 +21905,7 @@\n  * Read/set privileges of an arbitrary PCIe function\n  */\n #define\tMC_CMD_PRIVILEGE_MASK 0x5a\n+#define\tMC_CMD_PRIVILEGE_MASK_MSGSET 0x5a\n #undef\tMC_CMD_0x5a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20351,6 +21967,20 @@\n #define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000\n /* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000\n+/* enum: This Function/client may call MC_CMD_CLIENT_ALLOC to create new\n+ * dynamic client children of itself.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000\n+/* enum: A dynamic client with this privilege may perform all the same DMA\n+ * operations as the function client from which it is descended.\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000\n+/* enum: A client with this privilege may perform DMA as any PCIe function on\n+ * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC\n+ * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address\n+ * space override (i.e. with the ADDR_SPC_EN bit set).\n+ */\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000\n /* enum: Set this bit to indicate that a new privilege mask is to be set,\n  * otherwise the command will only read the existing mask.\n  */\n@@ -20368,6 +21998,7 @@\n  * Read/set link state mode of a VF\n  */\n #define\tMC_CMD_LINK_STATE_MODE 0x5c\n+#define\tMC_CMD_LINK_STATE_MODE_MSGSET 0x5c\n #undef\tMC_CMD_0x5c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20407,6 +22038,7 @@\n  * parameter to MC_CMD_INIT_RXQ.\n  */\n #define\tMC_CMD_GET_SNAPSHOT_LENGTH 0x101\n+#define\tMC_CMD_GET_SNAPSHOT_LENGTH_MSGSET 0x101\n #undef\tMC_CMD_0x101_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -20429,6 +22061,7 @@\n  * Additional fuse diagnostics\n  */\n #define\tMC_CMD_FUSE_DIAGS 0x102\n+#define\tMC_CMD_FUSE_DIAGS_MSGSET 0x102\n #undef\tMC_CMD_0x102_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20483,6 +22116,7 @@\n  * included in one of the masks provided.\n  */\n #define\tMC_CMD_PRIVILEGE_MODIFY 0x60\n+#define\tMC_CMD_PRIVILEGE_MODIFY_MSGSET 0x60\n #undef\tMC_CMD_0x60_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -20527,6 +22161,7 @@\n  * Read XPM memory\n  */\n #define\tMC_CMD_XPM_READ_BYTES 0x103\n+#define\tMC_CMD_XPM_READ_BYTES_MSGSET 0x103\n #undef\tMC_CMD_0x103_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -20559,6 +22194,7 @@\n  * Write XPM memory\n  */\n #define\tMC_CMD_XPM_WRITE_BYTES 0x104\n+#define\tMC_CMD_XPM_WRITE_BYTES_MSGSET 0x104\n #undef\tMC_CMD_0x104_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20591,6 +22227,7 @@\n  * Read XPM sector\n  */\n #define\tMC_CMD_XPM_READ_SECTOR 0x105\n+#define\tMC_CMD_XPM_READ_SECTOR_MSGSET 0x105\n #undef\tMC_CMD_0x105_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20631,6 +22268,7 @@\n  * Write XPM sector\n  */\n #define\tMC_CMD_XPM_WRITE_SECTOR 0x106\n+#define\tMC_CMD_XPM_WRITE_SECTOR_MSGSET 0x106\n #undef\tMC_CMD_0x106_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20677,6 +22315,7 @@\n  * Invalidate XPM sector\n  */\n #define\tMC_CMD_XPM_INVALIDATE_SECTOR 0x107\n+#define\tMC_CMD_XPM_INVALIDATE_SECTOR_MSGSET 0x107\n #undef\tMC_CMD_0x107_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20696,6 +22335,7 @@\n  * Blank-check XPM memory and report bad locations\n  */\n #define\tMC_CMD_XPM_BLANK_CHECK 0x108\n+#define\tMC_CMD_XPM_BLANK_CHECK_MSGSET 0x108\n #undef\tMC_CMD_0x108_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20733,6 +22373,7 @@\n  * Blank-check and repair XPM memory\n  */\n #define\tMC_CMD_XPM_REPAIR 0x109\n+#define\tMC_CMD_XPM_REPAIR_MSGSET 0x109\n #undef\tMC_CMD_0x109_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20756,6 +22397,7 @@\n  * be performed on an unprogrammed part.\n  */\n #define\tMC_CMD_XPM_DECODER_TEST 0x10a\n+#define\tMC_CMD_XPM_DECODER_TEST_MSGSET 0x10a\n #undef\tMC_CMD_0x10a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20776,6 +22418,7 @@\n  * first available location to use, or fail with ENOSPC if none left.\n  */\n #define\tMC_CMD_XPM_WRITE_TEST 0x10b\n+#define\tMC_CMD_XPM_WRITE_TEST_MSGSET 0x10b\n #undef\tMC_CMD_0x10b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -20797,6 +22440,7 @@\n  * does match, otherwise it will respond with success before it jumps to IMEM.\n  */\n #define\tMC_CMD_EXEC_SIGNED 0x10c\n+#define\tMC_CMD_EXEC_SIGNED_MSGSET 0x10c\n #undef\tMC_CMD_0x10c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -20827,6 +22471,7 @@\n  * MC_CMD_EXEC_SIGNED.\n  */\n #define\tMC_CMD_PREPARE_SIGNED 0x10d\n+#define\tMC_CMD_PREPARE_SIGNED_MSGSET 0x10d\n #undef\tMC_CMD_0x10d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -20850,6 +22495,7 @@\n  * will be removed once it is regarded as stable.\n  */\n #define\tMC_CMD_SET_SECURITY_RULE 0x10f\n+#define\tMC_CMD_SET_SECURITY_RULE_MSGSET 0x10f\n #undef\tMC_CMD_0x10f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21040,6 +22686,7 @@\n  * development. This note will be removed once it is regarded as stable.\n  */\n #define\tMC_CMD_RESET_SECURITY_RULES 0x110\n+#define\tMC_CMD_RESET_SECURITY_RULES_MSGSET 0x110\n #undef\tMC_CMD_0x110_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21066,6 +22713,7 @@\n  * will be removed once it is regarded as stable.\n  */\n #define\tMC_CMD_GET_SECURITY_RULESET_VERSION 0x111\n+#define\tMC_CMD_GET_SECURITY_RULESET_VERSION_MSGSET 0x111\n #undef\tMC_CMD_0x111_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -21096,6 +22744,7 @@\n  * removed once it is regarded as stable.\n  */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_ALLOC_MSGSET 0x112\n #undef\tMC_CMD_0x112_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21134,6 +22783,7 @@\n  * removed once it is regarded as stable.\n  */\n #define\tMC_CMD_SECURITY_RULE_COUNTER_FREE 0x113\n+#define\tMC_CMD_SECURITY_RULE_COUNTER_FREE_MSGSET 0x113\n #undef\tMC_CMD_0x113_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21169,6 +22819,7 @@\n  * will be removed once it is regarded as stable.\n  */\n #define\tMC_CMD_SUBNET_MAP_SET_NODE 0x114\n+#define\tMC_CMD_SUBNET_MAP_SET_NODE_MSGSET 0x114\n #undef\tMC_CMD_0x114_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21224,6 +22875,7 @@\n  * will be removed once it is regarded as stable.\n  */\n #define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115\n+#define\tMC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_MSGSET 0x115\n #undef\tMC_CMD_0x115_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21258,6 +22910,7 @@\n  * will be removed once it is regarded as stable.\n  */\n #define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116\n+#define\tMC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_MSGSET 0x116\n #undef\tMC_CMD_0x116_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21311,6 +22964,7 @@\n  * cause all functions to see a reset. (Available on Medford only.)\n  */\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_MSGSET 0x117\n #undef\tMC_CMD_0x117_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -21357,6 +23011,7 @@\n  * priority.\n  */\n #define\tMC_CMD_RX_BALANCING 0x118\n+#define\tMC_CMD_RX_BALANCING_MSGSET 0x118\n #undef\tMC_CMD_0x118_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -21386,6 +23041,7 @@\n  * info in respect to the binding protocol.\n  */\n #define\tMC_CMD_TSA_BIND 0x119\n+#define\tMC_CMD_TSA_BIND_MSGSET 0x119\n #undef\tMC_CMD_0x119_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -21951,6 +23607,7 @@\n  * OP_GET_CACHED_VERSION. All other sub-operations are prohibited.\n  */\n #define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a\n+#define\tMC_CMD_MANAGE_SECURITY_RULESET_CACHE_MSGSET 0x11a\n #undef\tMC_CMD_0x11a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -22007,6 +23664,7 @@\n  * if the tag is already present.\n  */\n #define\tMC_CMD_NVRAM_PRIVATE_APPEND 0x11c\n+#define\tMC_CMD_NVRAM_PRIVATE_APPEND_MSGSET 0x11c\n #undef\tMC_CMD_0x11c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -22041,6 +23699,7 @@\n  * correctly at ATE.\n  */\n #define\tMC_CMD_XPM_VERIFY_CONTENTS 0x11b\n+#define\tMC_CMD_XPM_VERIFY_CONTENTS_MSGSET 0x11b\n #undef\tMC_CMD_0x11b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -22084,6 +23743,7 @@\n  * and TMR_RELOAD_ACT_NS).\n  */\n #define\tMC_CMD_SET_EVQ_TMR 0x120\n+#define\tMC_CMD_SET_EVQ_TMR_MSGSET 0x120\n #undef\tMC_CMD_0x120_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22122,6 +23782,7 @@\n  * Query properties about the event queue timers.\n  */\n #define\tMC_CMD_GET_EVQ_TMR_PROPERTIES 0x122\n+#define\tMC_CMD_GET_EVQ_TMR_PROPERTIES_MSGSET 0x122\n #undef\tMC_CMD_0x122_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22191,6 +23852,7 @@\n  * non used switch buffers.\n  */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_MSGSET 0x11d\n #undef\tMC_CMD_0x11d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22198,7 +23860,8 @@\n /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20\n /* Desired instance. Must be set to a specific instance, which is a function\n- * local queue index.\n+ * local queue index. The calling client must be the currently-assigned user of\n+ * this VI (see MC_CMD_SET_VI_USER).\n  */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4\n@@ -22243,6 +23906,7 @@\n  * previously allocated common pools.\n  */\n #define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e\n+#define\tMC_CMD_ALLOCATE_TX_VFIFO_VFIFO_MSGSET 0x11e\n #undef\tMC_CMD_0x11e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22296,6 +23960,7 @@\n  * ready to be re-used.\n  */\n #define\tMC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f\n+#define\tMC_CMD_TEARDOWN_TX_VFIFO_VF_MSGSET 0x11f\n #undef\tMC_CMD_0x11f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22316,6 +23981,7 @@\n  * it ready to be re-used.\n  */\n #define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121\n+#define\tMC_CMD_DEALLOCATE_TX_VFIFO_CP_MSGSET 0x121\n #undef\tMC_CMD_0x121_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22344,6 +24010,7 @@\n  * or 0 if there has not been a previous rekey.\n  */\n #define\tMC_CMD_REKEY 0x123\n+#define\tMC_CMD_REKEY_MSGSET 0x123\n #undef\tMC_CMD_0x123_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -22368,6 +24035,7 @@\n  * not yet assigned.\n  */\n #define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124\n+#define\tMC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_MSGSET 0x124\n #undef\tMC_CMD_0x124_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -22396,6 +24064,7 @@\n  * the required bits were not set.\n  */\n #define\tMC_CMD_SET_SECURITY_FUSES 0x126\n+#define\tMC_CMD_SET_SECURITY_FUSES_MSGSET 0x126\n #undef\tMC_CMD_0x126_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -22438,6 +24107,7 @@\n  * SF-117371-SW\n  */\n #define\tMC_CMD_TSA_INFO 0x127\n+#define\tMC_CMD_TSA_INFO_MSGSET 0x127\n #undef\tMC_CMD_0x127_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -22614,6 +24284,7 @@\n  * Doxbox reference SF-117371-SW\n  */\n #define\tMC_CMD_HOST_INFO 0x128\n+#define\tMC_CMD_HOST_INFO_MSGSET 0x128\n #undef\tMC_CMD_0x128_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -22681,6 +24352,7 @@\n  * section 'Adapter Information'\n  */\n #define\tMC_CMD_TSAN_INFO 0x129\n+#define\tMC_CMD_TSAN_INFO_MSGSET 0x129\n #undef\tMC_CMD_0x129_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -22780,6 +24452,7 @@\n  * TSA adapter statistics operations.\n  */\n #define\tMC_CMD_TSA_STATISTICS 0x130\n+#define\tMC_CMD_TSA_STATISTICS_MSGSET 0x130\n #undef\tMC_CMD_0x130_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -22884,14 +24557,26 @@\n #define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0\n #define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8\n #define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LEN 4\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LO_LBN 0\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LO_WIDTH 32\n #define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LEN 4\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_HI_LBN 32\n+#define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_HI_WIDTH 32\n #define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0\n #define\tMC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64\n /* Rx statistics counter */\n #define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8\n #define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8\n #define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LEN 4\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LO_LBN 64\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LO_WIDTH 32\n #define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LEN 4\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_HI_LBN 96\n+#define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_HI_WIDTH 32\n #define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64\n #define\tMC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64\n \n@@ -22904,6 +24589,7 @@\n  * installing TSA binding certificates. See SF-117631-TC.\n  */\n #define\tMC_CMD_ERASE_INITIAL_NIC_SECRET 0x131\n+#define\tMC_CMD_ERASE_INITIAL_NIC_SECRET_MSGSET 0x131\n #undef\tMC_CMD_0x131_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -22921,6 +24607,7 @@\n  * NIC for TSA binding.\n  */\n #define\tMC_CMD_TSA_CONFIG 0x64\n+#define\tMC_CMD_TSA_CONFIG_MSGSET 0x64\n #undef\tMC_CMD_0x64_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -23038,6 +24725,7 @@\n  * to a TSA adapter.\n  */\n #define\tMC_CMD_TSA_IPADDR 0x65\n+#define\tMC_CMD_TSA_IPADDR_MSGSET 0x65\n #undef\tMC_CMD_0x65_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -23089,7 +24777,13 @@\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_LBN 64\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_WIDTH 32\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_LBN 96\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_WIDTH 32\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126\n@@ -23119,7 +24813,13 @@\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_LBN 64\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_WIDTH 32\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_LBN 96\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_WIDTH 32\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM_MCDI2 126\n@@ -23135,6 +24835,7 @@\n  * disabled.\n  */\n #define\tMC_CMD_SECURE_NIC_INFO 0x132\n+#define\tMC_CMD_SECURE_NIC_INFO_MSGSET 0x132\n #undef\tMC_CMD_0x132_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -23228,6 +24929,7 @@\n  * parameters in request or response.\n  */\n #define\tMC_CMD_TSA_TEST 0x125\n+#define\tMC_CMD_TSA_TEST_MSGSET 0x125\n #undef\tMC_CMD_0x125_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -23249,6 +24951,7 @@\n  * rule-set transitions.\n  */\n #define\tMC_CMD_TSA_RULESET_OVERRIDE 0x12a\n+#define\tMC_CMD_TSA_RULESET_OVERRIDE_MSGSET 0x12a\n #undef\tMC_CMD_0x12a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -23281,6 +24984,7 @@\n  * Specific usage is determined by the TYPE field.\n  */\n #define\tMC_CMD_TSAC_REQUEST 0x12b\n+#define\tMC_CMD_TSAC_REQUEST_MSGSET 0x12b\n #undef\tMC_CMD_0x12b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -23305,6 +25009,7 @@\n  * Get the version of the SUC\n  */\n #define\tMC_CMD_SUC_VERSION 0x134\n+#define\tMC_CMD_SUC_VERSION_MSGSET 0x134\n #undef\tMC_CMD_0x134_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -23350,6 +25055,7 @@\n  * Operations to support manftest on SUC based systems.\n  */\n #define\tMC_CMD_SUC_MANFTEST 0x135\n+#define\tMC_CMD_SUC_MANFTEST_MSGSET 0x135\n #undef\tMC_CMD_0x135_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND\n@@ -23546,6 +25252,7 @@\n  * Request a certificate.\n  */\n #define\tMC_CMD_GET_CERTIFICATE 0x12c\n+#define\tMC_CMD_GET_CERTIFICATE_MSGSET 0x12c\n #undef\tMC_CMD_0x12c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -23620,6 +25327,7 @@\n  * Get a global value which applies to all PCI functions\n  */\n #define\tMC_CMD_GET_NIC_GLOBAL 0x12d\n+#define\tMC_CMD_GET_NIC_GLOBAL_MSGSET 0x12d\n #undef\tMC_CMD_0x12d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -23647,6 +25355,7 @@\n  * appropriate error otherwise (see key descriptions).\n  */\n #define\tMC_CMD_SET_NIC_GLOBAL 0x12e\n+#define\tMC_CMD_SET_NIC_GLOBAL_MSGSET 0x12e\n #undef\tMC_CMD_0x12e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -23694,6 +25403,7 @@\n  * firmware buffer for later extraction.\n  */\n #define\tMC_CMD_LTSSM_TRACE_POLL 0x12f\n+#define\tMC_CMD_LTSSM_TRACE_POLL_MSGSET 0x12f\n #undef\tMC_CMD_0x12f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x12f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -23731,7 +25441,13 @@\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_OFST 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LEN 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_OFST 8\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LEN 4\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_LBN 64\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_WIDTH 32\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_OFST 12\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LEN 4\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_LBN 96\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_WIDTH 32\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM_MCDI2 126\n@@ -23765,6 +25481,7 @@\n  * firmware variant.\n  */\n #define\tMC_CMD_TELEMETRY_ENABLE 0x138\n+#define\tMC_CMD_TELEMETRY_ENABLE_MSGSET 0x138\n #undef\tMC_CMD_0x138_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x138_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -23856,6 +25573,7 @@\n  * Reference - SF-120569-SW Telemetry Firmware Design.\n  */\n #define\tMC_CMD_TELEMETRY_CONFIG 0x139\n+#define\tMC_CMD_TELEMETRY_CONFIG_MSGSET 0x139\n #undef\tMC_CMD_0x139_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x139_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -23925,6 +25643,7 @@\n  * due to resource constraints, returns ENOSPC.\n  */\n #define\tMC_CMD_GET_RX_PREFIX_ID 0x13b\n+#define\tMC_CMD_GET_RX_PREFIX_ID_MSGSET 0x13b\n #undef\tMC_CMD_0x13b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x13b_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -23935,7 +25654,13 @@\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_WIDTH 32\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LBN 32\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_WIDTH 32\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1\n@@ -24056,6 +25781,7 @@\n  * created with that prefix id\n  */\n #define\tMC_CMD_QUERY_RX_PREFIX_ID 0x13c\n+#define\tMC_CMD_QUERY_RX_PREFIX_ID_MSGSET 0x13c\n #undef\tMC_CMD_0x13c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x13c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24092,6 +25818,7 @@\n  * A command to perform various bundle-related operations on insecure cards.\n  */\n #define\tMC_CMD_BUNDLE 0x13d\n+#define\tMC_CMD_BUNDLE_MSGSET 0x13d\n #undef\tMC_CMD_0x13d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x13d_PRIVILEGE_CTG SRIOV_CTG_INSECURE\n@@ -24154,6 +25881,7 @@\n  * Read all VPD starting from a given address\n  */\n #define\tMC_CMD_GET_VPD 0x165\n+#define\tMC_CMD_GET_VPD_MSGSET 0x165\n #undef\tMC_CMD_0x165_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x165_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24185,6 +25913,7 @@\n  * Provide information about the NC-SI stack\n  */\n #define\tMC_CMD_GET_NCSI_INFO 0x167\n+#define\tMC_CMD_GET_NCSI_INFO_MSGSET 0x167\n #undef\tMC_CMD_0x167_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x167_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24256,6 +25985,7 @@\n  * System lockdown, when enabled firmware updates are blocked.\n  */\n #define\tMC_CMD_FIRMWARE_SET_LOCKDOWN 0x16f\n+#define\tMC_CMD_FIRMWARE_SET_LOCKDOWN_MSGSET 0x16f\n #undef\tMC_CMD_0x16f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x16f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -24278,6 +26008,7 @@\n  * documentation.\n  */\n #define\tMC_CMD_GET_TEST_FEATURES 0x1ac\n+#define\tMC_CMD_GET_TEST_FEATURES_MSGSET 0x1ac\n #undef\tMC_CMD_0x1ac_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x1ac_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24300,6 +26031,253 @@\n #define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM 63\n #define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM_MCDI2 255\n \n+\n+/***********************************/\n+/* MC_CMD_FPGA\n+ * A command to perform various fpga-related operations on platforms that\n+ * include FPGAs. Note that some platforms may only support a subset of these\n+ * operations.\n+ */\n+#define\tMC_CMD_FPGA 0x1bf\n+#define\tMC_CMD_FPGA_MSGSET 0x1bf\n+#undef\tMC_CMD_0x1bf_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1bf_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_FPGA_IN msgrequest */\n+#define\tMC_CMD_FPGA_IN_LEN 4\n+/* Sub-command code */\n+#define\tMC_CMD_FPGA_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_IN_OP_LEN 4\n+/* enum: Get the FPGA version string. */\n+#define\tMC_CMD_FPGA_IN_OP_GET_VERSION 0x0\n+/* enum: Read bitmask of features supported in the FPGA image. */\n+#define\tMC_CMD_FPGA_IN_OP_GET_CAPABILITIES 0x1\n+/* enum: Perform a FPGA reset. */\n+#define\tMC_CMD_FPGA_IN_OP_RESET 0x2\n+/* enum: Set active flash device. */\n+#define\tMC_CMD_FPGA_IN_OP_SELECT_FLASH 0x3\n+/* enum: Get active flash device. */\n+#define\tMC_CMD_FPGA_IN_OP_GET_ACTIVE_FLASH 0x4\n+/* enum: Configure internal link i.e. the FPGA port facing the ASIC. */\n+#define\tMC_CMD_FPGA_IN_OP_SET_INTERNAL_LINK 0x5\n+/* enum: Read internal link configuration. */\n+#define\tMC_CMD_FPGA_IN_OP_GET_INTERNAL_LINK 0x6\n+\n+/* MC_CMD_FPGA_OP_GET_VERSION_IN msgrequest: Get the FPGA version string. A\n+ * free-format string is returned in response to this command. Any checks on\n+ * supported FPGA operations are based on the response to\n+ * MC_CMD_FPGA_OP_GET_CAPABILITIES.\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_IN_LEN 4\n+/* Sub-command code. Must be OP_GET_VERSION */\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_IN_OP_LEN 4\n+\n+/* MC_CMD_FPGA_OP_GET_VERSION_OUT msgresponse: Returns the version string. */\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_LENMIN 0\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX 252\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_LEN(num) (0+1*(num))\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_NUM(len) (((len)-0)/1)\n+/* Null-terminated string containing version information. */\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_LEN 1\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MINNUM 0\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM 252\n+#define\tMC_CMD_FPGA_OP_GET_VERSION_OUT_VERSION_MAXNUM_MCDI2 1020\n+\n+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_IN msgrequest: Read bitmask of features\n+ * supported in the FPGA image.\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_IN_LEN 4\n+/* Sub-command code. Must be OP_GET_CAPABILITIES */\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_IN_OP_LEN 4\n+\n+/* MC_CMD_FPGA_OP_GET_CAPABILITIES_OUT msgresponse: Returns the version string.\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_LEN 4\n+/* Bit-mask of supported features. */\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_CAPABILITIES_LEN 4\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_LBN 0\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAC_WIDTH 1\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_LBN 1\n+#define\tMC_CMD_FPGA_OP_GET_CAPABILITIES_OUT_MAE_WIDTH 1\n+\n+/* MC_CMD_FPGA_OP_RESET_IN msgrequest: Perform a FPGA reset operation where\n+ * supported.\n+ */\n+#define\tMC_CMD_FPGA_OP_RESET_IN_LEN 4\n+/* Sub-command code. Must be OP_RESET */\n+#define\tMC_CMD_FPGA_OP_RESET_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_RESET_IN_OP_LEN 4\n+\n+/* MC_CMD_FPGA_OP_RESET_OUT msgresponse */\n+#define\tMC_CMD_FPGA_OP_RESET_OUT_LEN 0\n+\n+/* MC_CMD_FPGA_OP_SELECT_FLASH_IN msgrequest: Set active FPGA flash device.\n+ * Returns EINVAL if selected flash index does not exist on the platform under\n+ * test.\n+ */\n+#define\tMC_CMD_FPGA_OP_SELECT_FLASH_IN_LEN 8\n+/* Sub-command code. Must be OP_SELECT_FLASH */\n+#define\tMC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_SELECT_FLASH_IN_OP_LEN 4\n+/* Flash device identifier. */\n+#define\tMC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_OFST 4\n+#define\tMC_CMD_FPGA_OP_SELECT_FLASH_IN_FLASH_ID_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FPGA_FLASH_INDEX */\n+\n+/* MC_CMD_FPGA_OP_SELECT_FLASH_OUT msgresponse */\n+#define\tMC_CMD_FPGA_OP_SELECT_FLASH_OUT_LEN 0\n+\n+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN msgrequest: Get active FPGA flash device.\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_LEN 4\n+/* Sub-command code. Must be OP_GET_ACTIVE_FLASH */\n+#define\tMC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_ACTIVE_FLASH_IN_OP_LEN 4\n+\n+/* MC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT msgresponse: Returns flash identifier\n+ * for current active flash.\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_LEN 4\n+/* Flash device identifier. */\n+#define\tMC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_ACTIVE_FLASH_OUT_FLASH_ID_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_FPGA_FLASH_INDEX */\n+\n+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN msgrequest: Configure FPGA internal\n+ * port, facing the ASIC\n+ */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LEN 12\n+/* Sub-command code. Must be OP_SET_INTERNAL_LINK */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_OP_LEN 4\n+/* Flags */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_OFST 4\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLAGS_LEN 4\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_OFST 4\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_LBN 0\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_LINK_STATE_WIDTH 2\n+/* enum: Unmodified, same as last state set by firmware */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_AUTO 0x0\n+/* enum: Configure link-up */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_UP 0x1\n+/* enum: Configure link-down */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_DOWN 0x2\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_OFST 4\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_LBN 2\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_FLUSH_WIDTH 1\n+/* Link speed to be applied on FPGA internal port MAC. */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_OFST 8\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN_SPEED_LEN 4\n+\n+/* MC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT msgresponse */\n+#define\tMC_CMD_FPGA_OP_SET_INTERNAL_LINK_OUT_LEN 0\n+\n+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN msgrequest: Read FPGA internal port\n+ * configuration and status\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_LEN 4\n+/* Sub-command code. Must be OP_GET_INTERNAL_LINK */\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_IN_OP_LEN 4\n+\n+/* MC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT msgresponse: Response format for read\n+ * FPGA internal port configuration and status\n+ */\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LEN 8\n+/* Flags */\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_OFST 0\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_LBN 0\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_LINK_STATE_WIDTH 2\n+/*             Enum values, see field(s): */\n+/*                MC_CMD_FPGA_OP_SET_INTERNAL_LINK_IN/FLAGS */\n+/* Link speed set on FPGA internal port MAC. */\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_OFST 4\n+#define\tMC_CMD_FPGA_OP_GET_INTERNAL_LINK_OUT_SPEED_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE\n+ * This command is expected to be used on a U25 board with an MAE in the FPGA.\n+ * It does not modify the operational state of the NIC. The modes are described\n+ * in XN-200039-TC - U25 OVS packet formats.\n+ */\n+#define\tMC_CMD_EXTERNAL_MAE_GET_LINK_MODE 0x1c0\n+#define\tMC_CMD_EXTERNAL_MAE_GET_LINK_MODE_MSGSET 0x1c0\n+#undef\tMC_CMD_0x1c0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c0_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN msgrequest */\n+#define\tMC_CMD_EXTERNAL_MAE_GET_LINK_MODE_IN_LEN 0\n+\n+/* MC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT msgresponse */\n+#define\tMC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_LEN 4\n+/* The current link mode */\n+#define\tMC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_OFST 0\n+#define\tMC_CMD_EXTERNAL_MAE_GET_LINK_MODE_OUT_MODE_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_EXTERNAL_MAE_LINK_MODE */\n+\n+\n+/***********************************/\n+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE\n+ * This command is expected to be used on a U25 board with an MAE in the FPGA.\n+ * The modes are described in XN-200039-TC - U25 OVS packet formats. This\n+ * command will set the link between the FPGA and the X2 to the specified new\n+ * mode. It will first enter bootstrap mode, make sure there are no packets in\n+ * flight and then enter the requested mode. In order to make sure there are no\n+ * packets in flight, it will flush the X2 TX path, the FPGA RX path from the\n+ * X2, the FPGA TX path to the X2 and the X2 RX path. The driver is responsible\n+ * for making sure there are no TX or RX descriptors posted on any TXQ or RXQ\n+ * associated with the affected port before invoking this command. This command\n+ * is run implicitly with MODE set to LEGACY when MC_CMD_DRV_ATTACH is\n+ * executed.\n+ */\n+#define\tMC_CMD_EXTERNAL_MAE_SET_LINK_MODE 0x1c1\n+#define\tMC_CMD_EXTERNAL_MAE_SET_LINK_MODE_MSGSET 0x1c1\n+#undef\tMC_CMD_0x1c1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c1_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN msgrequest */\n+#define\tMC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_LEN 4\n+/* The new link mode. */\n+#define\tMC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_OFST 0\n+#define\tMC_CMD_EXTERNAL_MAE_SET_LINK_MODE_IN_MODE_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_EXTERNAL_MAE_LINK_MODE */\n+\n+/* MC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT msgresponse */\n+#define\tMC_CMD_EXTERNAL_MAE_SET_LINK_MODE_OUT_LEN 0\n+\n+/* CLIENT_HANDLE structuredef: A client is an abstract entity that can make\n+ * requests of the device and that can own resources managed by the device.\n+ * Examples of clients include PCIe functions and dynamic clients. A client\n+ * handle is a 32b opaque value used to refer to a client. Further details can\n+ * be found within XN-200418-TC.\n+ */\n+#define\tCLIENT_HANDLE_LEN 4\n+#define\tCLIENT_HANDLE_OPAQUE_OFST 0\n+#define\tCLIENT_HANDLE_OPAQUE_LEN 4\n+/* enum: A client handle guaranteed never to refer to a real client. */\n+#define\tCLIENT_HANDLE_NULL 0xffffffff\n+/* enum: Used to refer to the calling client. */\n+#define\tCLIENT_HANDLE_SELF 0xfffffffe\n+#define\tCLIENT_HANDLE_OPAQUE_LBN 0\n+#define\tCLIENT_HANDLE_OPAQUE_WIDTH 32\n+\n /* CLOCK_INFO structuredef: Information about a single hardware clock */\n #define\tCLOCK_INFO_LEN 28\n /* Enumeration that uniquely identifies the clock */\n@@ -24333,7 +26311,13 @@\n #define\tCLOCK_INFO_FREQUENCY_OFST 4\n #define\tCLOCK_INFO_FREQUENCY_LEN 8\n #define\tCLOCK_INFO_FREQUENCY_LO_OFST 4\n+#define\tCLOCK_INFO_FREQUENCY_LO_LEN 4\n+#define\tCLOCK_INFO_FREQUENCY_LO_LBN 32\n+#define\tCLOCK_INFO_FREQUENCY_LO_WIDTH 32\n #define\tCLOCK_INFO_FREQUENCY_HI_OFST 8\n+#define\tCLOCK_INFO_FREQUENCY_HI_LEN 4\n+#define\tCLOCK_INFO_FREQUENCY_HI_LBN 64\n+#define\tCLOCK_INFO_FREQUENCY_HI_WIDTH 32\n #define\tCLOCK_INFO_FREQUENCY_LBN 32\n #define\tCLOCK_INFO_FREQUENCY_WIDTH 64\n /* Human-readable ASCII name for clock, with NUL termination */\n@@ -24343,12 +26327,62 @@\n #define\tCLOCK_INFO_NAME_LBN 96\n #define\tCLOCK_INFO_NAME_WIDTH 8\n \n+/* SCHED_CREDIT_CHECK_RESULT structuredef */\n+#define\tSCHED_CREDIT_CHECK_RESULT_LEN 16\n+/* The instance of the scheduler. Refer to XN-200389-AW for the location of\n+ * these schedulers in the hardware.\n+ */\n+#define\tSCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0\n+#define\tSCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */\n+#define\tSCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0\n+#define\tSCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8\n+/* The type of node that this result refers to. */\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1\n+/* enum: Destination node */\n+#define\tSCHED_CREDIT_CHECK_RESULT_DEST 0x0\n+/* enum: Source node */\n+#define\tSCHED_CREDIT_CHECK_RESULT_SOURCE 0x1\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8\n+/* Level of node in scheduler hierarchy (level 0 is the bottom of the\n+ * hierarchy, increasing towards the root node).\n+ */\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_OFST 2\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LEN 2\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LBN 16\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_WIDTH 16\n+/* Node index */\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LBN 32\n+#define\tSCHED_CREDIT_CHECK_RESULT_NODE_INDEX_WIDTH 32\n+/* The number of credits the node is expected to have. */\n+#define\tSCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_OFST 8\n+#define\tSCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4\n+#define\tSCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LBN 64\n+#define\tSCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_WIDTH 32\n+/* The number of credits the node actually had. */\n+#define\tSCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_OFST 12\n+#define\tSCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4\n+#define\tSCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96\n+#define\tSCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32\n+\n \n /***********************************/\n /* MC_CMD_GET_CLOCKS_INFO\n  * Get information about the device clocks\n  */\n #define\tMC_CMD_GET_CLOCKS_INFO 0x166\n+#define\tMC_CMD_GET_CLOCKS_INFO_MSGSET 0x166\n #undef\tMC_CMD_0x166_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x166_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24387,6 +26421,7 @@\n  * returns ENOSPC if the caller's table is full.\n  */\n #define\tMC_CMD_VNIC_ENCAP_RULE_ADD 0x16d\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_MSGSET 0x16d\n #undef\tMC_CMD_0x16d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24469,6 +26504,7 @@\n  * if the input HANDLE doesn't correspond to an existing rule.\n  */\n #define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e\n+#define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE_MSGSET 0x16e\n #undef\tMC_CMD_0x16e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24508,303 +26544,568 @@\n #define\tUUID_NODE_LBN 80\n #define\tUUID_NODE_WIDTH 48\n \n-/* MC_CMD_DEVEL_DUMP_VI_ENTRY structuredef */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_LEN 28\n-/* Type of entry */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_C2H 0x0 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_H2C 0x1 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_C2H 0x2 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_H2C 0x3 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_C2H 0x4 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_H2C 0x5 /* enum */\n-/* enum: First QDMA writeback/completion queue. Used for ef100, C2H VDPA and\n- * plain virtio.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_WRB 0x6\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_PFTCH 0x7 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_QTBL 0x100 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_C2H_QTBL 0x101 /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_VIO 0x10a /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LBN 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_WIDTH 32\n-/* Internal QDMA/dmac queue number for this entry */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_OFST 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LBN 32\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_WIDTH 32\n-/* Size of entry data */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_OFST 8\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LBN 64\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_WIDTH 32\n-/* Offset of entry data from start of MCDI message response payload */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_OFST 12\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LBN 96\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_WIDTH 32\n-/* Absolute VI of the entry, or 0xffffffff if not available/applicable */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_OFST 16\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_NO_ABS_VI 0xffffffff /* enum */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LBN 128\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_WIDTH 32\n-/* Reserved */\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_OFST 20\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LEN 8\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LO_OFST 20\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_HI_OFST 24\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LBN 160\n-#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_WIDTH 64\n-\n-\n-/***********************************/\n-/* MC_CMD_DEVEL_DUMP_VI\n- * Dump various parts of the hardware's state for a VI.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI 0x1b5\n-#undef\tMC_CMD_0x1b5_PRIVILEGE_CTG\n-\n-#define\tMC_CMD_0x1b5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n-\n-/* MC_CMD_DEVEL_DUMP_VI_IN msgrequest */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_LEN 4\n-/* Absolute queue id of queue to dump state for */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_QID_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_QID_LEN 4\n-\n-/* MC_CMD_DEVEL_DUMP_VI_IN_V2 msgrequest */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_LEN 20\n-/* Which queue to dump. The meaning of this field dependes on ADDRESS_MODE. */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ID_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ID_LEN 4\n-/* Method of referring to the queue to dump */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_OFST 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_LEN 4\n-/* enum: First field refers to queue number as understood by QDMA/DMAC hardware\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_QUEUE_NUMBER 0x0\n-/* enum: First field refers to absolute VI number */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ABS_VI 0x1\n-/* enum: First field refers to function-relative VI number on the command's\n- * function\n+/* PLUGIN_EXTENSION structuredef: Used within MC_CMD_PLUGIN_GET_ALL to describe\n+ * an individual extension.\n+ */\n+#define\tPLUGIN_EXTENSION_LEN 20\n+#define\tPLUGIN_EXTENSION_UUID_OFST 0\n+#define\tPLUGIN_EXTENSION_UUID_LEN 16\n+#define\tPLUGIN_EXTENSION_UUID_LBN 0\n+#define\tPLUGIN_EXTENSION_UUID_WIDTH 128\n+#define\tPLUGIN_EXTENSION_ADMIN_GROUP_OFST 16\n+#define\tPLUGIN_EXTENSION_ADMIN_GROUP_LEN 1\n+#define\tPLUGIN_EXTENSION_ADMIN_GROUP_LBN 128\n+#define\tPLUGIN_EXTENSION_ADMIN_GROUP_WIDTH 8\n+#define\tPLUGIN_EXTENSION_FLAG_ENABLED_LBN 136\n+#define\tPLUGIN_EXTENSION_FLAG_ENABLED_WIDTH 1\n+#define\tPLUGIN_EXTENSION_RESERVED_LBN 137\n+#define\tPLUGIN_EXTENSION_RESERVED_WIDTH 23\n+\n+/* DESC_ADDR_REGION structuredef: Describes a contiguous region of DESC_ADDR\n+ * space that maps to a contiguous region of TRGT_ADDR space. Addresses\n+ * DESC_ADDR in the range [DESC_ADDR_BASE:DESC_ADDR_BASE + 1 <<\n+ * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +\n+ * TRGT_ADDR_BASE.\n+ */\n+#define\tDESC_ADDR_REGION_LEN 32\n+/* The start of the region in DESC_ADDR space. */\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_LEN 8\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_LO_WIDTH 32\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_HI_LBN 32\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_HI_WIDTH 32\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0\n+#define\tDESC_ADDR_REGION_DESC_ADDR_BASE_WIDTH 64\n+/* The start of the region in TRGT_ADDR space. Drivers can set this via\n+ * MC_CMD_SET_DESC_ADDR_REGIONS.\n+ */\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_OFST 8\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_LEN 8\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_LO_OFST 8\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LBN 64\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_LO_WIDTH 32\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_HI_OFST 12\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LBN 96\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_HI_WIDTH 32\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_LBN 64\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_BASE_WIDTH 64\n+/* The size of the region. */\n+#define\tDESC_ADDR_REGION_WINDOW_SIZE_LOG2_OFST 16\n+#define\tDESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4\n+#define\tDESC_ADDR_REGION_WINDOW_SIZE_LOG2_LBN 128\n+#define\tDESC_ADDR_REGION_WINDOW_SIZE_LOG2_WIDTH 32\n+/* The alignment restriction on TRGT_ADDR. TRGT_ADDR values set by the driver\n+ * must be a multiple of 1 << TRGT_ADDR_ALIGN_LOG2.\n+ */\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_OFST 20\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LBN 160\n+#define\tDESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_WIDTH 32\n+#define\tDESC_ADDR_REGION_RSVD_OFST 24\n+#define\tDESC_ADDR_REGION_RSVD_LEN 8\n+#define\tDESC_ADDR_REGION_RSVD_LO_OFST 24\n+#define\tDESC_ADDR_REGION_RSVD_LO_LEN 4\n+#define\tDESC_ADDR_REGION_RSVD_LO_LBN 192\n+#define\tDESC_ADDR_REGION_RSVD_LO_WIDTH 32\n+#define\tDESC_ADDR_REGION_RSVD_HI_OFST 28\n+#define\tDESC_ADDR_REGION_RSVD_HI_LEN 4\n+#define\tDESC_ADDR_REGION_RSVD_HI_LBN 224\n+#define\tDESC_ADDR_REGION_RSVD_HI_WIDTH 32\n+#define\tDESC_ADDR_REGION_RSVD_LBN 192\n+#define\tDESC_ADDR_REGION_RSVD_WIDTH 64\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_DESC_ADDR_INFO\n+ * Returns a description of the mapping from DESC_ADDR to TRGT_ADDR for the calling function's address space.\n+ */\n+#define\tMC_CMD_GET_DESC_ADDR_INFO 0x1b7\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_MSGSET 0x1b7\n+#undef\tMC_CMD_0x1b7_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1b7_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_DESC_ADDR_INFO_IN msgrequest */\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0\n+\n+/* MC_CMD_GET_DESC_ADDR_INFO_OUT msgresponse */\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4\n+/* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once\n+ * written) for details of each type.\n+ */\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4\n+/* enum: TRGT_ADDR = DESC_ADDR */\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0\n+/* enum: DESC_ADDR has one or more regions that map into TRGT_ADDR. The base\n+ * TRGT_ADDR for each region is programmable via MCDI.\n+ */\n+#define\tMC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_DESC_ADDR_REGIONS\n+ * Returns a list of the DESC_ADDR regions for the calling function's address space.  Only valid if that function's address space has the REGIONED mapping from DESC_ADDR to TRGT_ADDR.\n+ */\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS 0x1b8\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_MSGSET 0x1b8\n+#undef\tMC_CMD_0x1b8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1b8_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_DESC_ADDR_REGIONS_IN msgrequest */\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0\n+\n+/* MC_CMD_GET_DESC_ADDR_REGIONS_OUT msgresponse */\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMIN 32\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX 224\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX_MCDI2 992\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)\n+/* An array of DESC_ADDR_REGION strutures. The number of entries in the array\n+ * indicates the number of available regions.\n+ */\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_LEN 32\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM 7\n+#define\tMC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM_MCDI2 31\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_DESC_ADDR_REGIONS\n+ * Set the base TRGT_ADDR for a set of DESC_ADDR regions for the calling function's address space.  Only valid if that function's address space had the REGIONED mapping from DESC_ADDR to TRGT_ADDR.\n+ */\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS 0x1b9\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_MSGSET 0x1b9\n+#undef\tMC_CMD_0x1b9_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1b9_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_DESC_ADDR_REGIONS_IN msgrequest */\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMIN 16\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX 248\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX_MCDI2 1016\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_LEN(num) (8+8*(num))\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)\n+/* A bitmask indicating which regions should have their base TRGT_ADDR updated.\n+ * To update the base TRGR_ADDR for a DESC_ADDR region, the corresponding bit\n+ * should be set to 1.\n+ */\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4\n+/* Reserved field; must be set to zero. */\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4\n+/* An array of values used to updated the base TRGT_ADDR for DESC_ADDR regions.\n+ * Array indices corresponding to region numbers (i.e. the array is sparse, and\n+ * included entries for regions even if the corresponding SET_REGION_MASK bit\n+ * is zero).\n  */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI 0x2\n-/* enum: First field refers to function-relative VI number on a specified\n- * function\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI_PROXY 0x3\n-/* Type of VI. Not needed if ADDRESS_MODE is QUEUE_NUMBER. */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_OFST 8\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_LEN 4\n-/* enum: Return only entries used for ef100 queues (a single hardware queue) */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_EF100 0x0\n-/* enum: Return entries used for virtio (Potentially two hardware queues,\n- * depending on hardware implementation)\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VIRTIO 0x1\n-/* Only if ADDRESS_MODE is REL_VI_PROXY. Interface of function the queue is on.\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_OFST 8\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LEN 8\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_OFST 8\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LBN 64\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_WIDTH 32\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_OFST 12\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LBN 96\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_WIDTH 32\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM 30\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM_MCDI2 126\n+\n+/* MC_CMD_SET_DESC_ADDR_REGIONS_OUT msgresponse */\n+#define\tMC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_CLIENT_CMD\n+ * Execute an arbitrary MCDI command on behalf of a different client. The\n+ * consequences of the command (e.g. ownership of any resources created) apply\n+ * to the indicated client rather than the function client which actually sent\n+ * this command. All inherent permission checks are also performed on the\n+ * indicated client. The given client must be a descendant of the requestor.\n+ * The command to be proxied follows immediately afterward in the host buffer\n+ * (or on the UART). Chaining multiple MC_CMD_CLIENT_CMD is unnecessary and not\n+ * supported. New dynamic clients may be created with MC_CMD_CLIENT_ALLOC.\n  */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_OFST 12\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_LEN 4\n-/*            Enum values, see field(s): */\n-/*               DEVEL_PCIE_INTERFACE */\n-/* Only if ADDRESS_MODE is REL_VI_PROXY. PF number of the function the queue is\n- * on.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PF_OFST 16\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PF_LEN 2\n-/* Only if ADDRESS_MODE is REL_VI_PROXY. VF number of the function the queue is\n- * on.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VF_OFST 18\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VF_LEN 2\n-/* enum: The function is on a PF, not a VF. */\n-#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VF_NULL 0xffff\n-\n-/* MC_CMD_DEVEL_DUMP_VI_OUT msgresponse */\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LENMIN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LENMAX 252\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LENMAX_MCDI2 1012\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LEN(num) (0+1*(num))\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_NUM(len) (((len)-0)/1)\n-/* Number of dump entries returned */\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_LBN 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_WIDTH 8\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_MINNUM 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM 252\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM_MCDI2 1020\n-/* Array of MC_CMD_DEVEL_DUMP_VI_ENTRY structures of length NUM_ENTRIES */\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_OFST 4\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_LEN 28\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MINNUM 0\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM 8\n-#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM_MCDI2 36\n-\n-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structuredef */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_LEN 16\n-/* What register this is */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LEN 4\n-/* enum: Catchall for registers that aren't in this enum. Nothing should be in\n- * this long-term\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_UNKNOWN 0xffffffff\n-/* enum: S2IC Converter Debug Packet Counter register. Informs number of\n- * packets passed through Converter.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_H2C_S2IC_DBG_PKT_CNT 0x0\n-/* enum: IC2S Converter Debug Packet Counter register. Informs number of\n- * packets passed through Converter.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_C2H_IC2S_DBG_PKT_CNT 0x1\n-/* enum: Event Controller Tx path Debug register. Count of Moderator Tx events,\n- * not incl D2C, VirtIO, Dproxy.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DEBUG 0x2\n-/* enum: Event Controller Rx path Debug register. Count of Moderator Rx events.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_DEBUG 0x3\n-/* enum: Event Controller Debug register. Count of Total EVC events. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TOTAL_DEBUG 0x4\n-/* enum: Same info as EVC_RX_DEBUG; collected at different location in design\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EF100_DEBUG 0x5\n-/* enum: Same info as EVC_TX_DEBUG; collected at different location in design\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_EF100_DEBUG 0x6\n-/* enum: Event Controller Debug register. Count of Tx VirtIO events. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTIO_DEBUG 0x7\n-/* enum: Event Controller Debug register. Count of Tx Descriptor Proxy events.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DPRXY_DEBUG 0x8\n-/* enum: Event Controller Debug register. Count of Tx VirtQ Descriptor Proxy\n- * events.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_DPRXY_DEBUG 0x9\n-/* enum: Event Controller Debug register. Count of Tx Descriptor-to-Completion\n- * events.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_D2C_DEBUG 0xa\n-/* enum: Event Controller Debug register. Count of Tx VirtIO Descriptor-to-\n- * Completion events.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_D2C_DEBUG 0xb\n-/* enum: Event Controller Debug register. Count of Tx Timestamp events. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_TSTAMP_DEBUG 0xc\n-/* enum: Event Controller Debug register. Count of Rx EvQ Timeout events. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EVQ_TIMEOUT_DEBUG 0xd\n-/* enum: Event Controller Debug register. Count of MC events. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_MC_DEBUG 0xe\n-/* enum: Event Controller Debug register. Count of EQDMA VirtIO Control events.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_EQDMA_VIO_CTL_DEBUG 0xf\n-/* enum: Counter of QDMA Dropped C2H packets. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_DMAC_C2H_DROP_CTR_REG 0x10\n-/* enum: Number of packets received by c host fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_IN_TBL 0x11\n-/* enum: Number of packets sent by c host fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_OUT_TBL 0x12\n-/* enum: Number of packets received by c plugin fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_P_PACKETS_IN_TBL 0x13\n-/* enum: Number of packets received by b host fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_H_PACKETS_IN_TBL 0x14\n-/* enum: Number of packets received by b net fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_N_PACKETS_IN_TBL 0x15\n-/* enum: Number of packets received by b host fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PH_PACKETS_IN_TBL 0x16\n-/* enum: Number of packets received by b net fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PN_PACKETS_IN_TBL 0x17\n-/* enum: Number of packets sent by b net fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PACKETS_OUT_TBL 0x18\n-/* enum: Number of packets received by c net fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_IN_TBL 0x19\n-/* enum: Number of packets sent by c net fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_OUT_TBL 0x1a\n-/* enum: Number of packets received by ha fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_IN_TBL 0x1b\n-/* enum: Number of packets received by ha host shadow fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PH_PACKETS_IN_TBL 0x1c\n-/* enum: Number of packets received by ha fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_OUT_TBL 0x1d\n-/* enum: Number of packets received by d hub fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_IN_TBL 0x1e\n-/* enum: Number of packets received by d hub plugin fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_P_PACKETS_IN_TBL 0x1f\n-/* enum: Number of packets received by d hub plugin fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_O_PACKETS_IN_TBL 0x20\n-/* enum: Number of packets sent to dmac. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_OUT_TBL 0x21\n-/* enum: Number of packets received by na fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_IN_TBL 0x22\n-/* enum: Number of packets dropped by na fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_DROPPED_TBL 0x23\n-/* enum: Number of packets sent by na fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_OUT_TBL 0x24\n-/* enum: Number of packets received by rp hub fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_IN_TBL 0x25\n-/* enum: Number of packets removed from fifo. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_OUT_TBL 0x26\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LBN 0\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_WIDTH 32\n-/* If REG is a table, the table row. */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_OFST 4\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LBN 32\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_WIDTH 32\n-/* Address of the register (as seen by the MC) */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_OFST 8\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LBN 64\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_WIDTH 32\n-/* Value of the register */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_OFST 12\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LEN 4\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LBN 96\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_WIDTH 32\n-\n-\n-/***********************************/\n-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS\n- * Dump an assortment of hopefully useful riverhead debug registers\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS 0x1b6\n-#undef\tMC_CMD_0x1b6_PRIVILEGE_CTG\n-\n-#define\tMC_CMD_0x1b6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n-\n-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN msgrequest */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_LEN 4\n-/* Which page of registers to retrieve. Page 0 always exists, later pages may\n- * also exist if there are too many registers to fit in a single mcdi response.\n- * NUM_PAGES in the response will tell you how many there are.\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_LEN 4\n-\n-/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT msgresponse */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMIN 8\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX 248\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX_MCDI2 1016\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LEN(num) (8+16*(num))\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_NUM(len) (((len)-8)/16)\n-/* Number of registers dumped in this response */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_OFST 0\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_LEN 4\n-/* How many pages of registers are available to extract */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_OFST 4\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_LEN 4\n-/* Array of MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structs, one for each register\n- */\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_OFST 8\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_LEN 16\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MINNUM 0\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM 15\n-#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM_MCDI2 63\n+#define\tMC_CMD_CLIENT_CMD 0x1ba\n+#define\tMC_CMD_CLIENT_CMD_MSGSET 0x1ba\n+#undef\tMC_CMD_0x1ba_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1ba_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_CLIENT_CMD_IN msgrequest */\n+#define\tMC_CMD_CLIENT_CMD_IN_LEN 4\n+/* The client as which to execute the following command. */\n+#define\tMC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0\n+#define\tMC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4\n+\n+/* MC_CMD_CLIENT_CMD_OUT msgresponse */\n+#define\tMC_CMD_CLIENT_CMD_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_CLIENT_ALLOC\n+ * Create a new client object. Clients are a system for delineating NIC\n+ * resource ownership, such that groups of resources may be torn down as a\n+ * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts\n+ * and a glossary. Clients created by this command are known as \"dynamic\n+ * clients\". The newly-created client is a child of the client which sent this\n+ * command. The caller must have the GRP_ALLOC_CLIENT privilege. The new client\n+ * initially has no permission to do anything; see\n+ * MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY.\n+ */\n+#define\tMC_CMD_CLIENT_ALLOC 0x1bb\n+#define\tMC_CMD_CLIENT_ALLOC_MSGSET 0x1bb\n+#undef\tMC_CMD_0x1bb_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1bb_PRIVILEGE_CTG SRIOV_CTG_ALLOC_CLIENT\n+\n+/* MC_CMD_CLIENT_ALLOC_IN msgrequest */\n+#define\tMC_CMD_CLIENT_ALLOC_IN_LEN 0\n+\n+/* MC_CMD_CLIENT_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_CLIENT_ALLOC_OUT_LEN 4\n+/* The ID of the new client object which has been created. */\n+#define\tMC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0\n+#define\tMC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_CLIENT_FREE\n+ * Destroy and release an existing client object. All resources owned by that\n+ * client (including its child clients, and thus all resources owned by the\n+ * entire family tree) are freed.\n+ */\n+#define\tMC_CMD_CLIENT_FREE 0x1bc\n+#define\tMC_CMD_CLIENT_FREE_MSGSET 0x1bc\n+#undef\tMC_CMD_0x1bc_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1bc_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_CLIENT_FREE_IN msgrequest */\n+#define\tMC_CMD_CLIENT_FREE_IN_LEN 4\n+/* The ID of the client to be freed. This client must be a descendant of the\n+ * requestor. A client cannot free itself.\n+ */\n+#define\tMC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0\n+#define\tMC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4\n+\n+/* MC_CMD_CLIENT_FREE_OUT msgresponse */\n+#define\tMC_CMD_CLIENT_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_VI_USER\n+ * Assign partial rights over this VI to another client. VIs have an 'owner'\n+ * and a 'user'. The owner is the client which allocated the VI\n+ * (MC_CMD_ALLOC_VIS) and cannot be changed. The user is the client which has\n+ * permission to create queues and other resources on that VI. Initially\n+ * user==owner, but the user can be changed by this command; the resources thus\n+ * created are then owned by the user-client. Only the VI owner can call this\n+ * command, and the request will fail if there are any outstanding child\n+ * resources (e.g. queues) currently allocated from this VI.\n+ */\n+#define\tMC_CMD_SET_VI_USER 0x1be\n+#define\tMC_CMD_SET_VI_USER_MSGSET 0x1be\n+#undef\tMC_CMD_0x1be_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1be_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_VI_USER_IN msgrequest */\n+#define\tMC_CMD_SET_VI_USER_IN_LEN 8\n+/* Function-relative VI number to modify. */\n+#define\tMC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0\n+#define\tMC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4\n+/* Client ID to become the new user. This must be a descendant of the owning\n+ * client, the owning client itself, or the special value MC_CMD_CLIENT_ID_SELF\n+ * which is synonymous with the owning client.\n+ */\n+#define\tMC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4\n+#define\tMC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4\n+\n+/* MC_CMD_SET_VI_USER_OUT msgresponse */\n+#define\tMC_CMD_SET_VI_USER_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES\n+ * A device reports a set of MAC addresses for each client to use, known as the\n+ * \"permanent MAC addresses\". Those MAC addresses are provided by the client's\n+ * administrator, e.g. via MC_CMD_SET_CLIENT_MAC_ADDRESSES, and are intended as\n+ * a hint to that client which MAC address its administrator would like to use\n+ * to identity itself. This API exists solely to allow communication of MAC\n+ * address from administrator to adminstree, and has no inherent interaction\n+ * with switching within the device. There is no guarantee that a client will\n+ * be able to send traffic with a source MAC address taken from the list of MAC\n+ * address reported, nor is there a guarantee that a client will be able to\n+ * resource traffic with a destination MAC taken from the list of MAC\n+ * addresses. Likewise, there is no guarantee that a client will not be able to\n+ * use a MAC address not present in the list. Restrictions on switching are\n+ * controlled either through the EVB API if operating in EVB mode, or via MAE\n+ * rules if host software is directly managing the MAE. In order to allow\n+ * tenants to use this API whilst a provider is using the EVB API, the MAC\n+ * addresses reported by MC_CMD_GET_CLIENT_MAC_ADDRESSES will be augmented with\n+ * any MAC addresses associated with the vPort assigned to the caller. In order\n+ * to allow tenants to use the EVB API whilst a provider is using this API, if\n+ * a client queries the MAC addresses for a vPort using the host_evb_port_id\n+ * EVB_PORT_ASSIGNED, that list of MAC addresses will be augmented with the MAC\n+ * addresses assigned to the calling client. This query can either be explicit\n+ * (i.e. MC_CMD_VPORT_GET_MAC_ADDRESSES) or implicit (e.g. creation of a\n+ * vAdaptor with a NULL/automatic MAC address). Changing the MAC address on a\n+ * vAdaptor only affects VNIC steering filters; it has no effect on the MAC\n+ * addresses assigned to the vAdaptor's owner. VirtIO clients behave as EVB\n+ * clients. On VirtIO device reset, a vAdaptor is created with an automatic MAC\n+ * address. Querying the VirtIO device's MAC address queries the underlying\n+ * vAdaptor's MAC address. Setting the VirtIO device's MAC address sets the\n+ * underlying vAdaptor's MAC addresses.\n+ */\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c4\n+#undef\tMC_CMD_0x1c4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN msgrequest */\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4\n+/* A handle for the client for whom MAC address should be obtained. Use\n+ * CLIENT_HANDLE_SELF to obtain the MAC addresses assigned to the calling\n+ * client.\n+ */\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4\n+\n+/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT msgresponse */\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX 252\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)\n+/* An array of MAC addresses assigned to the client. */\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_LEN 6\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM 42\n+#define\tMC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM_MCDI2 170\n+\n+\n+/***********************************/\n+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES\n+ * Set the permanent MAC addresses for a client. The caller must by an\n+ * administrator of the target client. See MC_CMD_GET_CLIENT_MAC_ADDRESSES for\n+ * additional detail.\n+ */\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_MSGSET 0x1c5\n+#undef\tMC_CMD_0x1c5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN msgrequest */\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX 250\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX_MCDI2 1018\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)\n+/* A handle for the client for whom MAC addresses should be set */\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4\n+/* An array of MAC addresses to assign to the client. */\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_LEN 6\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM 41\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM_MCDI2 169\n+\n+/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT msgresponse */\n+#define\tMC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_BOARD_ATTR\n+ * Retrieve physical build-level board attributes as configured at\n+ * manufacturing stage. Fields originate from EEPROM and per-platform constants\n+ * in firmware. Fields are used in development to identify/ differentiate\n+ * boards based on build levels/parameters, and also in manufacturing to cross\n+ * check \"what was programmed in manufacturing\" is same as \"what firmware\n+ * thinks has been programmed\" as there are two layers to translation within\n+ * firmware before the attributes reach this MCDI handler. Some parameters are\n+ * retrieved as part of other commands and therefore not replicated here. See\n+ * GET_VERSION_OUT.\n+ */\n+#define\tMC_CMD_GET_BOARD_ATTR 0x1c6\n+#define\tMC_CMD_GET_BOARD_ATTR_MSGSET 0x1c6\n+#undef\tMC_CMD_0x1c6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_BOARD_ATTR_IN msgrequest */\n+#define\tMC_CMD_GET_BOARD_ATTR_IN_LEN 0\n+\n+/* MC_CMD_GET_BOARD_ATTR_OUT msgresponse */\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_LEN 16\n+/* Defines board capabilities and validity of attributes returned in this\n+ * response-message.\n+ */\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_WIDTH 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_LBN 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_WIDTH 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_LBN 2\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_WIDTH 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_WIDTH 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_LBN 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_WIDTH 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_LBN 16\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_WIDTH 8\n+/* enum: The FPGA voltage on the adapter can be set to low */\n+#define\tMC_CMD_FPGA_VOLTAGE_LOW 0x0\n+/* enum: The FPGA voltage on the adapter can be set to regular */\n+#define\tMC_CMD_FPGA_VOLTAGE_REG 0x1\n+/* enum: The FPGA voltage on the adapter can be set to high */\n+#define\tMC_CMD_FPGA_VOLTAGE_HIGH 0x2\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_LBN 24\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_WIDTH 8\n+/* An array of cage types on the board */\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_OFST 8\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_LEN 1\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_NUM 8\n+/* enum: The cages are not known */\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0\n+/* enum: The cages are SFP/SFP+ */\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1\n+/* enum: The cages are QSFP/QSFP+ */\n+#define\tMC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_SOC_STATE\n+ * Retrieve current state of the System-on-Chip. This command is valid when\n+ * MC_CMD_GET_BOARD_ATTR:HAS_SOC is set.\n+ */\n+#define\tMC_CMD_GET_SOC_STATE 0x1c7\n+#define\tMC_CMD_GET_SOC_STATE_MSGSET 0x1c7\n+#undef\tMC_CMD_0x1c7_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c7_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_SOC_STATE_IN msgrequest */\n+#define\tMC_CMD_GET_SOC_STATE_IN_LEN 0\n+\n+/* MC_CMD_GET_SOC_STATE_OUT msgresponse */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_LEN 12\n+/* Status flags for the SoC */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_WIDTH 1\n+#define\tMC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0\n+#define\tMC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_LBN 1\n+#define\tMC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_WIDTH 1\n+#define\tMC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0\n+#define\tMC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_LBN 2\n+#define\tMC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_WIDTH 1\n+/* Status fields for the SoC */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4\n+#define\tMC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4\n+#define\tMC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4\n+#define\tMC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0\n+#define\tMC_CMD_GET_SOC_STATE_OUT_RUN_STATE_WIDTH 8\n+/* enum: Power on (set by SUC on power up) */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0\n+/* enum: Running bootloader */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1\n+/* enum: Bootloader has started OS. OS is booting */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2\n+/* enum: OS is running */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3\n+/* enum: Maintenance OS is running */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4\n+/* Number of SoC resets since power on */\n+#define\tMC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_OFST 8\n+#define\tMC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_CHECK_SCHEDULER_CREDITS\n+ * For debugging purposes. For each source and destination node in the hardware\n+ * schedulers, check whether the number of credits is as it should be. This\n+ * should only be used when the NIC is idle, because collection is not atomic\n+ * and because the expected credit counts are only meaningful when no traffic\n+ * is flowing.\n+ */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_MSGSET 0x1c8\n+#undef\tMC_CMD_0x1c8_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c8_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_CHECK_SCHEDULER_CREDITS_IN msgrequest */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_LEN 8\n+/* Flags for the request */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1\n+/* If there are too many results to fit into an MCDI response, they're split\n+ * into pages. This field specifies which (0-indexed) page to request. A\n+ * request with PAGE=0 will snapshot the results, and subsequent requests with\n+ * PAGE>0 will return data from the most recent snapshot. The GENERATION field\n+ * in the response allows callers to verify that all responses correspond to\n+ * the same snapshot.\n+ */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4\n+\n+/* MC_CMD_CHECK_SCHEDULER_CREDITS_OUT msgresponse */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMIN 16\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX 240\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX_MCDI2 1008\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LEN(num) (16+16*(num))\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)\n+/* The total number of results (across all pages). */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4\n+/* The number of pages that the response is split across. */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4\n+/* The number of results in this response. */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_OFST 8\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4\n+/* Result generation count. Incremented any time a request is made with PAGE=0.\n+ */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_OFST 12\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4\n+/* The results, as an array of SCHED_CREDIT_CHECK_RESULT structures. */\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_OFST 16\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_LEN 16\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14\n+#define\tMC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62\n \n /* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are\n  * defined in SF-120734-TC with more information in SF-122717-TC.\n@@ -24839,6 +27140,7 @@\n  * Get a list of the virtio features supported by the device.\n  */\n #define\tMC_CMD_VIRTIO_GET_FEATURES 0x168\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_MSGSET 0x168\n #undef\tMC_CMD_0x168_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24867,7 +27169,13 @@\n #define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0\n #define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8\n #define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_WIDTH 32\n #define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LBN 32\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_WIDTH 32\n \n \n /***********************************/\n@@ -24877,6 +27185,7 @@\n  * the driver fails to request a feature which the device requires.\n  */\n #define\tMC_CMD_VIRTIO_TEST_FEATURES 0x169\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_MSGSET 0x169\n #undef\tMC_CMD_0x169_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24898,7 +27207,13 @@\n #define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8\n #define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8\n #define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LBN 64\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_WIDTH 32\n #define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LBN 96\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_WIDTH 32\n \n /* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */\n #define\tMC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0\n@@ -24912,6 +27227,7 @@\n  * invalid.\n  */\n #define\tMC_CMD_VIRTIO_INIT_QUEUE 0x16a\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_MSGSET 0x16a\n #undef\tMC_CMD_0x16a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -24956,17 +27272,35 @@\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LBN 128\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_WIDTH 32\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LBN 160\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_WIDTH 32\n /* Address of the available ring in the virtqueue. */\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LBN 192\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_WIDTH 32\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LBN 224\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_WIDTH 32\n /* Address of the used ring in the virtqueue. */\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LBN 256\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_WIDTH 32\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LBN 288\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_WIDTH 32\n /* PASID to use on PCIe transactions involving this queue. Ignored if the\n  * USE_PASID flag is not set.\n  */\n@@ -24990,7 +27324,13 @@\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LBN 384\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_WIDTH 32\n #define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LBN 416\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_WIDTH 32\n /*            Enum values, see field(s): */\n /*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */\n /* The initial producer index for this queue's used ring. If this queue is\n@@ -25023,6 +27363,7 @@\n  * Destroy a virtio virtqueue\n  */\n #define\tMC_CMD_VIRTIO_FINI_QUEUE 0x16b\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_MSGSET 0x16b\n #undef\tMC_CMD_0x16b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -25063,6 +27404,7 @@\n  * queue(s) to be allocated.\n  */\n #define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_MSGSET 0x16c\n #undef\tMC_CMD_0x16c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -25132,12 +27474,18 @@\n #define\tPCIE_FUNCTION_VF_NULL 0xffff\n #define\tPCIE_FUNCTION_VF_LBN 16\n #define\tPCIE_FUNCTION_VF_WIDTH 16\n-/* PCIe interface of the function */\n+/* PCIe interface of the function. Values should be taken from the\n+ * PCIE_INTERFACE enum\n+ */\n #define\tPCIE_FUNCTION_INTF_OFST 4\n #define\tPCIE_FUNCTION_INTF_LEN 4\n-/* enum: Host PCIe interface */\n+/* enum: Host PCIe interface. (Alias for HOST_PRIMARY, provided for backwards\n+ * compatibility)\n+ */\n #define\tPCIE_FUNCTION_INTF_HOST 0x0\n-/* enum: Application Processor interface */\n+/* enum: Application Processor interface (alias for NIC_EMBEDDED, provided for\n+ * backwards compatibility)\n+ */\n #define\tPCIE_FUNCTION_INTF_AP 0x1\n #define\tPCIE_FUNCTION_INTF_LBN 32\n #define\tPCIE_FUNCTION_INTF_WIDTH 32\n@@ -25157,6 +27505,7 @@\n  * MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE 0x172\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_MSGSET 0x172\n #undef\tMC_CMD_0x172_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25170,7 +27519,19 @@\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_WIDTH 32\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LBN 32\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_WIDTH 32\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_LEN 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_OFST 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_VF_LEN 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4\n /* The personality to set. The meanings of the personalities are defined in\n  * SF-120734-TC with more information in SF-122717-TC. At present, we only\n  * support proxying for VIRTIO_BLK\n@@ -25194,7 +27555,19 @@\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LBN 32\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_WIDTH 32\n #define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LBN 64\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_WIDTH 32\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_LEN 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_OFST 6\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_VF_LEN 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_OFST 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4\n \n \n /***********************************/\n@@ -25205,6 +27578,7 @@\n  * ownership is released.\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_DESTROY 0x173\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_MSGSET 0x173\n #undef\tMC_CMD_0x173_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25235,7 +27609,13 @@\n #define\tVIRTIO_BLK_CONFIG_FEATURES_OFST 0\n #define\tVIRTIO_BLK_CONFIG_FEATURES_LEN 8\n #define\tVIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_LO_WIDTH 32\n #define\tVIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_HI_LBN 32\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_HI_WIDTH 32\n #define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0\n #define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0\n #define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1\n@@ -25308,7 +27688,13 @@\n #define\tVIRTIO_BLK_CONFIG_CAPACITY_OFST 8\n #define\tVIRTIO_BLK_CONFIG_CAPACITY_LEN 8\n #define\tVIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_LO_LBN 64\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_LO_WIDTH 32\n #define\tVIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_HI_LBN 96\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_HI_WIDTH 32\n #define\tVIRTIO_BLK_CONFIG_CAPACITY_LBN 64\n #define\tVIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64\n /* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is\n@@ -25445,6 +27831,7 @@\n  * not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_MSGSET 0x174\n #undef\tMC_CMD_0x174_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25485,6 +27872,7 @@\n  * delivered to callers MCDI event queue.\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_COMMIT 0x175\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_MSGSET 0x175\n #undef\tMC_CMD_0x175_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25518,6 +27906,7 @@\n  * cycle. Returns ENODEV if no function with given label exists.\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN 0x176\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_MSGSET 0x176\n #undef\tMC_CMD_0x176_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25543,7 +27932,19 @@\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LBN 32\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_WIDTH 32\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LBN 64\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_WIDTH 32\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_LEN 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_OFST 6\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_VF_LEN 2\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_OFST 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4\n /* Function personality */\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12\n #define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4\n@@ -25588,6 +27989,7 @@\n  * error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1\n+#define\tMC_CMD_DESC_PROXY_FUNC_CLOSE_MSGSET 0x1a1\n #undef\tMC_CMD_0x1a1_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25607,9 +28009,27 @@\n #define\tDESC_PROXY_FUNC_MAP_FUNC_OFST 0\n #define\tDESC_PROXY_FUNC_MAP_FUNC_LEN 8\n #define\tDESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_LO_WIDTH 32\n #define\tDESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_HI_LBN 32\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_HI_WIDTH 32\n #define\tDESC_PROXY_FUNC_MAP_FUNC_LBN 0\n #define\tDESC_PROXY_FUNC_MAP_FUNC_WIDTH 64\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_PF_LEN 2\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_PF_WIDTH 16\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_VF_OFST 2\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_VF_LEN 2\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_VF_LBN 16\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_VF_WIDTH 16\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_INTF_LBN 32\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_INTF_WIDTH 32\n /* Function personality */\n #define\tDESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8\n #define\tDESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4\n@@ -25631,6 +28051,7 @@\n  * Enumerate existing descriptor proxy functions\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_ENUM 0x177\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_MSGSET 0x177\n #undef\tMC_CMD_0x177_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25670,6 +28091,7 @@\n  * function.\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_ENABLE 0x178\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_MSGSET 0x178\n #undef\tMC_CMD_0x178_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25702,6 +28124,7 @@\n  * Disable descriptor proxying for function\n  */\n #define\tMC_CMD_DESC_PROXY_FUNC_DISABLE 0x179\n+#define\tMC_CMD_DESC_PROXY_FUNC_DISABLE_MSGSET 0x179\n #undef\tMC_CMD_0x179_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25725,6 +28148,7 @@\n  * descriptors.\n  */\n #define\tMC_CMD_GET_ADDR_SPC_ID 0x1a0\n+#define\tMC_CMD_GET_ADDR_SPC_ID_MSGSET 0x1a0\n #undef\tMC_CMD_0x1a0_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n@@ -25769,7 +28193,19 @@\n #define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4\n #define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8\n #define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LBN 32\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_WIDTH 32\n #define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LBN 64\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_WIDTH 32\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_LEN 2\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_OFST 6\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_VF_LEN 2\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_OFST 8\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4\n /* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */\n #define\tMC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12\n #define\tMC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4\n@@ -25789,7 +28225,72 @@\n #define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0\n #define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8\n #define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_WIDTH 32\n #define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LBN 32\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_CLIENT_HANDLE\n+ * Obtain a handle for a client given a description of that client. N.B. this\n+ * command is subject to change given the open discussion about how PCIe\n+ * functions should be referenced on an iEP (integrated endpoint: functions\n+ * span multiple buses) and multihost (multiple PCIe interfaces) system.\n+ */\n+#define\tMC_CMD_GET_CLIENT_HANDLE 0x1c3\n+#define\tMC_CMD_GET_CLIENT_HANDLE_MSGSET 0x1c3\n+#undef\tMC_CMD_0x1c3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1c3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_CLIENT_HANDLE_IN msgrequest */\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_LEN 12\n+/* Type of client to get a client handle for */\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4\n+/* enum: Obtain a client handle for a PCIe function-type client. */\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0\n+/* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -\n+ * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -\n+ * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or\n+ * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer\n+ * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a\n+ * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF\n+ * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named\n+ * interface where ... refers to a small integer for the VF/PF fields, and to\n+ * values from the PCIE_INTERFACE enum for for the INTF field. It's only\n+ * meaningful to use INTF=CALLER within a structure that's an argument to\n+ * MC_CMD_DEVEL_GET_CLIENT_HANDLE.\n+ */\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LEN 8\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LBN 32\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_WIDTH 32\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_OFST 8\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LBN 64\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_WIDTH 32\n+/* enum: NULL value for the INTF field of struct PCIE_FUNCTION. Provided for\n+ * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER.\n+ */\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_LEN 2\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_OFST 8\n+#define\tMC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4\n+\n+/* MC_CMD_GET_CLIENT_HANDLE_OUT msgresponse */\n+#define\tMC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4\n+#define\tMC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0\n+#define\tMC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4\n \n /* MAE_FIELD_FLAGS structuredef */\n #define\tMAE_FIELD_FLAGS_LEN 4\n@@ -25937,6 +28438,40 @@\n #define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1\n #define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096\n #define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_OFST 138\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_OFST 138\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_OFST 138\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_OFST 138\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_LBN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LBN 1104\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_OFST 138\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_LBN 1104\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_OFST 139\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_OFST 139\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_OFST 139\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_OFST 139\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_LBN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LBN 1112\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_OFST 139\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LBN 1112\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_WIDTH 8\n #define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140\n #define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4\n #define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120\n@@ -26623,9 +29158,24 @@\n #define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344\n #define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3\n #define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1\n-#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_OFST 344\n-#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_LBN 4\n-#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_WIDTH 28\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_LBN 5\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_LBN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_LBN 7\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_LBN 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_LBN 9\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1\n #define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752\n #define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32\n #define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348\n@@ -26707,16 +29257,34 @@\n #define\tMAE_MPORT_SELECTOR_TYPE_WIDTH 8\n /* enum: The MPORT connected to a given physical port */\n #define\tMAE_MPORT_SELECTOR_TYPE_PPORT 0x2\n-/* enum: The MPORT assigned to a given PCIe function */\n+/* enum: The MPORT assigned to a given PCIe function. Deprecated in favour of\n+ * MH_FUNC.\n+ */\n #define\tMAE_MPORT_SELECTOR_TYPE_FUNC 0x3\n /* enum: An mport_id */\n #define\tMAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4\n+/* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)\n+ */\n+#define\tMAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5\n+/* enum: This is guaranteed never to be a valid selector type */\n+#define\tMAE_MPORT_SELECTOR_TYPE_INVALID 0xff\n #define\tMAE_MPORT_SELECTOR_MPORT_ID_OFST 0\n #define\tMAE_MPORT_SELECTOR_MPORT_ID_LBN 0\n #define\tMAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24\n #define\tMAE_MPORT_SELECTOR_PPORT_ID_OFST 0\n #define\tMAE_MPORT_SELECTOR_PPORT_ID_LBN 0\n #define\tMAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4\n+#define\tMAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0\n+#define\tMAE_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20\n+#define\tMAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4\n+#define\tMAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */\n+#define\tMAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */\n+/* enum: Deprecated, use CALLER_INTF instead. */\n+#define\tMAE_MPORT_SELECTOR_CALLER 0xf\n+#define\tMAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */\n+#define\tMAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0\n+#define\tMAE_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16\n+#define\tMAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4\n #define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0\n #define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16\n #define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8\n@@ -26737,15 +29305,56 @@\n  * function.\n  */\n #define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff\n+/* enum: Same as PF_ID_CALLER, but for use in the smaller MH_PF_ID field. Only\n+ * valid if FUNC_INTF_ID is CALLER.\n+ */\n+#define\tMAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf\n #define\tMAE_MPORT_SELECTOR_FLAT_LBN 0\n #define\tMAE_MPORT_SELECTOR_FLAT_WIDTH 32\n \n+/* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or\n+ * virtual network port by MAE port and link end\n+ */\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_LEN 8\n+/* The MAE MPORT of interest */\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_WIDTH 32\n+/* Which end of the link identified by MPORT to consider */\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MAE_MPORT_END */\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_LINK_END_LBN 32\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_LINK_END_WIDTH 32\n+/* A field for accessing the endpoint selector as a collection of bits */\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_LEN 8\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_WIDTH 32\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LBN 32\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_WIDTH 32\n+/* enum: Set FLAT to this value to obtain backward-compatible behaviour in\n+ * commands that have been extended to take a MAE_LINK_ENDPOINT_SELECTOR\n+ * argument. New commands that are designed to take such an argument from the\n+ * start will not support this.\n+ */\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0\n+#define\tMAE_LINK_ENDPOINT_SELECTOR_FLAT_WIDTH 64\n+\n \n /***********************************/\n /* MC_CMD_MAE_GET_CAPS\n  * Describes capabilities of the MAE (Match-Action Engine)\n  */\n #define\tMC_CMD_MAE_GET_CAPS 0x140\n+#define\tMC_CMD_MAE_GET_CAPS_MSGSET 0x140\n #undef\tMC_CMD_0x140_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -26772,6 +29381,9 @@\n #define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4\n #define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2\n #define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_LBN 3\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1\n /* The total number of counters available to allocate. */\n #define\tMC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8\n #define\tMC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4\n@@ -26823,6 +29435,7 @@\n  * Get a level of support for match fields when used in match-action rules\n  */\n #define\tMC_CMD_MAE_GET_AR_CAPS 0x141\n+#define\tMC_CMD_MAE_GET_AR_CAPS_MSGSET 0x141\n #undef\tMC_CMD_0x141_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -26855,6 +29468,7 @@\n  * Get a level of support for fields used in outer rule keys.\n  */\n #define\tMC_CMD_MAE_GET_OR_CAPS 0x142\n+#define\tMC_CMD_MAE_GET_OR_CAPS_MSGSET 0x142\n #undef\tMC_CMD_0x142_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -26885,6 +29499,7 @@\n  * Rules.\n  */\n #define\tMC_CMD_MAE_COUNTER_ALLOC 0x143\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_MSGSET 0x143\n #undef\tMC_CMD_0x143_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -26928,6 +29543,7 @@\n  * Free match-action-engine counters\n  */\n #define\tMC_CMD_MAE_COUNTER_FREE 0x144\n+#define\tMC_CMD_MAE_COUNTER_FREE_MSGSET 0x144\n #undef\tMC_CMD_0x144_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -26995,6 +29611,7 @@\n  * delivering packets to the current queue first.\n  */\n #define\tMC_CMD_MAE_COUNTERS_STREAM_START 0x151\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_MSGSET 0x151\n #undef\tMC_CMD_0x151_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27031,6 +29648,7 @@\n  * Stop streaming counter values to the specified RxQ.\n  */\n #define\tMC_CMD_MAE_COUNTERS_STREAM_STOP 0x152\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_MSGSET 0x152\n #undef\tMC_CMD_0x152_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27060,6 +29678,7 @@\n  * MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.\n  */\n #define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_MSGSET 0x153\n #undef\tMC_CMD_0x153_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27076,9 +29695,15 @@\n \n /***********************************/\n /* MC_CMD_MAE_ENCAP_HEADER_ALLOC\n- * Allocate encap action metadata\n+ * Allocate an encapsulation header to be used in an Action Rule response. The\n+ * header must be constructed as a valid packet with 0-length payload.\n+ * Specifically, the L3/L4 lengths & checksums will only be incrementally fixed\n+ * by the NIC, rather than recomputed entirely. Currently only IPv4, IPv6 and\n+ * UDP are supported. If the maximum number of headers have already been\n+ * allocated then the command will fail with MC_CMD_ERR_ENOSPC.\n  */\n #define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_MSGSET 0x148\n #undef\tMC_CMD_0x148_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27109,9 +29734,10 @@\n \n /***********************************/\n /* MC_CMD_MAE_ENCAP_HEADER_UPDATE\n- * Update encap action metadata\n+ * Update encap action metadata. See comments for MAE_ENCAP_HEADER_ALLOC.\n  */\n #define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_MSGSET 0x149\n #undef\tMC_CMD_0x149_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27141,6 +29767,7 @@\n  * Free encap action metadata\n  */\n #define\tMC_CMD_MAE_ENCAP_HEADER_FREE 0x14a\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_MSGSET 0x14a\n #undef\tMC_CMD_0x14a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27176,9 +29803,12 @@\n /* MC_CMD_MAE_MAC_ADDR_ALLOC\n  * Allocate MAC address. Hardware implementations have MAC addresses programmed\n  * into an indirection table, and clients should take care not to allocate the\n- * same MAC address twice (but instead reuse its ID).\n+ * same MAC address twice (but instead reuse its ID). If the maximum number of\n+ * MAC addresses have already been allocated then the command will fail with\n+ * MC_CMD_ERR_ENOSPC.\n  */\n #define\tMC_CMD_MAE_MAC_ADDR_ALLOC 0x15e\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_MSGSET 0x15e\n #undef\tMC_CMD_0x15e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27204,6 +29834,7 @@\n  * Free MAC address.\n  */\n #define\tMC_CMD_MAE_MAC_ADDR_FREE 0x15f\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_MSGSET 0x15f\n #undef\tMC_CMD_0x15f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27238,9 +29869,12 @@\n /***********************************/\n /* MC_CMD_MAE_ACTION_SET_ALLOC\n  * Allocate an action set, which can be referenced either in response to an\n- * Action Rule, or as part of an Action Set List.\n+ * Action Rule, or as part of an Action Set List. If the maxmimum number of\n+ * action sets have already been allocated then the command will fail with\n+ * MC_CMD_ERR_ENOSPC.\n  */\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC 0x14d\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_MSGSET 0x14d\n #undef\tMC_CMD_0x14d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27267,6 +29901,15 @@\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_LBN 12\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_LBN 13\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1\n /* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2\n@@ -27313,8 +29956,135 @@\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4\n \n+/* MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN msgrequest: Only supported if\n+ * MAE_ACTION_SET_ALLOC_V2_SUPPORTED is advertised in\n+ * MC_CMD_GET_CAPABILITIES_V7_OUT.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LEN 51\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_WIDTH 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_WIDTH 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_LBN 8\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_LBN 9\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_LBN 10\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_LBN 11\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_LBN 12\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_LBN 13\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1\n+/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2\n+/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_OFST 6\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_LEN 2\n+/* If VLAN_PUSH == 2, inner TCI value to be inserted. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_OFST 8\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_LEN 2\n+/* If VLAN_PUSH == 2, inner TPID value to be inserted. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_OFST 10\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_LEN 2\n+/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_OFST 12\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4\n+/* Set to ENCAP_HEADER_ID_NULL to request no encap action */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_OFST 16\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4\n+/* An m-port selector identifying the m-port that the modified packet should be\n+ * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the\n+ * packet.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4\n+/* Allows an action set to trigger several counter updates. Set to\n+ * COUNTER_LIST_ID_NULL to request no counter action.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4\n+/* If a driver only wished to update one counter within this action set, then\n+ * it can supply a COUNTER_ID instead of allocating a single-element counter\n+ * list. This field should be set to COUNTER_ID_NULL if this behaviour is not\n+ * required. It is not valid to supply a non-NULL value for both\n+ * COUNTER_LIST_ID and COUNTER_ID.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4\n+/* Set to MAC_ID_NULL to request no source MAC replacement. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_OFST 36\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4\n+/* Set to MAC_ID_NULL to request no destination MAC replacement. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_OFST 40\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4\n+/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_OFST 44\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4\n+/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits\n+ * within IPv4 and IPv6 headers.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_OFST 48\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_LEN 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_OFST 48\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_OFST 48\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_OFST 48\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_LBN 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_OFST 48\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_LBN 3\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_WIDTH 6\n+/* Actions for modifying the Explicit Congestion Notification (ECN) bits within\n+ * IPv4 and IPv6 headers.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_LBN 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_LBN 3\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_WIDTH 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_LBN 5\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1\n+\n /* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4\n+/* The MSB of the AS_ID is guaranteed to be clear if the ID is not\n+ * ACTION_SET_ID_NULL. This allows an AS_ID to be distinguished from an ASL_ID\n+ * returned from MC_CMD_MAE_ACTION_SET_LIST_ALLOC.\n+ */\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0\n #define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4\n /* enum: An action set ID that is guaranteed never to represent an action set\n@@ -27326,6 +30096,7 @@\n /* MC_CMD_MAE_ACTION_SET_FREE\n  */\n #define\tMC_CMD_MAE_ACTION_SET_FREE 0x14e\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_MSGSET 0x14e\n #undef\tMC_CMD_0x14e_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27361,9 +30132,12 @@\n /* MC_CMD_MAE_ACTION_SET_LIST_ALLOC\n  * Allocate an action set list (ASL) that can be referenced by an ID. The ASL\n  * ID can be used when inserting an action rule, so that for each packet\n- * matching the rule every action set in the list is applied.\n+ * matching the rule every action set in the list is applied. If the maximum\n+ * number of ASLs have already been allocated then the command will fail with\n+ * MC_CMD_ERR_ENOSPC.\n  */\n #define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_MSGSET 0x14f\n #undef\tMC_CMD_0x14f_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27394,6 +30168,9 @@\n \n /* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */\n #define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4\n+/* The MSB of the ASL_ID is guaranteed to be set. This allows an ASL_ID to be\n+ * distinguished from an AS_ID returned from MC_CMD_MAE_ACTION_SET_ALLOC.\n+ */\n #define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0\n #define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4\n /* enum: An action set list ID that is guaranteed never to represent an action\n@@ -27407,6 +30184,7 @@\n  * Free match-action-engine redirect_lists\n  */\n #define\tMC_CMD_MAE_ACTION_SET_LIST_FREE 0x150\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_MSGSET 0x150\n #undef\tMC_CMD_0x150_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27441,9 +30219,11 @@\n /***********************************/\n /* MC_CMD_MAE_OUTER_RULE_INSERT\n  * Inserts an Outer Rule, which controls encapsulation parsing, and may\n- * influence the Lookup Sequence.\n+ * influence the Lookup Sequence. If the maximum number of rules have already\n+ * been inserted then the command will fail with MC_CMD_ERR_ENOSPC.\n  */\n #define\tMC_CMD_MAE_OUTER_RULE_INSERT 0x15a\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_MSGSET 0x15a\n #undef\tMC_CMD_0x15a_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27504,6 +30284,7 @@\n /* MC_CMD_MAE_OUTER_RULE_REMOVE\n  */\n #define\tMC_CMD_MAE_OUTER_RULE_REMOVE 0x15b\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_MSGSET 0x15b\n #undef\tMC_CMD_0x15b_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27583,9 +30364,11 @@\n /* MC_CMD_MAE_ACTION_RULE_INSERT\n  * Insert a rule specify that packets matching a filter be processed according\n  * to a previous allocated action. Masks can be set as indicated by\n- * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES.\n+ * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES. If the maximum number of rules have\n+ * already been inserted then the command will fail with MC_CMD_ERR_ENOSPC.\n  */\n #define\tMC_CMD_MAE_ACTION_RULE_INSERT 0x15c\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_MSGSET 0x15c\n #undef\tMC_CMD_0x15c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27627,6 +30410,7 @@\n  * ENOTSUP, in which case the driver should DELETE/INSERT.\n  */\n #define\tMC_CMD_MAE_ACTION_RULE_UPDATE 0x15d\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_MSGSET 0x15d\n #undef\tMC_CMD_0x15d_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27648,6 +30432,7 @@\n /* MC_CMD_MAE_ACTION_RULE_DELETE\n  */\n #define\tMC_CMD_MAE_ACTION_RULE_DELETE 0x155\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_MSGSET 0x155\n #undef\tMC_CMD_0x155_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27684,6 +30469,7 @@\n  * Return the m-port corresponding to a selector.\n  */\n #define\tMC_CMD_MAE_MPORT_LOOKUP 0x160\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_MSGSET 0x160\n #undef\tMC_CMD_0x160_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -27705,6 +30491,7 @@\n  * match or delivery argument.\n  */\n #define\tMC_CMD_MAE_MPORT_ALLOC 0x163\n+#define\tMC_CMD_MAE_MPORT_ALLOC_MSGSET 0x163\n #undef\tMC_CMD_0x163_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27812,6 +30599,7 @@\n  * Free a m-port which was previously allocated by the driver.\n  */\n #define\tMC_CMD_MAE_MPORT_FREE 0x164\n+#define\tMC_CMD_MAE_MPORT_FREE_MSGSET 0x164\n #undef\tMC_CMD_0x164_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE\n@@ -27847,6 +30635,9 @@\n #define\tMAE_MPORT_DESC_CAN_DELETE_OFST 8\n #define\tMAE_MPORT_DESC_CAN_DELETE_LBN 2\n #define\tMAE_MPORT_DESC_CAN_DELETE_WIDTH 1\n+#define\tMAE_MPORT_DESC_IS_ZOMBIE_OFST 8\n+#define\tMAE_MPORT_DESC_IS_ZOMBIE_LBN 3\n+#define\tMAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1\n #define\tMAE_MPORT_DESC_CALLER_FLAGS_LBN 64\n #define\tMAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32\n /* Not the ideal name; it's really the type of thing connected to the m-port */\n@@ -27869,7 +30660,13 @@\n #define\tMAE_MPORT_DESC_RESERVED_OFST 32\n #define\tMAE_MPORT_DESC_RESERVED_LEN 8\n #define\tMAE_MPORT_DESC_RESERVED_LO_OFST 32\n+#define\tMAE_MPORT_DESC_RESERVED_LO_LEN 4\n+#define\tMAE_MPORT_DESC_RESERVED_LO_LBN 256\n+#define\tMAE_MPORT_DESC_RESERVED_LO_WIDTH 32\n #define\tMAE_MPORT_DESC_RESERVED_HI_OFST 36\n+#define\tMAE_MPORT_DESC_RESERVED_HI_LEN 4\n+#define\tMAE_MPORT_DESC_RESERVED_HI_LBN 288\n+#define\tMAE_MPORT_DESC_RESERVED_HI_WIDTH 32\n #define\tMAE_MPORT_DESC_RESERVED_LBN 256\n #define\tMAE_MPORT_DESC_RESERVED_WIDTH 64\n /* Logical port index. Only valid when type NET Port. */\n@@ -27916,8 +30713,11 @@\n \n /***********************************/\n /* MC_CMD_MAE_MPORT_ENUMERATE\n+ * Deprecated in favour of MAE_MPORT_READ_JOURNAL. Support for this command\n+ * will be removed at some future point.\n  */\n #define\tMC_CMD_MAE_MPORT_ENUMERATE 0x17c\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_MSGSET 0x17c\n #undef\tMC_CMD_0x17c_PRIVILEGE_CTG\n \n #define\tMC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n@@ -27945,4 +30745,50 @@\n #define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244\n #define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012\n \n+\n+/***********************************/\n+/* MC_CMD_MAE_MPORT_READ_JOURNAL\n+ * Firmware maintains a per-client journal of mport creations and deletions.\n+ * This journal is clear-on-read, i.e. repeated calls of this command will\n+ * drain the buffer. Whenever the caller resets its function via FLR or\n+ * MC_CMD_ENTITY_RESET, the journal is regenerated from a blank start.\n+ */\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL 0x147\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_MSGSET 0x147\n+#undef\tMC_CMD_0x147_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x147_PRIVILEGE_CTG SRIOV_CTG_MAE\n+\n+/* MC_CMD_MAE_MPORT_READ_JOURNAL_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4\n+/* Any unused flags are reserved and must be set to zero. */\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4\n+\n+/* MC_CMD_MAE_MPORT_READ_JOURNAL_OUT msgresponse */\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMIN 12\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX 252\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)\n+/* Any unused flags are reserved and must be ignored. */\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_OFST 8\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4\n+/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may\n+ * grow in future version of this command. Drivers should use a stride of\n+ * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.\n+ */\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_OFST 12\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240\n+#define\tMC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008\n+\n #endif /* _SIENA_MC_DRIVER_PCOL_H */\ndiff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h\nindex f7c89fabc..c45f678c2 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h\n@@ -6,7 +6,7 @@\n \n /*\n  * This file is automatically generated. DO NOT EDIT IT.\n- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and\n+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and\n  * rebuild this file with \"make mcdi_headers_v5\".\n  */\n \n@@ -20,6 +20,7 @@\n  * Perform an FC operation\n  */\n #define\tMC_CMD_FC 0x9\n+#define\tMC_CMD_FC_MSGSET 0x9\n \n /* MC_CMD_FC_IN msgrequest */\n #define\tMC_CMD_FC_IN_LEN 4\n@@ -212,7 +213,13 @@\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LBN 128\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_WIDTH 32\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LBN 160\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_WIDTH 32\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24\n@@ -784,12 +791,24 @@\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LBN 96\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_WIDTH 32\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LBN 128\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_WIDTH 32\n /* AOE address from which to transfer data */\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LBN 160\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_WIDTH 32\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LBN 192\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_WIDTH 32\n /* Length of AOE transfer (total) */\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4\n@@ -916,7 +935,13 @@\n #define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12\n #define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8\n #define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LEN 4\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LBN 96\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_WIDTH 32\n #define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LEN 4\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LBN 128\n+#define\tMC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_WIDTH 32\n #define\tMC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20\n #define\tMC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4\n \n@@ -1016,7 +1041,13 @@\n #define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12\n #define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8\n #define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LEN 4\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LBN 96\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_WIDTH 32\n #define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LEN 4\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LBN 128\n+#define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_WIDTH 32\n /* Port number of PTP packet for which timestamp required */\n #define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20\n #define\tMC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4\n@@ -1320,7 +1351,13 @@\n #define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4\n #define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8\n #define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LBN 32\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LBN 64\n+#define\tMC_CMD_FC_OUT_GET_VERSION_VERSION_HI_WIDTH 32\n \n /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */\n #define\tMC_CMD_FC_OUT_TRC_RX_READ_LEN 8\n@@ -1347,7 +1384,13 @@\n #define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0\n #define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8\n #define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS\n #define\tMC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */\n #define\tMC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */\n@@ -1382,7 +1425,13 @@\n #define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0\n #define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8\n #define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS\n #define\tMC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */\n #define\tMC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */\n@@ -1415,7 +1464,13 @@\n #define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0\n #define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8\n #define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK\n \n /* MC_CMD_FC_OUT_MAC msgresponse */\n@@ -1636,7 +1691,13 @@\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LBN 128\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LBN 160\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28\n@@ -1976,12 +2037,24 @@\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LBN 64\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LBN 96\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_WIDTH 32\n /* Length of address map */\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LBN 128\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LBN 160\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_WIDTH 32\n /* Component information field */\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4\n@@ -1989,7 +2062,13 @@\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LBN 224\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LBN 256\n+#define\tMC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_WIDTH 32\n /* Name of the component */\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36\n #define\tMC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1\n@@ -2132,7 +2211,13 @@\n #define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12\n #define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8\n #define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LBN 96\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LBN 128\n+#define\tMC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_WIDTH 32\n \n /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */\n #define\tMC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)\n@@ -2153,7 +2238,13 @@\n #define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4\n #define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8\n #define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LBN 32\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LBN 64\n+#define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK\n \n /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */\n@@ -2222,12 +2313,24 @@\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LBN 32\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LBN 64\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_WIDTH 32\n /* AOE address from which to transfer data */\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LBN 96\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LBN 128\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_WIDTH 32\n /* Length of AOE transfer (total) */\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4\n@@ -2243,12 +2346,24 @@\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LBN 288\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LBN 320\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_WIDTH 32\n /* When active, end read time */\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LBN 352\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LBN 384\n+#define\tMC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_WIDTH 32\n \n /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */\n #define\tMC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0\n@@ -2263,7 +2378,13 @@\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LBN 32\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LBN 64\n+#define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4\n #define\tMC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16\n@@ -2311,7 +2432,13 @@\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LBN 0\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_WIDTH 32\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LBN 32\n+#define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_WIDTH 32\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31\n #define\tMC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127\n@@ -2391,6 +2518,7 @@\n  * AOE operations on MC\n  */\n #define\tMC_CMD_AOE 0xa\n+#define\tMC_CMD_AOE_MSGSET 0xa\n \n /* MC_CMD_AOE_IN msgrequest */\n #define\tMC_CMD_AOE_IN_LEN 4\n@@ -2580,7 +2708,13 @@\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LEN 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LBN 64\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_WIDTH 32\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LEN 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LBN 96\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_WIDTH 32\n #define\tMC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16\n@@ -3024,7 +3158,13 @@\n #define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0\n #define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8\n #define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LEN 4\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LBN 0\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_WIDTH 32\n #define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LEN 4\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LBN 32\n+#define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_WIDTH 32\n #define\tMC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS\n \n /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */\ndiff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h\nindex be570bc0a..e8fbb6f94 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h\n@@ -6,7 +6,7 @@\n \n /*\n  * This file is automatically generated. DO NOT EDIT IT.\n- * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and\n+ * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and\n  * rebuild this file with \"make mcdi_headers_v5\".\n  *\n  * The version of this file has MCDI strings really used in the libefx.\n",
    "prefixes": [
        "v4",
        "1/3"
    ]
}