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GET /api/patches/93298/?format=api
{ "id": 93298, "url": "https://patches.dpdk.org/api/patches/93298/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210518085058.630072-3-feifei.wang2@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210518085058.630072-3-feifei.wang2@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210518085058.630072-3-feifei.wang2@arm.com", "date": "2021-05-18T08:50:58", "name": "[v3,2/2] net/mlx5: remove unnecessary wmb for Memory Region cache", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4a8756c145c8db4045db427f26dfe4e9bb19bfb4", "submitter": { "id": 1771, "url": "https://patches.dpdk.org/api/people/1771/?format=api", "name": "Feifei Wang", "email": "feifei.wang2@arm.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210518085058.630072-3-feifei.wang2@arm.com/mbox/", "series": [ { "id": 17013, "url": "https://patches.dpdk.org/api/series/17013/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17013", "date": "2021-05-18T08:50:56", "name": "remove wmb for net/mlx", "version": 3, "mbox": "https://patches.dpdk.org/series/17013/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/93298/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/93298/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2DA68A0A02;\n\tTue, 18 May 2021 10:51:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0767441104;\n\tTue, 18 May 2021 10:51:15 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id A345E41107\n for <dev@dpdk.org>; Tue, 18 May 2021 10:51:12 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E4B81063;\n Tue, 18 May 2021 01:51:12 -0700 (PDT)", "from net-x86-dell-8268.shanghai.arm.com\n (net-x86-dell-8268.shanghai.arm.com [10.169.210.111])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ABF813F719;\n Tue, 18 May 2021 01:51:09 -0700 (PDT)" ], "From": "Feifei Wang <feifei.wang2@arm.com>", "To": "Matan Azrad <matan@nvidia.com>, Shahaf Shuler <shahafs@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Cc": "dev@dpdk.org, nd@arm.com, Feifei Wang <feifei.wang2@arm.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>", "Date": "Tue, 18 May 2021 16:50:58 +0800", "Message-Id": "<20210518085058.630072-3-feifei.wang2@arm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210518085058.630072-1-feifei.wang2@arm.com>", "References": "<20210318071840.359957-1-feifei.wang2@arm.com>\n <20210518085058.630072-1-feifei.wang2@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 2/2] net/mlx5: remove unnecessary wmb for\n Memory Region cache", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "'dev_gen' is a variable to trigger all cores to flush their local caches\nonce the global MR cache has been rebuilt.\n\nThis is due to MR cache's R/W lock can maintain synchronization between\nthreads:\n\n1. dev_gen and global cache updating ordering inside the lock protected\nsection does not matter. Because other threads cannot take the lock\nuntil global cache has been updated. Thus, in out of order platform,\neven if other agents firstly observe updated dev_gen but global does\nnot update, they also have to wait the lock. As a result, it is\nunnecessary to add a wmb between global cache rebuilding and updating\nthe dev_gen to keep the memory store order.\n\n2. Store-Release of unlock provides the implicit wmb at the level\nvisible by software. This makes 'rebuilding global cache' and 'updating\ndev_gen' be observed before local_cache starts to be updated by other\nagents. Thus, wmb after 'updating dev_gen' can be removed.\n\nSuggested-by: Ruifeng Wang <ruifeng.wang@arm.com>\nSigned-off-by: Feifei Wang <feifei.wang2@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n drivers/net/mlx5/mlx5_mr.c | 22 ++++++----------------\n 1 file changed, 6 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex e791b6338d..0c5403e493 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -107,18 +107,13 @@ mlx5_mr_mem_event_free_cb(struct mlx5_dev_ctx_shared *sh,\n \tif (rebuild) {\n \t\tmlx5_mr_rebuild_cache(&sh->share_cache);\n \t\t/*\n-\t\t * Flush local caches by propagating invalidation across cores.\n-\t\t * rte_smp_wmb() is enough to synchronize this event. If one of\n-\t\t * freed memsegs is seen by other core, that means the memseg\n-\t\t * has been allocated by allocator, which will come after this\n-\t\t * free call. Therefore, this store instruction (incrementing\n-\t\t * generation below) will be guaranteed to be seen by other core\n-\t\t * before the core sees the newly allocated memory.\n+\t\t * No explicit wmb is needed after updating dev_gen due to\n+\t\t * store-release ordering in unlock that provides the\n+\t\t * implicit barrier at the software visible level.\n \t\t */\n \t\t++sh->share_cache.dev_gen;\n \t\tDRV_LOG(DEBUG, \"broadcasting local cache flush, gen=%d\",\n \t\t sh->share_cache.dev_gen);\n-\t\trte_smp_wmb();\n \t}\n \trte_rwlock_write_unlock(&sh->share_cache.rwlock);\n }\n@@ -411,18 +406,13 @@ mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr,\n \t (void *)mr);\n \tmlx5_mr_rebuild_cache(&sh->share_cache);\n \t/*\n-\t * Flush local caches by propagating invalidation across cores.\n-\t * rte_smp_wmb() is enough to synchronize this event. If one of\n-\t * freed memsegs is seen by other core, that means the memseg\n-\t * has been allocated by allocator, which will come after this\n-\t * free call. Therefore, this store instruction (incrementing\n-\t * generation below) will be guaranteed to be seen by other core\n-\t * before the core sees the newly allocated memory.\n+\t * No explicit wmb is needed after updating dev_gen due to\n+\t * store-release ordering in unlock that provides the\n+\t * implicit barrier at the software visible level.\n \t */\n \t++sh->share_cache.dev_gen;\n \tDRV_LOG(DEBUG, \"broadcasting local cache flush, gen=%d\",\n \t sh->share_cache.dev_gen);\n-\trte_smp_wmb();\n \trte_rwlock_read_unlock(&sh->share_cache.rwlock);\n \treturn 0;\n }\n", "prefixes": [ "v3", "2/2" ] }